{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,8,17]],"date-time":"2023-08-17T00:07:45Z","timestamp":1692230865579},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"9","license":[{"start":{"date-parts":[[2020,8,9]],"date-time":"2020-08-09T00:00:00Z","timestamp":1596931200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2020,8,9]],"date-time":"2020-08-09T00:00:00Z","timestamp":1596931200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2020,9]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>High Level Synthesis (HLS) tools enable application domain experts to implement applications and algorithms on FPGAs. The majority of present FPGA applications is following a stream processing model which is almost entirely implemented statically and not exploiting the benefits enabled by partial reconfiguration. In this paper, we propose a generic approach for implementing and using partial reconfiguration through an HLS design flow for Maxeler platforms. Our flow extracts HLS generated HDL code from the Maxeler compilation process in order to implement a static FPGA infrastructure as well as run-time reconfigurable stream processing modules. As a distinct feature, our infrastructure can accommodate multiple partial modules in a pipeline daisy-chained manner, which aligns directly to Maxeler\u2019s dataflow programming paradigm. The benefits of the proposed flow are demonstrated by a case study of a dynamically reconfigurable video processing pipeline delivering 6.4GB\/s throughput.<\/jats:p>","DOI":"10.1007\/s11265-020-01545-y","type":"journal-article","created":{"date-parts":[[2020,8,9]],"date-time":"2020-08-09T22:02:10Z","timestamp":1597010530000},"page":"887-905","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Enabling Dynamic System Integration on Maxeler HLS Platforms"],"prefix":"10.1007","volume":"92","author":[{"given":"Charalampos","family":"Kritikakis","sequence":"first","affiliation":[]},{"given":"Dirk","family":"Koch","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,8,9]]},"reference":[{"key":"1545_CR1","unstructured":"Sunway taihulight supercomputer (2017) https:\/\/www.top500.org\/system\/178764."},{"key":"1545_CR2","doi-asserted-by":"crossref","unstructured":"DeHon, A., & et al. (1999). Balancing interconnect and computation in a reconfigurable computing array (or, why you don\u2019t really want 100% LUT utilization). In ACM\/SIGDA.","DOI":"10.1145\/296399.296431"},{"key":"1545_CR3","unstructured":"Baidu (2015) https:\/\/www.bdti.com\/InsideDSP\/2015\/01\/22\/Xilinx."},{"key":"1545_CR4","unstructured":"Amazon f1 instances, https:\/\/aws.amazon.com\/ec2\/instance-types\/f1\/."},{"key":"1545_CR5","unstructured":"Alibaba cloud services, https:\/\/www.alibabacloud.com\/."},{"key":"1545_CR6","unstructured":"Microsoft azure, https:\/\/azure.microsoft.com\/."},{"key":"1545_CR7","unstructured":"Wirbel, L. (2014). Xilinx SDAccel."},{"key":"1545_CR8","doi-asserted-by":"crossref","unstructured":"Stone, J.E., & et al. (2010). OpenCL: A parallel programming standard for heterogeneous computing systems. Computing in Science & Engineering.","DOI":"10.1109\/MCSE.2010.69"},{"key":"1545_CR9","doi-asserted-by":"crossref","unstructured":"Sohanghpurwala, A.A., & et al. (2011). OpenPR: An open-source partial-reconfiguration toolkit for Xilinx FPGAs. In (IPDPSW).","DOI":"10.1109\/IPDPS.2011.146"},{"key":"1545_CR10","doi-asserted-by":"crossref","unstructured":"Beckhoff Christian et al. (2012). GoAhead: A partial reconfiguration framework. In (FCCM).","DOI":"10.1109\/FCCM.2012.17"},{"key":"1545_CR11","unstructured":"Jensen, J.J. (2012). Reconfigurable FPGA accelerator for databases. Master\u2019s thesis University of Oslo."},{"key":"1545_CR12","doi-asserted-by":"crossref","unstructured":"Cattaneo, R., & et al. (2013). Runtime adaptation on dataflow HPC platforms. In 2013 NASA\/ESA AHS 2013. Torino.","DOI":"10.1109\/AHS.2013.6604230"},{"key":"1545_CR13","doi-asserted-by":"crossref","unstructured":"Lindtjorn, O., & et al. (2011). Beyond traditional microprocessors for geoscience high-performance computing applications.","DOI":"10.1109\/MM.2011.17"},{"key":"1545_CR14","doi-asserted-by":"crossref","unstructured":"Smaragdos Georgios et al. (2014). FPGA-based biophysically-meaningful modeling of olivocerebellar neurons. In FPGA.","DOI":"10.1145\/2554688.2554790"},{"key":"1545_CR15","doi-asserted-by":"crossref","unstructured":"Wenlai Zhao et al. (2016). F-CNN: An FPGA-based framework for training convolutional neural networks. In ASAP.","DOI":"10.1109\/ASAP.2016.7760779"},{"key":"1545_CR16","unstructured":"Maxeler app gallery, http:\/\/appgallery.maxeler.com\/."},{"key":"1545_CR17","unstructured":"Technologies, M. (2014). Multiscale dataflow programing."},{"key":"1545_CR18","doi-asserted-by":"crossref","unstructured":"Beckhoff, C., & et al. (2013). Automatic floorplanning and interface synthesis of island style reconfigurable systems with GoAhead. In ARCS (pp. 303\u2013316): Springer.","DOI":"10.1007\/978-3-642-36424-2_26"},{"key":"1545_CR19","unstructured":"Pham, K.D., & et al. (2017). BITMAN: A tool and API for FPGA bitstream manipulations. In DATE (pp. 894\u2013897)."},{"key":"1545_CR20","doi-asserted-by":"crossref","unstructured":"Grigore, N.B., & et al. (2018). HLS enabled partially reconfigurable module implementation In ARCS (pp. 269\u2013282).","DOI":"10.1007\/978-3-319-77610-1_20"},{"key":"1545_CR21","unstructured":"Example video, https:\/\/youtu.be\/vgVNCVeqs8M."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-020-01545-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11265-020-01545-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-020-01545-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,8]],"date-time":"2021-08-08T23:33:18Z","timestamp":1628465598000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11265-020-01545-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8,9]]},"references-count":21,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2020,9]]}},"alternative-id":["1545"],"URL":"https:\/\/doi.org\/10.1007\/s11265-020-01545-y","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,8,9]]},"assertion":[{"value":"29 November 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 March 2020","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"5 May 2020","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"9 August 2020","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}