{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T15:27:29Z","timestamp":1759332449413,"version":"3.37.3"},"reference-count":64,"publisher":"Springer Science and Business Media LLC","issue":"9","license":[{"start":{"date-parts":[[2020,6,19]],"date-time":"2020-06-19T00:00:00Z","timestamp":1592524800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,6,19]],"date-time":"2020-06-19T00:00:00Z","timestamp":1592524800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1149539"],"award-info":[{"award-number":["CCF-1149539"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2020,9]]},"DOI":"10.1007\/s11265-020-01546-x","type":"journal-article","created":{"date-parts":[[2020,6,19]],"date-time":"2020-06-19T08:05:22Z","timestamp":1592553922000},"page":"907-929","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks"],"prefix":"10.1007","volume":"92","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7515-3525","authenticated-orcid":false,"given":"Saunak","family":"Saha","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Henry","family":"Duwe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joseph","family":"Zambreno","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2020,6,19]]},"reference":[{"issue":"10","key":"1546_CR1","doi-asserted-by":"publisher","first-page":"1537","DOI":"10.1109\/TCAD.2015.2474396","volume":"34","author":"F Akopyan","year":"2015","unstructured":"Akopyan, F., Sawada, J., Cassidy, A., Alvarez-Icaza, R., Arthur, J., Merolla, P., Imam, N., Nakamura, Y., Datta, P., Nam, G.J., & et al. (2015). Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(10), 1537\u20131557.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"1546_CR2","doi-asserted-by":"crossref","unstructured":"Allu, B., & Zhang, W. (2004). Static next sub-bank prediction for drowsy instruction cache. In Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems (pp. 124\u2013131): ACM.","DOI":"10.1145\/1023833.1023852"},{"issue":"10","key":"1546_CR3","doi-asserted-by":"publisher","first-page":"1133","DOI":"10.1097\/00004647-200110000-00001","volume":"21","author":"D Attwell","year":"2001","unstructured":"Attwell, D., & Laughlin, S.B. (2001). An energy budget for signaling in the grey matter of the brain. Journal of Cerebral Blood Flow & Metabolism, 21(10), 1133\u20131145.","journal-title":"Journal of Cerebral Blood Flow & Metabolism"},{"key":"1546_CR4","doi-asserted-by":"crossref","unstructured":"Bauer, J., Bershteyn, M., Kaplan, I., & Vyedin, P. (1998). A reconfigurable logic machine for fast event-driven simulation. In Proceedings 1998 Design and Automation Conference. 35th DAC.(Cat. No. 98CH36175) (pp. 668\u2013671): IEEE.","DOI":"10.1145\/277044.277214"},{"issue":"2","key":"1546_CR5","doi-asserted-by":"publisher","first-page":"78","DOI":"10.1147\/sj.52.0078","volume":"5","author":"LA Belady","year":"1966","unstructured":"Belady, L.A. (1966). A study of replacement algorithms for a virtual-storage computer. IBM Systems Journal, 5(2), 78\u2013101.","journal-title":"IBM Systems Journal"},{"key":"1546_CR6","doi-asserted-by":"crossref","unstructured":"Bellosa, F. (2000). The benefits of event: driven energy accounting in power-sensitive systems. In Proceedings of the 9th workshop on ACM SIGOPS European workshop: beyond the PC: new challenges for the operating system (pp. 37\u201342): ACM.","DOI":"10.1145\/566726.566736"},{"issue":"24","key":"1546_CR7","doi-asserted-by":"publisher","first-page":"10464","DOI":"10.1523\/JNEUROSCI.18-24-10464.1998","volume":"18","author":"Gq Bi","year":"1998","unstructured":"Bi, G.q., & Poo, M.m. (1998). Synaptic modifications in cultured hippocampal neurons: dependence on spike timing, synaptic strength, and postsynaptic cell type. Journal of Neuroscience, 18(24), 10464\u201310472.","journal-title":"Journal of Neuroscience"},{"key":"1546_CR8","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1109\/MCSE.2017.33","volume":"19","author":"K Boahen","year":"2017","unstructured":"Boahen, K. (2017). A neuromorph\u2019s prospectus. Computing in Science & Engineering, 19, 14\u201328.","journal-title":"Computing in Science & Engineering"},{"issue":"5","key":"1546_CR9","doi-asserted-by":"publisher","first-page":"3637","DOI":"10.1152\/jn.00686.2005","volume":"94","author":"R Brette","year":"2005","unstructured":"Brette, R., & Gerstner, W. (2005). Adaptive exponential integrate-and-fire model as an effective description of neuronal activity. Journal of Neurophysiology, 94(5), 3637\u20133642.","journal-title":"Journal of Neurophysiology"},{"key":"1546_CR10","doi-asserted-by":"crossref","unstructured":"Cassidy, A., Andreou, A.G., & Georgiou, J. (2011). Design of a one million neuron single fpga neuromorphic system for real-time multimodal scene analysis. In 2011 45Th annual conference on information sciences and systems (pp. 1\u20136): IEEE.","DOI":"10.1109\/CISS.2011.5766099"},{"key":"1546_CR11","unstructured":"Chandrasekar, K., Weis, C., Li, Y., Akesson, B., Wehn, N., & Goossens, K. (2012). Drampower: Open-source dram power & energy estimation tool. http:\/\/www.drampower.info, 22."},{"issue":"1","key":"1546_CR12","doi-asserted-by":"publisher","first-page":"127","DOI":"10.1109\/JSSC.2016.2616357","volume":"52","author":"YH Chen","year":"2016","unstructured":"Chen, Y.H., Krishna, T., Emer, J.S., & Sze, V. (2016). Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE Journal of Solid-State Circuits, 52(1), 127\u2013138.","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"1","key":"1546_CR13","doi-asserted-by":"publisher","first-page":"82","DOI":"10.1109\/MM.2018.112130359","volume":"38","author":"M Davies","year":"2018","unstructured":"Davies, M., Srinivasa, N., Lin, T.H., Chinya, G., Cao, Y., Choday, S.H., Dimou, G., Joshi, P., Imam, N., Jain, S., & et al. (2018). Loihi: a neuromorphic manycore processor with on-chip learning. IEEE Micro, 38(1), 82\u201399.","journal-title":"IEEE Micro"},{"key":"1546_CR14","doi-asserted-by":"crossref","unstructured":"Delbruck, T. (2016). Neuromorophic vision sensing and processing. In 2016 46Th european solid-state device research conference (ESSDERC) (pp. 7\u201314): IEEE.","DOI":"10.1109\/ESSDERC.2016.7599576"},{"key":"1546_CR15","doi-asserted-by":"publisher","first-page":"99","DOI":"10.3389\/fncom.2015.00099","volume":"9","author":"PU Diehl","year":"2015","unstructured":"Diehl, P.U., & Cook, M. (2015). Unsupervised learning of digit recognition using spike-timing-dependent plasticity. Frontiers in Computational Neuroscience, 9, 99.","journal-title":"Frontiers in Computational Neuroscience"},{"key":"1546_CR16","doi-asserted-by":"crossref","unstructured":"Diehl, P.U., Neil, D., Binas, J., Cook, M., Liu, S.C., & Pfeiffer, M. (2015). Fast-classifying, high-accuracy spiking deep networks through weight and threshold balancing. In 2015 International joint conference on neural networks (IJCNN) (pp. 1\u20138): IEEE.","DOI":"10.1109\/IJCNN.2015.7280696"},{"key":"1546_CR17","doi-asserted-by":"crossref","unstructured":"Duong, N., Zhao, D., Kim, T., Cammarota, R., Valero, M., & Veidenbaum, A.V. (2012). Improving cache management policies using dynamic reuse distances. In 2012 45Th annual IEEE\/ACM international symposium on microarchitecture (pp. 389\u2013400): IEEE.","DOI":"10.1109\/MICRO.2012.43"},{"key":"1546_CR18","doi-asserted-by":"crossref","unstructured":"Flautner, K., Kim, N.S., Martin, S., Blaauw, D., & Mudge, T. (2002). Drowsy caches: simple techniques for reducing leakage power. In ACM SIGARCH Computer architecture news (vol. 30, pp. 148\u2013157): IEEE computer society.","DOI":"10.1145\/545214.545232"},{"key":"1546_CR19","doi-asserted-by":"crossref","unstructured":"Gerstner, W., & Kistler, W.M. (2002). Spiking neuron models: Single neurons, populations, plasticity. Cambridge: Cambridge University Press.","DOI":"10.1017\/CBO9780511815706"},{"issue":"5951","key":"1546_CR20","doi-asserted-by":"publisher","first-page":"379","DOI":"10.1126\/science.1181936","volume":"326","author":"W Gerstner","year":"2009","unstructured":"Gerstner, W., & Naud, R. (2009). How good are neuron models? Science, 326(5951), 379\u2013380.","journal-title":"Science"},{"key":"1546_CR21","doi-asserted-by":"publisher","first-page":"26","DOI":"10.3389\/neuro.01.026.2009","volume":"3","author":"DF Goodman","year":"2009","unstructured":"Goodman, D.F., & Brette, R. (2009). The brian simulator. Frontiers in Neuroscience, 3, 26.","journal-title":"Frontiers in Neuroscience"},{"key":"1546_CR22","unstructured":"Han, S., Mao, H., & Dally, W.J. (2015). Deep compression: Compressing deep neural network with pruning, trained quantization and huffman coding coRR. arXiv:1510.00149."},{"issue":"7","key":"1546_CR23","doi-asserted-by":"publisher","first-page":"1527","DOI":"10.1162\/neco.2006.18.7.1527","volume":"18","author":"GE Hinton","year":"2006","unstructured":"Hinton, G.E., Osindero, S., & Teh, Y.W. (2006). A fast learning algorithm for deep belief nets. Neural Computation, 18(7), 1527\u20131554.","journal-title":"Neural Computation"},{"key":"1546_CR24","doi-asserted-by":"crossref","unstructured":"Hinton, G.E., Sejnowski, T.J., & Poggio, T.A. (1999). Unsupervised learning: foundations of neural computation. Cambrdige: MIT press.","DOI":"10.7551\/mitpress\/7011.001.0001"},{"issue":"4","key":"1546_CR25","doi-asserted-by":"publisher","first-page":"500","DOI":"10.1113\/jphysiol.1952.sp004764","volume":"117","author":"AL Hodgkin","year":"1952","unstructured":"Hodgkin, A.L., & Huxley, A.F. (1952). A quantitative description of membrane current and its application to conduction and excitation in nerve. The Journal of Physiology, 117(4), 500\u2013544.","journal-title":"The Journal of Physiology"},{"issue":"4","key":"1546_CR26","doi-asserted-by":"publisher","first-page":"424","DOI":"10.1113\/jphysiol.1952.sp004716","volume":"116","author":"AL Hodgkin","year":"1952","unstructured":"Hodgkin, A.L., Huxley, A.F., & Katz, B. (1952). Measurement of current-voltage relations in the membrane of the giant axon of loligo. The Journal of Physiology, 116(4), 424\u2013448.","journal-title":"The Journal of Physiology"},{"issue":"5","key":"1546_CR27","doi-asserted-by":"publisher","first-page":"1977","DOI":"10.4249\/scholarpedia.1977","volume":"2","author":"JJ Hopfield","year":"2007","unstructured":"Hopfield, J.J. (2007). Hopfield network. Scholarpedia, 2(5), 1977.","journal-title":"Scholarpedia"},{"key":"1546_CR28","doi-asserted-by":"crossref","unstructured":"Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., & Bose, P. (2004). Microarchitectural techniques for power gating of execution units. In Proceedings of the 2004 international symposium on Low power electronics and design (pp. 32\u201337): ACM.","DOI":"10.1145\/1013235.1013249"},{"issue":"1","key":"1546_CR29","first-page":"6869","volume":"18","author":"I Hubara","year":"2017","unstructured":"Hubara, I., Courbariaux, M., Soudry, D., El-Yaniv, R., & Bengio, Y. (2017). Quantized neural networks: Training neural networks with low precision weights and activations. The Journal of Machine Learning Research, 18 (1), 6869\u20136898.","journal-title":"The Journal of Machine Learning Research"},{"issue":"5","key":"1546_CR30","doi-asserted-by":"publisher","first-page":"1063","DOI":"10.1109\/TNN.2004.832719","volume":"15","author":"EM Izhikevich","year":"2004","unstructured":"Izhikevich, E.M. (2004). Which model to use for cortical spiking neurons? IEEE Transactions on Neural networks, 15(5), 1063\u20131070.","journal-title":"IEEE Transactions on Neural networks"},{"key":"1546_CR31","unstructured":"Jiang, H., Marek-Sadowska, M., & Nassif, S.R. (2005). Benefits and costs of power-gating technique. In 2005 International conference on computer design (pp. 559\u2013566): IEEE."},{"issue":"1","key":"1546_CR32","doi-asserted-by":"publisher","first-page":"31","DOI":"10.1145\/511399.511340","volume":"30","author":"S Jiang","year":"2002","unstructured":"Jiang, S., & Zhang, X. (2002). Lirs: an efficient low inter-reference recency set replacement policy to improve buffer cache performance. ACM SIGMETRICS Performance Evaluation Review, 30(1), 31\u201342.","journal-title":"ACM SIGMETRICS Performance Evaluation Review"},{"issue":"2","key":"1546_CR33","doi-asserted-by":"publisher","first-page":"959","DOI":"10.1152\/jn.00190.2004","volume":"92","author":"R Jolivet","year":"2004","unstructured":"Jolivet, R., Lewis, T.J., & Gerstner, W. (2004). Generalized integrate-and-fire models of neuronal activity approximate spike trains of a detailed model to a high degree of accuracy. Journal of Neurophysiology, 92(2), 959\u2013976.","journal-title":"Journal of Neurophysiology"},{"key":"1546_CR34","unstructured":"Jolivet, R., Rauch, A., L\u00fcscher, H. R., & Gerstner, W. (2006). Integrate-and-fire models with adaptation are good enough. In Advances in neural information processing systems (pp. 595\u2013602)."},{"key":"1546_CR35","unstructured":"Jouppi, N.P., Young, C., Patil, N., Patterson, D., Agrawal, G., Bajwa, R., Bates, S., Bhatia, S., Boden, N., Borchers, A., & et al. (2017). In-datacenter performance analysis of a tensor processing unit. In 2017 ACM\/IEEE 44Th annual international symposium on computer architecture (ISCA) (pp. 1\u201312): IEEE."},{"key":"1546_CR36","unstructured":"Jug, F. (2012). On competition and learning in cortical structures. Ph.D. thesis, ETH Zurich."},{"key":"1546_CR37","doi-asserted-by":"crossref","unstructured":"Kaxiras, S., Hu, Z., & Martonosi, M. (2001). Cache decay: exploiting generational behavior to reduce cache leakage power. In Proceedings 28th annual international symposium on computer architecture (pp. 240\u2013251): IEEE.","DOI":"10.1145\/384285.379268"},{"key":"1546_CR38","doi-asserted-by":"crossref","unstructured":"Khan, S.M., Tian, Y., & Jimenez, D.A. (2010). Sampling dead block prediction for last-level caches. In Proceedings of the 2010 43rd Annual IEEE\/ACM International Symposium on Microarchitecture (pp. 175\u2013186): IEEE Computer Society.","DOI":"10.1109\/MICRO.2010.24"},{"issue":"1","key":"1546_CR39","doi-asserted-by":"publisher","first-page":"45","DOI":"10.1109\/LCA.2015.2414456","volume":"15","author":"Y Kim","year":"2015","unstructured":"Kim, Y., Yang, W., & Mutlu, O. (2015). Ramulator: a fast and extensible dram simulator. IEEE Computer Architecture Letters, 15(1), 45\u201349.","journal-title":"IEEE Computer Architecture Letters"},{"issue":"4","key":"1546_CR40","first-page":"38","volume":"11","author":"Y Kim","year":"2015","unstructured":"Kim, Y., Zhang, Y., & Li, P. (2015). A reconfigurable digital neuromorphic processor with memristive synaptic crossbar for cognitive computing. ACM Journal on Emerging Technologies in Computing Systems (JETC), 11(4), 38.","journal-title":"ACM Journal on Emerging Technologies in Computing Systems (JETC)"},{"key":"1546_CR41","unstructured":"Koch, C., & Segev, I. (1998). Methods in neuronal modeling: from ions to networks. Cambridge: MIT press."},{"key":"1546_CR42","unstructured":"LeCun, Y., Cortes, C., & Burges, C. (2010). Mnist handwritten digit database at&t labs."},{"key":"1546_CR43","doi-asserted-by":"crossref","unstructured":"Li, S., Chen, K., Ahn, J.H., Brockman, J.B., & Jouppi, N.P. (2011). Cacti-p: Architecture-level modeling for sram-based structures with advanced leakage reduction techniques. In Proceedings of the International Conference on Computer-Aided Design (pp. 694\u2013701): IEEE Press.","DOI":"10.1109\/ICCAD.2011.6105405"},{"key":"1546_CR44","doi-asserted-by":"crossref","unstructured":"Li, Y., & Pedram, A. (2017). Caterpillar: Coarse grain reconfigurable architecture for accelerating the training of deep neural networks. In 2017 IEEE 28Th international conference on application-specific systems, architectures and processors (ASAP) (pp. 1\u201310): IEEE.","DOI":"10.1109\/ASAP.2017.7995252"},{"key":"1546_CR45","doi-asserted-by":"publisher","first-page":"11","DOI":"10.1016\/j.neucom.2016.12.038","volume":"234","author":"W Liu","year":"2017","unstructured":"Liu, W., Wang, Z., Liu, X., Zeng, N., Liu, Y., & Alsaadi, F.E. (2017). A survey of deep neural network architectures and their applications. Neurocomputing, 234, 11\u201326.","journal-title":"Neurocomputing"},{"key":"1546_CR46","doi-asserted-by":"publisher","first-page":"76","DOI":"10.1038\/scientificamerican0591-76","volume":"264","author":"MA Mahowald","year":"1991","unstructured":"Mahowald, M.A., & Mead, C. (1991). The silicon retina. Scientific American, 264, 76\u201382.","journal-title":"Scientific American"},{"issue":"10","key":"1546_CR47","doi-asserted-by":"publisher","first-page":"1629","DOI":"10.1109\/5.58356","volume":"78","author":"C Mead","year":"1990","unstructured":"Mead, C. (1990). Neuromorphic electronic systems. Proceedings of the IEEE, 78(10), 1629\u20131636.","journal-title":"Proceedings of the IEEE"},{"key":"1546_CR48","unstructured":"Moerland, P., & Fiesler, E. (1996). Hardware-friendly learning algorithms for neural networks: an overview. In Proceedings of Fifth International Conference on Microelectronics for neural networks (pp. 117\u2013124): IEEE."},{"issue":"1","key":"1546_CR49","doi-asserted-by":"publisher","first-page":"144","DOI":"10.1109\/JPROC.2018.2881432","volume":"107","author":"A Neckar","year":"2019","unstructured":"Neckar, A., Fok, S., Benjamin, B.V., Stewart, T.C., Oza, N.N., Voelker, A.R., Eliasmith, C., Manohar, R., & Boahen, K. (2019). Braindrop: a mixed-signal neuromorphic architecture with a dynamical systems-based programming model. Proceedings of the IEEE, 107(1), 144\u2013164.","journal-title":"Proceedings of the IEEE"},{"issue":"12","key":"1546_CR50","doi-asserted-by":"publisher","first-page":"2621","DOI":"10.1109\/TVLSI.2013.2294916","volume":"22","author":"D Neil","year":"2014","unstructured":"Neil, D., & Liu, S.C. (2014). Minitaur, an event-driven fpga-based spiking network accelerator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(12), 2621\u20132628.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"1546_CR51","first-page":"178","volume":"7","author":"P O\u2019Connor","year":"2013","unstructured":"O\u2019Connor, P., Neil, D., Liu, S.C., Delbruck, T., & Pfeiffer, M. (2013). Real-time classification and sensor fusion with a spiking deep belief network. Frontiers in Neuroscience, 7, 178.","journal-title":"Frontiers in Neuroscience"},{"key":"1546_CR52","doi-asserted-by":"crossref","unstructured":"Podili, A., Zhang, C., & Prasanna, V. (2017). Fast and efficient implementation of convolutional neural networks on fpga. In 2017 IEEE 28Th international conference on application-specific systems, architectures and processors (ASAP) (pp. 11\u201318): IEEE.","DOI":"10.1109\/ASAP.2017.7995253"},{"key":"1546_CR53","doi-asserted-by":"crossref","unstructured":"Powell, M., Yang, S.H., Falsafi, B., Roy, K., & Vijaykumar, T. (2000). Gated-v dd: a circuit technique to reduce leakage in deep-submicron cache memories. In Proceedings of the 2000 international symposium on Low power electronics and design (pp. 90\u201395): ACM.","DOI":"10.1145\/344166.344526"},{"key":"1546_CR54","doi-asserted-by":"publisher","first-page":"141","DOI":"10.3389\/fnins.2015.00141","volume":"9","author":"N Qiao","year":"2015","unstructured":"Qiao, N., Mostafa, H., Corradi, F., Osswald, M., Stefanini, F., Sumislawska, D., & Indiveri, G. (2015). A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128k synapses. Frontiers in Neuroscience, 9, 141.","journal-title":"Frontiers in Neuroscience"},{"issue":"2","key":"1546_CR55","doi-asserted-by":"publisher","first-page":"381","DOI":"10.1145\/1273440.1250709","volume":"35","author":"MK Qureshi","year":"2007","unstructured":"Qureshi, M.K., Jaleel, A., Patt, Y.N., Steely, S.C., & Emer, J. (2007). Adaptive insertion policies for high performance caching. ACM SIGARCH Computer Architecture News, 35(2), 381\u2013391.","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"1546_CR56","doi-asserted-by":"crossref","unstructured":"Rumelhart, D.E., Hinton, G.E., & Williams, R.J. (1985). Learning internal representations by error propagation. Technical report. California Univ San Diego La Jolla Inst for Cognitive Science.","DOI":"10.21236\/ADA164453"},{"key":"1546_CR57","unstructured":"Schuman, C.D., Potok, T.E., Patton, R.M., Birdwell, J.D., Dean, M.E., Rose, G.S., & Plank, J.S. (2017). A survey of neuromorphic computing and neural networks in hardware. arXiv:1705.06963."},{"key":"1546_CR58","unstructured":"Shepherd, G.M. (2003). The synaptic organization of the brain. Oxford: Oxford University Press."},{"issue":"6","key":"1546_CR59","doi-asserted-by":"publisher","first-page":"444","DOI":"10.1109\/TBCAS.2009.2027127","volume":"3","author":"B Wen","year":"2009","unstructured":"Wen, B., & Boahen, K. (2009). A silicon cochlea with active coupling. IEEE Transactions on Biomedical Circuits and Systems, 3(6), 444\u2013455.","journal-title":"IEEE Transactions on Biomedical Circuits and Systems"},{"key":"1546_CR60","doi-asserted-by":"crossref","unstructured":"Wijeratne, S., Jayaweera, S., Dananjaya, M., & Pasqual, A. (2018). Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutiosnal neural networks. In 2018 IEEE 29Th international conference on application-specific systems, architectures and processors (ASAP) (pp. 1\u20137): IEEE.","DOI":"10.1109\/ASAP.2018.8445087"},{"key":"1546_CR61","doi-asserted-by":"crossref","unstructured":"Yu, T., Park, J., Joshi, S., & Maier, C. (2012). Cauwenberghs, g.: 65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing. In 2012 IEEE Biomedical circuits and systems conference (bioCAS) (pp. 21\u201324): IEEE.","DOI":"10.1109\/BioCAS.2012.6418479"},{"key":"1546_CR62","doi-asserted-by":"crossref","unstructured":"Zhao, R., Liu, S., Ng, H.C., Wang, E., Davis, J.J., Niu, X., Wang, X., Shi, H., Constantinides, G.A., Cheung, P.Y., & et al. (2018). Hardware compilation of deep neural networks: an overview. In 2018 IEEE 29Th international conference on application-specific systems, architectures and processors (ASAP) (pp. 1\u20138): IEEE.","DOI":"10.1109\/ASAP.2018.8445088"},{"key":"1546_CR63","unstructured":"Zhao, W., Fu, H., Luk, W., Yu, T., Wang, S., Feng, B., Ma, Y., & Yang, G. (2016). F-cnn: an fpga-based framework for training convolutional neural networks. In 2016 IEEE 27Th international conference on application-specific systems, architectures and processors (ASAP) (pp. 107\u2013114): IEEE."},{"issue":"3","key":"1546_CR64","doi-asserted-by":"publisher","first-page":"347","DOI":"10.1145\/860176.860181","volume":"2","author":"H Zhou","year":"2003","unstructured":"Zhou, H., Toburen, M.C., Rotenberg, E., & Conte, T. M. (2003). Adaptive mode control: a static-power-efficient cache design. ACM Transactions on Embedded Computing Systems (TECS), 2(3), 347\u2013372.","journal-title":"ACM Transactions on Embedded Computing Systems (TECS)"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-020-01546-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11265-020-01546-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-020-01546-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,18]],"date-time":"2021-06-18T23:59:17Z","timestamp":1624060757000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11265-020-01546-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,6,19]]},"references-count":64,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2020,9]]}},"alternative-id":["1546"],"URL":"https:\/\/doi.org\/10.1007\/s11265-020-01546-x","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2020,6,19]]},"assertion":[{"value":"30 November 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"17 March 2020","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"5 May 2020","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"19 June 2020","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}