{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T02:03:51Z","timestamp":1771466631500,"version":"3.50.1"},"reference-count":51,"publisher":"Springer Science and Business Media LLC","issue":"11","license":[{"start":{"date-parts":[[2020,7,9]],"date-time":"2020-07-09T00:00:00Z","timestamp":1594252800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2020,7,9]],"date-time":"2020-07-09T00:00:00Z","timestamp":1594252800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"funder":[{"DOI":"10.13039\/100011273","name":"FP7 Information and Communication Technologies","doi-asserted-by":"publisher","award":["269921"],"award-info":[{"award-number":["269921"]}],"id":[{"id":"10.13039\/100011273","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100011273","name":"FP7 Information and Communication Technologies","doi-asserted-by":"publisher","award":["243914"],"award-info":[{"award-number":["243914"]}],"id":[{"id":"10.13039\/100011273","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100011273","name":"FP7 Information and Communication Technologies","doi-asserted-by":"publisher","award":["604102"],"award-info":[{"award-number":["604102"]}],"id":[{"id":"10.13039\/100011273","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100010664","name":"H2020 Future and Emerging Technologies","doi-asserted-by":"publisher","award":["720270"],"award-info":[{"award-number":["720270"]}],"id":[{"id":"10.13039\/100010664","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100010664","name":"H2020 Future and Emerging Technologies","doi-asserted-by":"publisher","award":["785907"],"award-info":[{"award-number":["785907"]}],"id":[{"id":"10.13039\/100010664","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2020,11]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.<\/jats:p>","DOI":"10.1007\/s11265-020-01558-7","type":"journal-article","created":{"date-parts":[[2020,7,9]],"date-time":"2020-07-09T08:08:43Z","timestamp":1594282123000},"page":"1277-1292","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":40,"title":["Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System"],"prefix":"10.1007","volume":"92","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3955-4815","authenticated-orcid":false,"given":"Andreas","family":"Gr\u00fcbl","sequence":"first","affiliation":[]},{"given":"Sebastian","family":"Billaudelle","sequence":"additional","affiliation":[]},{"given":"Benjamin","family":"Cramer","sequence":"additional","affiliation":[]},{"given":"Vitali","family":"Karasenko","sequence":"additional","affiliation":[]},{"given":"Johannes","family":"Schemmel","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,7,9]]},"reference":[{"key":"1558_CR1","doi-asserted-by":"crossref","unstructured":"Aamir, S.A., M\u00fcller, P., Kriener, L., Kiene, G., Schemmel, J., & Meier, K. (2017). From lif to adex neuron models: Accelerated analog 65 nm cmos implementation. In IEEE Biomedical Circuits and Systems Conference (BioCAS) (pp. 1\u20134): IEEE.","DOI":"10.1109\/BIOCAS.2017.8325167"},{"issue":"5","key":"1558_CR2","doi-asserted-by":"publisher","first-page":"1027","DOI":"10.1109\/TBCAS.2018.2848203","volume":"12","author":"SA Aamir","year":"2018","unstructured":"Aamir, S.A., Muller\u0308, P., Kiene, G., Kriener, L., Stradmann, Y., Grubl\u0308, A., Schemmel, J., & Meier, K. (2018). A mixed-signal structured adex neuron for accelerated neuromorphic cores. IEEE Transactions on Biomedical Circuits and Systems, 12(5), 1027\u20131037. https:\/\/doi.org\/10.1109\/TBCAS.2018.2848203.","journal-title":"IEEE Transactions on Biomedical Circuits and Systems"},{"issue":"12","key":"1558_CR3","doi-asserted-by":"publisher","first-page":"4299","DOI":"10.1109\/TCSI.2018.2840718","volume":"65","author":"SA Aamir","year":"2018","unstructured":"Aamir, S.A., Stradmann, Y., Muller\u0308, P., Pehle, C., Hartel, A., Grubl\u0308, A., Schemmel, J., & Meier, K. (2018). An accelerated lif neuronal network array for a large-scale mixed-signal neuromorphic architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(12), 4299\u20134312. https:\/\/doi.org\/10.1109\/TCSI.2018.2840718.","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"key":"1558_CR4","doi-asserted-by":"crossref","unstructured":"Abrahams, M., & Barkley, J. (1998). Rtl verification strategies. In Wescon\/98. Conference Proceedings (Cat. No. 98CH36265), IEEE (pp. 130\u2013134).","DOI":"10.1109\/WESCON.1998.716434"},{"issue":"10","key":"1558_CR5","doi-asserted-by":"publisher","first-page":"1537","DOI":"10.1109\/TCAD.2015.2474396","volume":"34","author":"F Akopyan","year":"2015","unstructured":"Akopyan, F., Sawada, J., Cassidy, A., Alvarez-Icaza, R., Arthur, J., Merolla, P., Imam, N., Nakamura, Y., Datta, P., Nam, G., Taba, B., Beakes, M., Brezzo, B., Kuang, J.B., Manohar, R., Risk, W.P., Jackson, B., & Modha, D.S. (2015). Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(10), 1537\u20131557. https:\/\/doi.org\/10.1109\/TCAD.2015.2474396.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"1558_CR6","unstructured":"Bellec, G., Salaj, D., Subramoney, A., Legenstein, R., & Maass, W. (2018). Long short-term memory and learning-to-learn in networks of spiking neurons, In: Advances in Neural Information Processing Systems (pp. 787\u2013797)."},{"key":"1558_CR7","unstructured":"Bellec, G., Scherr, F., Hajek, E., Salaj, D., Legenstein, R., & Maass, W. (2019). Biologically inspired alternatives to backpropagation through time for learning in recurrent neural nets. arXiv:1901.09049."},{"key":"1558_CR8","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-93820-2","volume-title":"Static Timing Analysis for Nanometer Designs - A Practical Approach","author":"J Bhasker","year":"2009","unstructured":"Bhasker, J., & Chadha, R. (2009). Static Timing Analysis for Nanometer Designs - A Practical Approach. US: Springer. https:\/\/doi.org\/10.1007\/978-0-387-93820-2."},{"key":"1558_CR9","doi-asserted-by":"crossref","unstructured":"Bohnstingl, T., Scherr, F., Pehle, C., Meier, K., & Maass, W. (2019). Neuromorphic hardware learns to learn. Frontiers in neuroscience 13.","DOI":"10.3389\/fnins.2019.00483"},{"key":"1558_CR10","unstructured":"Cadence Design Systems: OCEAN Reference(2018)."},{"key":"1558_CR11","unstructured":"Cadence Design Systems: Virtuoso Analog Design Environment XL User Guide (2019)."},{"key":"1558_CR12","doi-asserted-by":"crossref","unstructured":"Cramer, B., Stradmann, Y., Schemmel, J., & Zenke, F. (2019). The heidelberg spiking datasets for the systematic evaluation of spiking neural networks. arXiv:1910.07407.","DOI":"10.1109\/TNNLS.2020.3044364"},{"key":"1558_CR13","doi-asserted-by":"crossref","unstructured":"Cramer, B., St\u00f6ckel, D., Kreft, M., Schemmel, J., Meier, K., & Priesemann, V. (2019). Control of criticality and computation in spiking neuromorphic networks with plasticity.","DOI":"10.1038\/s41467-020-16548-3"},{"key":"1558_CR14","doi-asserted-by":"publisher","first-page":"1161","DOI":"10.1136\/bmj.2.3859.1161","volume":"2","author":"H Dale","year":"1934","unstructured":"Dale, H. (1934). Pharmacology and nerve endings. British medical journal, 2, 1161\u20131163.","journal-title":"British medical journal"},{"issue":"1","key":"1558_CR15","doi-asserted-by":"publisher","first-page":"82","DOI":"10.1109\/MM.2018.112130359","volume":"38","author":"M Davies","year":"2018","unstructured":"Davies, M., Srinivasa, N., Lin, T., Chinya, G., Cao, Y., Choday, S.H., Dimou, G., Joshi, P., Imam, N., Jain, S., Liao, Y., Lin, C., Lines, A., Liu, R., Mathaikutty, D., McCoy, S., Paul, A., Tse, J., Venkataramanan, G., Weng, Y., Wild, A., Yang, Y., & Wang, H. (2018). Loihi: A neuromorphic manycore processor with on-chip learning. IEEE Micro, 38(1), 82\u201399. https:\/\/doi.org\/10.1109\/MM.2018.112130359.","journal-title":"IEEE Micro"},{"key":"1558_CR16","doi-asserted-by":"publisher","unstructured":"Diehl, P.U., & Cook, M. (2014). Efficient implementation of stdp rules on spinnaker neuromorphic hardware. In 2014 International Joint Conference on Neural Networks (IJCNN) (pp. 4288\u20134295), DOI https:\/\/doi.org\/10.1109\/IJCNN.2014.6889876.","DOI":"10.1109\/IJCNN.2014.6889876"},{"key":"1558_CR17","doi-asserted-by":"crossref","unstructured":"Farahini, N., Hemani, A., Lansner, A., Clermidy, F., & Svensson, C. (2014). A scalable custom simulation machine for the bayesian confidence propagation neural network model of the brain. In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 578\u2013585).","DOI":"10.1109\/ASPDAC.2014.6742953"},{"issue":"4","key":"1558_CR18","doi-asserted-by":"publisher","first-page":"e1003024","DOI":"10.1371\/journal.pcbi.1003024","volume":"9","author":"N Fr\u00e9maux","year":"2013","unstructured":"Fr\u00e9maux, N., Sprekeler, H., & Gerstner, W. (2013). Reinforcement learning using a continuous time actor-critic framework with spiking neurons. PLoS Comput Biol, 9(4), e1003024. https:\/\/doi.org\/10.1371\/journal.pcbi.1003024.","journal-title":"PLoS Comput Biol"},{"key":"1558_CR19","unstructured":"Friedmann, S. (2013). A new approach to learning in neuromorphic hardware. Ph.D. thesis, Ruprecht-Karls-Universit\u00e4t Heidelberg."},{"key":"1558_CR20","doi-asserted-by":"publisher","unstructured":"Friedmann, S. (2015). The nux processor v3.0. https:\/\/doi.org\/10.5281\/zenodo.32146. https:\/\/github.com\/electronicvisions\/nux.","DOI":"10.5281\/zenodo.32146"},{"key":"1558_CR21","unstructured":"Friedmann, S. (2015). Omnibus on-chip bus. https:\/\/github.com\/electronicvisions\/omnibus. Forked from, https:\/\/github.com\/five-elephants\/omnibus."},{"issue":"1","key":"1558_CR22","doi-asserted-by":"publisher","first-page":"128","DOI":"10.1109\/TBCAS.2016.2579164","volume":"11","author":"S Friedmann","year":"2017","unstructured":"Friedmann, S., Schemmel, J., Gr\u00fcbl, A., Hartel, A., Hock, M., & Meier, K. (2017). Demonstrating hybrid learning in a flexible neuromorphic hardware system. IEEE Transactions on Biomedical Circuits and Systems, 11(1), 128\u2013142. https:\/\/doi.org\/10.1109\/TBCAS.2016.2579164.","journal-title":"IEEE Transactions on Biomedical Circuits and Systems"},{"issue":"5","key":"1558_CR23","doi-asserted-by":"publisher","first-page":"051001","DOI":"10.1088\/1741-2560\/13\/5\/051001","volume":"13","author":"S Furber","year":"2016","unstructured":"Furber, S. (2016). Large-scale neuromorphic computing systems. Journal of Neural Engineering, 13(5), 051001. https:\/\/doi.org\/10.1088\/1741-2560\/13\/5\/051001.","journal-title":"Journal of Neural Engineering"},{"issue":"5","key":"1558_CR24","doi-asserted-by":"publisher","first-page":"652","DOI":"10.1109\/JPROC.2014.2304638","volume":"102","author":"SB Furber","year":"2014","unstructured":"Furber, S.B., Galluppi, F., Temple, S., & Plana, L.A. (2014). The spinnaker project. Proceedings of the IEEE, 102(5), 652\u2013665. https:\/\/doi.org\/10.1109\/JPROC.2014.2304638.","journal-title":"Proceedings of the IEEE"},{"issue":"6","key":"1558_CR25","doi-asserted-by":"publisher","first-page":"8427","DOI":"10.4249\/scholarpedia.8427","volume":"4","author":"W Gerstner","year":"2009","unstructured":"Gerstner, W., & Brette, R. (2009). Adaptive exponential integrate-and-fire model. Scholarpedia, 4 (6), 8427. https:\/\/doi.org\/10.4249\/scholarpedia.8427, http:\/\/www.scholarpedia.org\/article\/Adaptive_exponential_integrate-and-fire_model.","journal-title":"Scholarpedia"},{"key":"1558_CR26","unstructured":"Hartel, A. (2016). Implementation and characterization of mixed-signal neuromorphic ASICs. Ph.D. thesis, Ruprecht-Karls-Universit\u00e4t Heidelberg."},{"key":"1558_CR27","unstructured":"Hock, M. (2014). Modern semiconductor technologies for neuromorphic hardware. Ph.D. thesis, Ruprecht-Karls-Universit\u00e4t Heidelberg."},{"key":"1558_CR28","doi-asserted-by":"publisher","unstructured":"Hock, M., Hartel, A., Schemmel, J., & Meier, K. (2013). An analog dynamic memory array for neuromorphic hardware. In Circuit Theory and Design (ECCTD), 2013 European Conference on (pp. 1\u20134), DOI https:\/\/doi.org\/10.1109\/ECCTD.2013.6662229, (to appear in print).","DOI":"10.1109\/ECCTD.2013.6662229"},{"issue":"3","key":"1558_CR29","doi-asserted-by":"publisher","first-page":"566","DOI":"10.1109\/TVLSI.2012.2187224","volume":"21","author":"S Hoppner","year":"2013","unstructured":"Hoppner, S., Eisenreich, H., Henker, S., Walter, D., Ellguth, G., & Schuffny, R. (2013). A compact clock generator for heterogeneous gals mpsocs in 65-nm cmos technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(3), 566\u2013570. https:\/\/doi.org\/10.1109\/TVLSI.2012.2187224.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"issue":"3","key":"1558_CR30","doi-asserted-by":"publisher","first-page":"90","DOI":"10.1109\/MCSE.2007.55","volume":"9","author":"JD Hunter","year":"2007","unstructured":"Hunter, J.D. (2007). Matplotlib: A 2d graphics environment. Computing in Science Engineering, 9(3), 90\u201395. https:\/\/doi.org\/10.1109\/MCSE.2007.55.","journal-title":"Computing in Science Engineering"},{"key":"1558_CR31","unstructured":"Jones, E., Oliphant, T., & Peterson, P. (2001). SciPy: Open source scientific tools for Python. http:\/\/www.scipy.org\/."},{"key":"1558_CR32","doi-asserted-by":"publisher","first-page":"1201","DOI":"10.3389\/fnins.2019.01201","volume":"13","author":"AF Kungl","year":"2019","unstructured":"Kungl, A.F., Schmitt, S., Kl\u00e4hn, J., M\u00fcller, P., Baumbach, A., Dold, D., Kugele, A., M\u00fcller, E., Koke, C., Kleider, M., Mauch, C., Breitwieser, O., Leng, L., G\u00fcrtler, N., G\u00fcttler, M., Husmann, D., Husmann, K., Hartel, A., Karasenko, V., Gr\u00fcbl, A., Schemmel, J., Meier, K., & Petrovici, M.A. (2019). Accelerated physical emulation of bayesian inference in spiking neural networks. Frontiers in Neuroscience, 13, 1201. https:\/\/doi.org\/10.3389\/fnins.2019.01201.","journal-title":"Frontiers in Neuroscience"},{"issue":"6197","key":"1558_CR33","doi-asserted-by":"publisher","first-page":"668","DOI":"10.1126\/science.1254642","volume":"345","author":"PA Merolla","year":"2014","unstructured":"Merolla, P.A., Arthur, J.V., Alvarez-Icaza, R., Cassidy, A.S., Sawada, J., Akopyan, F., Jackson, B.L., Imam, N., Guo, C., Nakamura, Y., & et al. (2014). A million spiking-neuron integrated circuit with a scalable communication network and interface. Science, 345(6197), 668\u2013673.","journal-title":"Science"},{"issue":"1","key":"1558_CR34","doi-asserted-by":"publisher","first-page":"106","DOI":"10.1109\/TBCAS.2017.2759700","volume":"12","author":"S Moradi","year":"2018","unstructured":"Moradi, S., Qiao, N., Stefanini, F., & Indiveri, G. (2018). A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (dynaps). IEEE Transactions on Biomedical Circuits and Systems, 12(1), 106\u2013122. https:\/\/doi.org\/10.1109\/TBCAS.2017.2759700.","journal-title":"IEEE Transactions on Biomedical Circuits and Systems"},{"key":"1558_CR35","unstructured":"M\u00fcller, P. (2017). Modeling and verification for a scalable neuromorphic substrate. Ph.D. thesis, Ruprecht-Karls-Universit\u00e4t Heidelberg."},{"key":"1558_CR36","unstructured":"OCP. (2009). : Open core protocol specification 3.0. http:\/\/www.ocpip.org\/home."},{"key":"1558_CR37","volume-title":"A guide to NumPy, Vol. 1","author":"TE Oliphant","year":"2006","unstructured":"Oliphant, T.E. (2006). A guide to NumPy Vol. 1. USA: Trelgol Publishing."},{"key":"1558_CR38","unstructured":"PowerISA: PowerISA version 2.03. Tech. rep., power.org (2006). Available at, http:\/\/www.power.org\/resources\/reading\/."},{"key":"1558_CR39","unstructured":"Schemmel, J., Billaudelle, S., Dauer, P., & Weis, J. (2020). Accelerated analog neuromorphic computing. arXiv:2003.11996. Cs.NE."},{"key":"1558_CR40","doi-asserted-by":"crossref","unstructured":"Schemmel, J., Br\u00fcderle, D., Gr\u00fcbl, A., Hock, M., Meier, K., & Millner, S. (2010). A wafer-scale neuromorphic hardware system for large-scale neural modeling. In Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), (pp. 1947\u20131950).","DOI":"10.1109\/ISCAS.2010.5536970"},{"key":"1558_CR41","doi-asserted-by":"crossref","unstructured":"Schemmel, J., Br\u00fcderle, D., Meier, K., & Ostendorf, B. (2007). Modeling synaptic plasticity within networks of highly accelerated I&F neurons. In Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 3367\u20133370): IEEE Press.","DOI":"10.1109\/ISCAS.2007.378289"},{"key":"1558_CR42","doi-asserted-by":"crossref","unstructured":"Schemmel, J., Gr\u00fcbl, A., Meier, K., & Muller, E. (2006). Implementing synaptic plasticity in a VLSI spiking neural network model. In Proceedings of the 2006 International Joint Conference on Neural Networks (IJCNN): IEEE Press.","DOI":"10.1109\/IJCNN.2006.246651"},{"key":"1558_CR43","doi-asserted-by":"publisher","unstructured":"Schmitt, S., Klahn\u0308, J., Bellec, G., Grubl\u0308, A., Guttler\u0308, M., Hartel, A., Hartmann, S., Husmann, D., Husmann, K., Jeltsch, S., Karasenko, V., Kleider, M., Koke, C., Kononov, A., Mauch, C., Muller\u0308, E., Muller\u0308, P., Partzsch, J., Petrovici, M.A., Schiefer, S., Scholze, S., Thanasoulis, V., Vogginger, B., Legenstein, R., Maass, W., Mayr, C., Sch\u00fcffny, R., Schemmel, J., & Meier, K. (2017). Neuromorphic hardware in the loop: Training a deep spiking network on the brainscales wafer-scale system. In 2017 International Joint Conference on Neural Networks (IJCNN) (pp. 2227\u20132234), DOI https:\/\/doi.org\/10.1109\/IJCNN.2017.7966125, (to appear in print).","DOI":"10.1109\/IJCNN.2017.7966125"},{"issue":"1","key":"1558_CR44","doi-asserted-by":"publisher","first-page":"61","DOI":"10.1016\/j.vlsi.2011.05.003","volume":"45","author":"S Scholze","year":"2012","unstructured":"Scholze, S., Eisenreich, H., H\u00f6ppner, S., Ellguth, G., Henker, S., Ander, M., H\u00e4nzsche, S., Partzsch, J., Mayr, C., & Sch\u00fcffny, R. (2012). A 32gbit\/s communication soc for a waferscale neuromorphic system. Integration, 45(1), 61\u201375. https:\/\/doi.org\/10.1016\/j.vlsi.2011.05.003http:\/\/www.sciencedirect.com\/science\/article\/pii\/S0167926011000538.","journal-title":"Integration"},{"key":"1558_CR45","unstructured":"Sutherland, S. (2004). Integrating systemc models with verilog and systemverilog models using the systemverilog direct programming interface. SNUG Europe 17."},{"key":"1558_CR46","volume-title":"Reinforcement learning: An introduction","author":"RS Sutton","year":"2018","unstructured":"Sutton, R.S., & Barto, A.G. (2018). Reinforcement learning: An introduction. Cambridge: MIT press."},{"key":"1558_CR47","unstructured":"Taiwan Semiconductor Manufacturing Company: TSMC 65nm Core Library(201)."},{"key":"1558_CR48","doi-asserted-by":"publisher","first-page":"891","DOI":"10.3389\/fnins.2018.00891","volume":"12","author":"CS Thakur","year":"2018","unstructured":"Thakur, C.S., Molin, J.L., Cauwenberghs, G., Indiveri, G., Kumar, K., Qiao, N., Schemmel, J., Wang, R., Chicca, E., Olson Hasler, J., Seo, J.s., Yu, S., Cao, Y., van Schaik, A., & Etienne-Cummings, R. (2018). Large-scale neuromorphic spiking array processors: A quest to mimic the brain. Frontiers in Neuroscience, 12, 891. https:\/\/doi.org\/10.3389\/fnins.2018.00891.","journal-title":"Frontiers in Neuroscience"},{"key":"1558_CR49","doi-asserted-by":"publisher","first-page":"719","DOI":"10.1073\/pnas.94.2.719","volume":"94","author":"M Tsodyks","year":"1997","unstructured":"Tsodyks, M., & Markram, H. (1997). The neural code between neocortical pyramidal neurons depends on neurotransmitter release probability. Proceedings of the national academy of science USA, 94, 719\u2013723.","journal-title":"Proceedings of the national academy of science USA"},{"key":"1558_CR50","doi-asserted-by":"publisher","first-page":"260","DOI":"10.3389\/fnins.2019.00260","volume":"13","author":"T Wunderlich","year":"2019","unstructured":"Wunderlich, T., Kungl, A.F., M\u00fcller, E., Hartel, A., Stradmann, Y., Aamir, S.A., Gr\u00fcbl, A., Heimbrecht, A., Schreiber, K., St\u00f6ckel, D., & et al. (2019). Demonstrating advantages of neuromorphic computation: a pilot study. Frontiers in Neuroscience, 13, 260.","journal-title":"Frontiers in Neuroscience"},{"issue":"6","key":"1558_CR51","doi-asserted-by":"publisher","first-page":"1514","DOI":"10.1162\/neco_a_01086","volume":"30","author":"F Zenke","year":"2018","unstructured":"Zenke, F., & Ganguli, S. (2018). Superspike: Supervised learning in multilayer spiking neural networks. Neural computation, 30(6), 1514\u20131541.","journal-title":"Neural computation"}],"updated-by":[{"DOI":"10.1007\/s11265-020-01584-5","type":"correction","label":"Correction","source":"publisher","updated":{"date-parts":[[2020,8,13]],"date-time":"2020-08-13T00:00:00Z","timestamp":1597276800000}}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-020-01558-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11265-020-01558-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-020-01558-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,1]],"date-time":"2022-11-01T21:01:11Z","timestamp":1667336471000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11265-020-01558-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,7,9]]},"references-count":51,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2020,11]]}},"alternative-id":["1558"],"URL":"https:\/\/doi.org\/10.1007\/s11265-020-01558-7","relation":{"correction":[{"id-type":"doi","id":"10.1007\/s11265-020-01584-5","asserted-by":"object"}]},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,7,9]]},"assertion":[{"value":"17 December 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"30 April 2020","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"20 May 2020","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"9 July 2020","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 August 2020","order":5,"name":"change_date","label":"Change Date","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"Correction","order":6,"name":"change_type","label":"Change Type","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"The article was published online with unupdated Fig.\u00a04. The original article has been corrected.","order":7,"name":"change_details","label":"Change Details","group":{"name":"ArticleHistory","label":"Article History"}}]}}