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For this context, we propose three multi-issue core designs featuring an exposed datapath architecture with high performance, while retaining energy-efficiency. These features are achieved with exploitation of instruction-level parallelism, fast branching and the use of an instruction register file. With benchmarks in control-flow and signal processing application domains we measured in the best case 64% reduced energy consumption compared to a state-of-the-art RISC core, while consuming less silicon area. A high-performance design point reaches nearly 2.6 GHz operating frequency in the best case, over 2\u00d7 improvement, while simultaneously achieving a 14% improvement in system energy-delay product.<\/jats:p>","DOI":"10.1007\/s11265-020-01578-3","type":"journal-article","created":{"date-parts":[[2020,7,26]],"date-time":"2020-07-26T00:03:32Z","timestamp":1595721812000},"page":"1057-1073","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications"],"prefix":"10.1007","volume":"92","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4438-2031","authenticated-orcid":false,"given":"Joonas","family":"Multanen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Heikki","family":"Kultala","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kati","family":"Tervo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pekka","family":"J\u00e4\u00e4skel\u00e4inen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2020,7,26]]},"reference":[{"key":"1578_CR1","unstructured":"Huawei Technologies, Anders, S., & Andrae, G. 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