{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,22]],"date-time":"2025-11-22T11:21:56Z","timestamp":1763810516744,"version":"3.37.3"},"reference-count":28,"publisher":"Springer Science and Business Media LLC","issue":"10","license":[{"start":{"date-parts":[[2021,4,12]],"date-time":"2021-04-12T00:00:00Z","timestamp":1618185600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,4,12]],"date-time":"2021-04-12T00:00:00Z","timestamp":1618185600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100001871","name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","award":["UIDB\/50021\/2020"],"award-info":[{"award-number":["UIDB\/50021\/2020"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001871","name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","award":["PTDC\/EEI-HAC\/30485\/2017"],"award-info":[{"award-number":["PTDC\/EEI-HAC\/30485\/2017"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001871","name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","award":["UIDB\/EEA\/50008\/2020"],"award-info":[{"award-number":["UIDB\/EEA\/50008\/2020"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001871","name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","award":["SFRH\/BD\/144047\/2019"],"award-info":[{"award-number":["SFRH\/BD\/144047\/2019"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2021,10]]},"DOI":"10.1007\/s11265-020-01626-y","type":"journal-article","created":{"date-parts":[[2021,4,12]],"date-time":"2021-04-12T04:02:40Z","timestamp":1618200160000},"page":"1173-1186","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["A Compute Cache System for Signal Processing Applications"],"prefix":"10.1007","volume":"93","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0038-2830","authenticated-orcid":false,"given":"Jo\u00e3o","family":"Vieira","sequence":"first","affiliation":[]},{"given":"Nuno","family":"Roma","sequence":"additional","affiliation":[]},{"given":"Gabriel","family":"Falcao","sequence":"additional","affiliation":[]},{"given":"Pedro","family":"Tom\u00e1s","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,4,12]]},"reference":[{"issue":"1","key":"1626_CR1","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1145\/216585.216588","volume":"23","author":"WA Wulf","year":"1995","unstructured":"Wulf, W.A., & McKee, S.A. (1995). Hitting the memory wall: implications of the obvious. SIGARCH Computer Architecture News, 23(1), 20\u201324.","journal-title":"SIGARCH Computer Architecture News"},{"key":"1626_CR2","doi-asserted-by":"publisher","first-page":"170864","DOI":"10.1109\/ACCESS.2019.2955864","volume":"7","author":"J Vieira","year":"2019","unstructured":"Vieira, J., Duarte, R.P., & Neto, H.C. (2019). kNN-STUFF: kNN streaming unit for Fpgas. IEEE Access, 7, 170864\u2013170877.","journal-title":"IEEE Access"},{"key":"1626_CR3","doi-asserted-by":"crossref","unstructured":"Aga, S., Jeloka, S., Subramaniyan, A., Narayanasamy, S., Blaauw, D.T., & Das, R. (2017). Compute caches. In HPCA (pp. 481\u2013492): IEEE Computer Society.","DOI":"10.1109\/HPCA.2017.21"},{"key":"1626_CR4","doi-asserted-by":"crossref","unstructured":"Vieira, J., Giacomin, E., Qureshi, Y.M., Zapater, M., Tang, X., Kvatinsky, S., Atienza, D., & Gaillardon, P. (2019). A product engine for energy-efficient execution of binary neural networks using resistive memories (pp. 160\u2013165): IEEE.","DOI":"10.1109\/VLSI-SoC.2019.8920343"},{"key":"1626_CR5","unstructured":"Ghose, S., Hsieh, K., Boroumand, A., Ausavarungnirun, R., & Mutlu, O. (2018). Enabling the adoption of processing-in-memory: challenges, mechanisms, future research directions. arXiv:1802.00320."},{"key":"1626_CR6","doi-asserted-by":"crossref","unstructured":"Kim, N.S., & Mehra, P. (2019). Practical near-data processing to evolve memory and storage devices into mainstream heterogeneous computing systems. In DAC (p. 22): ACM.","DOI":"10.1145\/3316781.3323484"},{"key":"1626_CR7","doi-asserted-by":"crossref","unstructured":"Shafiee, A., Nag, A., Muralimanohar, N., Balasubramonian, R., Strachan, J.P., Hu, M., Williams, R.S., & Srikumar, V. (2016). ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. In ISCA (pp. 14\u201326): IEEE Computer Society.","DOI":"10.1145\/3007787.3001139"},{"key":"1626_CR8","doi-asserted-by":"crossref","unstructured":"Vieira, J., Roma, N., Tom\u00e1s, P., Ienne, P., & Falcao, G. (2018). Exploiting compute caches for memory bound vector operations. In SBAC-PAD (pp. 197\u2013200): IEEE.","DOI":"10.1109\/CAHPC.2018.8645905"},{"key":"1626_CR9","doi-asserted-by":"crossref","unstructured":"Vieira, J., Roma, N., Falcao, G., & Tom\u00e1s, P. (2020). Processing convolutional neural networks on cache. In ICASSP 2020-2020 IEEE international conference on acoustics, speech and signal processing (ICASSP) (pp. 1658\u20131662): IEEE.","DOI":"10.1109\/ICASSP40776.2020.9054326"},{"key":"1626_CR10","doi-asserted-by":"crossref","unstructured":"Li, S., Niu, D., Malladi, K.T., Zheng, H., Brennan, B., & Xie, Y. (2017). DRISA: a DRAM-based reconfigurable in-situ accelerator. In MICRO (pp. 288\u2013301): ACM.","DOI":"10.1145\/3123939.3123977"},{"key":"1626_CR11","unstructured":"Seshadri, V., Lee, D., Mullins, T., Hassan, H., Boroumand, A., Kim, J., Kozuch, M.A., Mutlu, O., Gibbons, P.B., & Mowry, T.C. (2017). Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology. In MICRO (pp. 273\u2013287): ACM."},{"issue":"2","key":"1626_CR12","doi-asserted-by":"publisher","first-page":"127","DOI":"10.1109\/LCA.2015.2434872","volume":"14","author":"V Seshadri","year":"2015","unstructured":"Seshadri, V., Hsieh, K., Boroumand, A., Lee, D., Kozuch, M.A., Mutlu, O., Gibbons, P.B., & Mowry, T.C. (2015). Fast bulk bitwise AND and OR in DRAM. IEEE Computer Architecture Letters, 14(2), 127\u2013131.","journal-title":"IEEE Computer Architecture Letters"},{"key":"1626_CR13","doi-asserted-by":"crossref","unstructured":"Li, S., Xu, C., Zou, Q., Zhao, J., Lu, Y., & Xie, Y. (2016). Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. In DAC (pp. 173:1\u2013173:6): ACM.","DOI":"10.1145\/2897937.2898064"},{"key":"1626_CR14","unstructured":"Yitbarek, S.F., Yang, T., Das, R., & Austin, T.M. (2016). Exploring specialized near-memory processing for data intensive operations. In DATE (pp. 1449\u20131452): IEEE."},{"key":"1626_CR15","doi-asserted-by":"crossref","unstructured":"Chi, P., Li, S., Xu, C., Zhang, T., Zhao, J., Liu, Y., Wang, Y., & Xie, Y. (2016). PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In ISCA (pp. 27\u201339): IEEE Computer Society.","DOI":"10.1145\/3007787.3001140"},{"issue":"5","key":"1626_CR16","doi-asserted-by":"publisher","first-page":"834","DOI":"10.1109\/TCAD.2018.2824304","volume":"38","author":"M Cheng","year":"2019","unstructured":"Cheng, M., Xia, L., Zhu, Z., Cai, Y., Xie, Y., Wang, Y., & Yang, H. (2019). TIME: a training-in-memory architecture For RRAM-based deep neural networks. IEEE Trans. on CAD of Integrated Circuits and Systems, 38(5), 834\u2013847.","journal-title":"IEEE Trans. on CAD of Integrated Circuits and Systems"},{"issue":"6","key":"1626_CR17","doi-asserted-by":"publisher","first-page":"1428","DOI":"10.1109\/TPDS.2018.2791440","volume":"29","author":"Y Wang","year":"2018","unstructured":"Wang, Y., Chen, W., Yang, J., & Li, T. (2018). Towards memory-efficient allocation of CNNs on processing-in-memory architecture. IEEE Trans. Parallel Distrib. Syst., 29(6), 1428\u2013 1441.","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"1626_CR18","doi-asserted-by":"crossref","unstructured":"Subramaniyan, A., Wang, J., Balasubramanian, E.R.M., Blaauw, D.T., Sylvester, D., & Das, R. (2017). Cache automaton. In MICRO (pp. 259\u2013272): ACM.","DOI":"10.1145\/3123939.3123986"},{"key":"1626_CR19","doi-asserted-by":"crossref","unstructured":"Wang, X., Yu, J., Augustine, C., Iyer, R.R., & Das, R. (2019). Bit prudent in-cache acceleration of deep convolutional neural networks. In HPCA (pp. 81\u201393): IEEE.","DOI":"10.1109\/HPCA.2019.00029"},{"issue":"3","key":"1626_CR20","doi-asserted-by":"publisher","first-page":"11","DOI":"10.1109\/MM.2019.2908101","volume":"39","author":"C Eckert","year":"2019","unstructured":"Eckert, C., Wang, X., Wang, J., Subramaniyan, A., Sylvester, D., Blaauw, D.T., Das, R., & Iyer, R.R. (2019). Neural cache: bit-serial in-cache acceleration of deep neural networks. IEEE Micro, 39 (3), 11\u201319.","journal-title":"IEEE Micro"},{"key":"1626_CR21","doi-asserted-by":"crossref","unstructured":"Nag, A., Ramachandra, C.N., Balasubramonian, R., Stutsman, R., Giacomin, E., Kambalasubramanyam, H., & Gaillardon, P. (2019). GenCache: leveraging in-cache operators for efficient sequence alignment. In MICRO (pp. 334\u2013346): ACM.","DOI":"10.1145\/3352460.3358308"},{"key":"1626_CR22","doi-asserted-by":"crossref","unstructured":"Ahn, J., Yoo, S., Mutlu, O., & Choi, K. (2015). PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture. In ISCA (pp. 336\u2013348): ACM.","DOI":"10.1145\/2872887.2750385"},{"key":"1626_CR23","doi-asserted-by":"crossref","unstructured":"Cong, J., & Xiao, B. (2014). Minimizing computation in convolutional neural networks. In ICANN. Volume 8681 of Lecture Notes in Computer Science (pp. 281\u2013290): Springer.","DOI":"10.1007\/978-3-319-11179-7_36"},{"issue":"2","key":"1626_CR24","doi-asserted-by":"publisher","first-page":"643","DOI":"10.1109\/TCSI.2018.2872455","volume":"66-I","author":"E Giacomin","year":"2019","unstructured":"Giacomin, E., Greenberg-Toledo, T., Kvatinsky, S., & Gaillardon, P. (2019). A robust digital rram-based convolutional block for low-power image processing and learning applications. IEEE Trans. Circuits Syst. I Regul. Pap., 66-I(2), 643\u2013654.","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"1626_CR25","doi-asserted-by":"crossref","unstructured":"Pouyan, P., Amat, E., Hamdioui, S., & Rubio, A. (2016). RRAM variability and its mitigation schemes. In 2016 26th international workshop on power and timing modeling, optimization and simulation (PATMOS) (pp. 141\u2013146): IEEE.","DOI":"10.1109\/PATMOS.2016.7833679"},{"key":"1626_CR26","doi-asserted-by":"crossref","unstructured":"Liu, X., Zhou, M., Rosing, T.S., & Zhao, J. (2019). HR3AM: a heat resilient design for RRAM-based neuromorphic computing. In ISLPED (pp. 1\u20136): IEEE.","DOI":"10.1109\/ISLPED.2019.8824926"},{"key":"1626_CR27","doi-asserted-by":"crossref","unstructured":"Bo, C., Wang, K., Fox, J.J., & Skadron, K. (2016). Entity resolution acceleration using the automata processor. In BigData (pp. 311\u2013318): IEEE Computer Society.","DOI":"10.1109\/BigData.2016.7840617"},{"key":"1626_CR28","doi-asserted-by":"crossref","unstructured":"Qureshi, Y.M., Simon, W.A., Zapater, M., Atienza, D., & Olcoz, K. (2019). Gem5-X: a gem5-based system level simulation framework to optimize many-core platforms. In SpringSim (pp. 1\u201312): IEEE.","DOI":"10.23919\/SpringSim.2019.8732862"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-020-01626-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11265-020-01626-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-020-01626-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,19]],"date-time":"2021-10-19T20:25:25Z","timestamp":1634675125000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11265-020-01626-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,12]]},"references-count":28,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2021,10]]}},"alternative-id":["1626"],"URL":"https:\/\/doi.org\/10.1007\/s11265-020-01626-y","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2021,4,12]]},"assertion":[{"value":"13 July 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"3 November 2020","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"10 December 2020","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"12 April 2021","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}