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These processors exploit instruction level parallelism, while being energy efficient due to their simplistic internal structure. However, the incorporation into a complete computing system raises severe challenges at the hardware and software level. This article evaluates a CGRA integrated into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC) in detail. Besides the actual application execution performance, the practicability of the configuration toolchain is validated. Challenges of the real-world integration are discussed and practical insights are highlighted.<\/jats:p>","DOI":"10.1007\/s11265-021-01641-7","type":"journal-article","created":{"date-parts":[[2021,2,27]],"date-time":"2021-02-27T09:03:51Z","timestamp":1614416631000},"page":"463-479","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment"],"prefix":"10.1007","volume":"93","author":[{"given":"Dennis","family":"Wolf","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Engel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tajas","family":"Ruschke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Koch","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian","family":"Hochberger","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2021,2,27]]},"reference":[{"key":"1641_CR1","doi-asserted-by":"crossref","unstructured":"Chin, S. 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