{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T05:27:27Z","timestamp":1780637247051,"version":"3.54.1"},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"8","license":[{"start":{"date-parts":[[2022,4,22]],"date-time":"2022-04-22T00:00:00Z","timestamp":1650585600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2022,4,22]],"date-time":"2022-04-22T00:00:00Z","timestamp":1650585600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2020-HW-2988"],"award-info":[{"award-number":["2020-HW-2988"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2022,8]]},"DOI":"10.1007\/s11265-022-01746-7","type":"journal-article","created":{"date-parts":[[2022,4,22]],"date-time":"2022-04-22T04:08:51Z","timestamp":1650600531000},"page":"799-809","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Polynomial Multiplication Architecture with Integrated Modular Reduction for R-LWE Cryptosystems"],"prefix":"10.1007","volume":"94","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8289-2377","authenticated-orcid":false,"given":"Xinmiao","family":"Zhang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6164-1977","authenticated-orcid":false,"given":"Zheang","family":"Huai","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Keshab K.","family":"Parhi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2022,4,22]]},"reference":[{"key":"1746_CR1","unstructured":"Avanzi,\u00a0R., et al. (2019). CRYSTALS - Kyber: Algorithm specifications and supporting documentation. https:\/\/pq-crystals.org\/. Accessed 30 July 2021."},{"key":"1746_CR2","unstructured":"D\u2019Anvers,\u00a0J., et al. (2021). SABER: MLWR-based KEM. https:\/\/www.esat.kuleuven.be\/cosic\/pqcrypto\/saber\/. Accessed 30 July 2021."},{"key":"1746_CR3","doi-asserted-by":"crossref","unstructured":"Brakerrski,\u00a0Z., Gentry,\u00a0C., & Vaikunranathan,\u00a0V. (2012). Fully homomorphic encryption without bootstrapping. Proceedings of the 3rd Innovations in Theoretical Computer Science Conference,\u00a0309\u2013325.","DOI":"10.1145\/2090236.2090262"},{"key":"1746_CR4","doi-asserted-by":"crossref","unstructured":"Brakerrski,\u00a0Z., (2012). Fully homomorphic encryption without modulus switching from classical GapSVP.\u00a0Advances in Cryptology \u2013 CRYPTO\u00a0(pp. 868\u2013886).","DOI":"10.1007\/978-3-642-32009-5_50"},{"key":"1746_CR5","unstructured":"Roy,\u00a0S. S., Turan,\u00a0F., Jarvinen,\u00a0K., Vercauteren,\u00a0F., & Verbauwhede\u00a0I. (2019). FPGA-based high-performance parallel architecture for homomorphic computing on encrypted data. Proceeding of the IEEE International Symposium on High Performance Computer Architecture,\u00a0387\u2013398."},{"key":"1746_CR6","doi-asserted-by":"crossref","unstructured":"Freking,\u00a0W. L. & Parhi,\u00a0K. K. (1999). Parallel modular multiplication with application to VLSI RSA implementation. Proceeding of the IEEE International Symposium on Circuits and System,\u00a0490\u2013495.","DOI":"10.1109\/ISCAS.1999.777934"},{"key":"1746_CR7","doi-asserted-by":"crossref","unstructured":"Ding,\u00a0J. & Li,\u00a0S. (2020). A low-latency and low-cost Montgomery modular multiplier based on NLP multiplication. IEEE Transactions on Circuits and Systems-II, 67(7), 1319\u20131323.","DOI":"10.1109\/TCSII.2019.2932328"},{"issue":"9","key":"1746_CR8","doi-asserted-by":"publisher","first-page":"1562","DOI":"10.1109\/TC.2017.2686385","volume":"66","author":"SS Roy","year":"2017","unstructured":"Roy, S. S., Vercauteren, F., Vliegen, J., & Verbauwhede, I. (2017). Hardware assisted fully homomorphic function evaluation and encrypted search. IEEE Transactions on Computers, 66(9), 1562\u20131572.","journal-title":"IEEE Transactions on Computers"},{"issue":"6","key":"1746_CR9","first-page":"1509","volume":"64","author":"D Yarkin","year":"2014","unstructured":"Yarkin, D., Ozturk, E., & Sunar, B. (2014). Accelerating fully homomorphic encryption in hardware. IEEE Transactions on Computers, 64(6), 1509\u20131521.","journal-title":"IEEE Transactions on Computers"},{"key":"1746_CR10","doi-asserted-by":"crossref","unstructured":"Tan,\u00a0W., et al. (2019). An efficient polynomial multiplier architecture for the bootstrapping algorithm in a fully homomorphic encryption scheme. Proceeding of the IEEE International Conference on Signal Processing Systems,\u00a085\u201390.","DOI":"10.1109\/SiPS47522.2019.9020592"},{"key":"1746_CR11","doi-asserted-by":"crossref","unstructured":"Mert,\u00a0A. C., Ozturk,\u00a0E., & Savas,\u00a0E. (2019). Design and implementation of a fast and scalable NTT-based polynomial multiplier architecture. Proceeding of the Euromicro Conference on Digital System Design,\u00a0253\u2013260.","DOI":"10.1109\/DSD.2019.00045"},{"key":"1746_CR12","doi-asserted-by":"crossref","unstructured":"\u00a0Riazi,\u00a0M., et al. (2020). HEAX: an architecture for computing on encrypted data. Proceeding of the International Conference on Architectural Support for Programming Languages and Operating Systems,\u00a01295\u20131309.","DOI":"10.1145\/3373376.3378523"},{"key":"1746_CR13","doi-asserted-by":"crossref","unstructured":"Poppelmann,\u00a0T., & Guneysu,\u00a0T. (2012). Towards efficient arithmetic for lattice-based cryptography on reconfigurable hardware. Proceeding of the International Conference on Cryptology and Information Security in Latin America,\u00a0139\u2013158.","DOI":"10.1007\/978-3-642-33481-8_8"},{"key":"1746_CR14","doi-asserted-by":"crossref","unstructured":"Zhang, Y., et al. (2020). An efficient and parallel R-LWE cryptoprocessor. IEEE Transactions on Circuits and System-II, 67(5), 886\u2013890.","DOI":"10.1109\/TCSII.2020.2980387"},{"key":"1746_CR15","doi-asserted-by":"crossref","unstructured":"Zhang, X., & Parhi, K. K. (2021). Reduced-complexity modular polynomial multiplication for R-LWE cryptosystems. Proceeding of International Conference on Acoustics, Speech and Signal Processing,\u00a07853\u20137857.","DOI":"10.1109\/ICASSP39728.2021.9414005"},{"key":"1746_CR16","unstructured":"Karatsuba,\u00a0A. & Ofman,\u00a0Y. (1962). Multiplication of many-digital numbers by automatic computers. In\u00a0Doklady Akademii Nauk\u00a0(vol. 145, no. 2, pp. 293\u2013294). Russian Academy of Sciences."},{"issue":"1","key":"1746_CR17","doi-asserted-by":"publisher","first-page":"75","DOI":"10.1023\/A:1007901117408","volume":"17","author":"DA Parker","year":"1997","unstructured":"Parker, D. A., & Parhi, K. K. (1997). Low area\/power parallel FIR digital filter implementations. Journal of VLSI Signal Processing, 17(1), 75\u201392.","journal-title":"Journal of VLSI Signal Processing"},{"key":"1746_CR18","unstructured":"Parhi,\u00a0K. K. (1999). VLSI digital signal processing systems. John Wiley & Sons."},{"key":"1746_CR19","doi-asserted-by":"crossref","unstructured":"Cheng, C. & Parhi, K. K. (2004). Hardware efficient fast parallel FIR filter structures based on iterated short convolution. IEEE Transactions on Circuits and Systems, Part-I: Regular Papers, 51(8), 1492\u20131500.","DOI":"10.1109\/TCSI.2004.832784"},{"key":"1746_CR20","doi-asserted-by":"crossref","unstructured":"Yabuuchi, M., et al. (2014). 20nm high-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read\/write assists.\u00a0Proceeding of IEEE International Solid-State Circuits Conference,\u00a0234\u2013235.","DOI":"10.1109\/ISSCC.2014.6757414"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-022-01746-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11265-022-01746-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-022-01746-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,2]],"date-time":"2022-08-02T15:35:16Z","timestamp":1659454516000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11265-022-01746-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4,22]]},"references-count":20,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2022,8]]}},"alternative-id":["1746"],"URL":"https:\/\/doi.org\/10.1007\/s11265-022-01746-7","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,4,22]]},"assertion":[{"value":"27 August 2021","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"24 December 2021","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 February 2022","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"22 April 2022","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}