{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T14:38:32Z","timestamp":1740148712586,"version":"3.37.3"},"reference-count":12,"publisher":"Springer Science and Business Media LLC","issue":"9","license":[{"start":{"date-parts":[[2022,7,5]],"date-time":"2022-07-05T00:00:00Z","timestamp":1656979200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2022,7,5]],"date-time":"2022-07-05T00:00:00Z","timestamp":1656979200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["326384402"],"award-info":[{"award-number":["326384402"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Karlsruher Institut f\u00fcr Technologie (KIT)"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2022,9]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>Virtual FPGAs (V-FPGAs) are used as vendor-independent virtualization layers, to retrofit features which are not available on the host FPGA and to prototype novel FPGA architectures. In these usecases, the achievable clock frequencies of V-FPGA user applications are a major concern. The abstraction layer inherently induces overhead, but this aspect is reinforced by nonuniformity effects: When V-FPGA cells perform worse locally, basic architecture modeling generalizes these worst-case path delays to the whole device, limiting applications to a lower frequency than theoretically achievable. We propose three approaches to attenuate these effects: First we introduce uniformity metrics and manual V-FPGA placement strategies for more uniform placement, improving achievable frequency by 16 %. Second, we propose a framework for automated timing extraction, enabling individual characterization of each V-FPGA design. Third, after evaluating Vivado synthesis strategies, we extend the timing model for non-uniform timings, achieving improvements of up to 28 %.<\/jats:p>","DOI":"10.1007\/s11265-022-01786-z","type":"journal-article","created":{"date-parts":[[2022,7,5]],"date-time":"2022-07-05T11:09:06Z","timestamp":1657019346000},"page":"865-882","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["V-FPGAs: Increasing Performance with Manual Placement, Timing Extraction and Extended Timing Modeling"],"prefix":"10.1007","volume":"94","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1087-1814","authenticated-orcid":false,"given":"Johannes","family":"Pfau","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3100-7956","authenticated-orcid":false,"given":"Peter Wagih","family":"Zaki","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5082-5487","authenticated-orcid":false,"given":"J\u00fcrgen","family":"Becker","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2022,7,5]]},"reference":[{"key":"1786_CR1","doi-asserted-by":"publisher","unstructured":"Figuli,\u00a0P., H\u00fcbner,\u00a0M., Girardey,\u00a0R., Bapp,\u00a0F., Bruckschl\u00f6gl,\u00a0T., Thoma,\u00a0F., Henkel,\u00a0J., & Becker,\u00a0J. (2011).\u00a0A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion.\u00a0In 2011 NASA\/ESA Conference on Adaptive Hardware and Systems (AHS)\u00a0(pp. 96\u2013103).\u00a0https:\/\/doi.org\/10.1109\/AHS.2011.5963922","DOI":"10.1109\/AHS.2011.5963922"},{"key":"1786_CR2","doi-asserted-by":"publisher","unstructured":"Sidiropoulos,\u00a0H., Figuli,\u00a0P., Siozios,\u00a0K., Soudris,\u00a0D., & Becker,\u00a0J. (2013). A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization.\u00a0In 2013 23rd International Conference on Field programmable Logic and Applications\u00a0(pp. 1\u20134).\u00a0https:\/\/doi.org\/10.1109\/FPL.2013.6645564","DOI":"10.1109\/FPL.2013.6645564"},{"key":"1786_CR3","doi-asserted-by":"publisher","unstructured":"Harbaum,\u00a0T., Schade,\u00a0C., Damschen,\u00a0M., Tradowsky,\u00a0C., Bauer,\u00a0L., Henkel,\u00a0J., & Becker,\u00a0J. (2017). Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration.\u00a0In 2017 30th IEEE International System-on-Chip Conference (SOCC)\u00a0(pp. 153\u2013158).\u00a0https:\/\/doi.org\/10.1109\/SOCC.2017.8226027","DOI":"10.1109\/SOCC.2017.8226027"},{"key":"1786_CR4","doi-asserted-by":"publisher","unstructured":"Pfau,\u00a0J., Reuter,\u00a0M., Hofmann,\u00a0K., & Becker,\u00a0J. (2020).\u00a0Designing universal logic module FPGA architectures for use with ambipolar transistor technology.\u00a0In 2020 International Conference on Field-Programmable Technology (ICFPT)\u00a0(pp. 165\u2013173).\u00a0https:\/\/doi.org\/10.1109\/ICFPT51103.2020.00031","DOI":"10.1109\/ICFPT51103.2020.00031"},{"key":"1786_CR5","doi-asserted-by":"publisher","first-page":"91564","DOI":"10.1109\/ACCESS.2021.3092167","volume":"9","author":"S Rai","year":"2021","unstructured":"Rai, S., Nath, P., Rupani, A., Vishvakarma, S. K., & Kumar, A. (2021). A survey of fpga logic cell designs in the light of emerging technologies. IEEE Access, 9, 91564\u201391574. https:\/\/doi.org\/10.1109\/ACCESS.2021.3092167","journal-title":"IEEE Access"},{"key":"1786_CR6","doi-asserted-by":"crossref","unstructured":"Pfau, J., Zaki, P. W., & Becker, J. (2021). Evaluation of different manual placement strategies to ensure uniformity of the V-FPGA. In S. Derrien, F. Hannig, P. C. Diniz, & D. Chillet (Eds.), Applied Reconfigurable Computing. Architectures, Tools, and Applications (pp. 35\u201349). Springer International Publishing, Cham.","DOI":"10.1007\/978-3-030-79025-7_3"},{"key":"1786_CR7","doi-asserted-by":"publisher","unstructured":"Luu,\u00a0J., Goeders,\u00a0J., Wainberg,\u00a0M., Somerville,\u00a0A., Yu,\u00a0T., Nasartschuk,\u00a0K., Nasr,\u00a0M., Wang,\u00a0S.,\u00a0 Liu,\u00a0T., Ahmed,\u00a0N., Kent,\u00a0K. B., Anderson,\u00a0J., Rose,\u00a0J., & Betz,\u00a0V. (2014).\u00a0Vtr 7.0. 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