{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T14:44:52Z","timestamp":1751035492940,"version":"3.37.3"},"reference-count":31,"publisher":"Springer Science and Business Media LLC","issue":"7","license":[{"start":{"date-parts":[[2023,2,28]],"date-time":"2023-02-28T00:00:00Z","timestamp":1677542400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,2,28]],"date-time":"2023-02-28T00:00:00Z","timestamp":1677542400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2023,7]]},"DOI":"10.1007\/s11265-022-01832-w","type":"journal-article","created":{"date-parts":[[2023,2,28]],"date-time":"2023-02-28T03:02:32Z","timestamp":1677553352000},"page":"797-813","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Evaluation of a Modular Approach to AES Hardware Architecture and Optimization"],"prefix":"10.1007","volume":"95","author":[{"given":"Ryan","family":"Swann","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8767-390X","authenticated-orcid":false,"given":"James","family":"Stine","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2023,2,28]]},"reference":[{"key":"1832_CR1","doi-asserted-by":"crossref","unstructured":"Henzen, L., & Fichtner, W. (2010).\u00a0FPGA parallel-pipelined AES-GCM core for 100G Ethernet applications. In\u00a02010 Proceedings of ESSCIRC\u00a0(pp. 202\u2013205).","DOI":"10.1109\/ESSCIRC.2010.5619894"},{"key":"1832_CR2","unstructured":"Specification for the Advanced Encryption Standard (AES). (2001).\u00a0Federal Information Processing Standards Publication 197. http:\/\/csrc.nist.gov\/publications\/fips\/fips197\/fips-197.pdf. Accessed 16 May 2022."},{"key":"1832_CR3","doi-asserted-by":"crossref","unstructured":"Harrison, O., & Waldron, J. (2007). AES encryption implementation and analysis on commodity graphics processing units. In Cryptographic Hardware and Embedded Systems - CHES 2007 (pp. 209\u2013226). Lecture Notes in Computer Science. Springer, Berlin, Heidelberg.","DOI":"10.1007\/978-3-540-74735-2_15"},{"issue":"3","key":"1832_CR4","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1016\/0890-5401(88)90024-7","volume":"78","author":"T Itoh","year":"1988","unstructured":"Itoh, T., & Tsujii, S. (1988). A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases. Information and Computation, 78(3), 171\u2013177. https:\/\/doi.org\/10.1016\/0890-5401(88)90024-7","journal-title":"Information and Computation"},{"key":"1832_CR5","doi-asserted-by":"publisher","first-page":"191","DOI":"10.1007\/s00145-012-9124-7","volume":"2009","author":"J Boyar","year":"2009","unstructured":"Boyar, J., & Peralta, R. (2009). Logic minimization techniques with applications to cryptology. IACR Cryptology ePrint Archive, 2009, 191. https:\/\/doi.org\/10.1007\/s00145-012-9124-7","journal-title":"IACR Cryptology ePrint Archive"},{"key":"1832_CR6","doi-asserted-by":"publisher","unstructured":"Lee, R. B., & Chen,\u00a0Y-Y. (2010).\u00a0Processor accelerator for AES. In\u00a02010 IEEE 8th Symposium on Application Specific Processors (SASP) (pp. 16\u201321).\u00a0https:\/\/doi.org\/10.1109\/SASP.2010.5521153","DOI":"10.1109\/SASP.2010.5521153"},{"key":"1832_CR7","doi-asserted-by":"crossref","unstructured":"Canright, D. (2005).\u00a0A very compact S-Box for AES. In J. R. Rao, & B.\u00a0Sunar (Eds.), Cryptographic Hardware and Embedded Systems \u2013 CHES 2005\u00a0(pp. 441\u2013455). Springer, Berlin, Heidelberg.","DOI":"10.1007\/11545262_32"},{"key":"1832_CR8","doi-asserted-by":"publisher","unstructured":"Swann, R., & Stine, J. E. (2021).\u00a0A reconfigurable architecture for improvement and optimization of advanced encryption standard hardware. In\u00a02021 55th Asilomar Conference on Signals, Systems, and Computers\u00a0(pp. 1181\u20131185).\u00a0https:\/\/doi.org\/10.1109\/IEEECONF53345.2021.9723104","DOI":"10.1109\/IEEECONF53345.2021.9723104"},{"key":"1832_CR9","unstructured":"Daemen, J., & Rijmen, V. (1999).\u00a0AES Proposal: Rijndael version 2."},{"key":"1832_CR10","unstructured":"NIST Special Publication 800-20. (1999). NIST Special Publication 800-20. https:\/\/nvlpubs.nist.gov\/nistpubs\/Legacy\/SP\/nistspecialpublication800-20.pdf. Accessed 16 May 2022."},{"key":"1832_CR11","doi-asserted-by":"publisher","unstructured":"Rewagad, P., & Pawar, Y. (2013).\u00a0Use of digital signature with Diffie Hellman key exchange and AES encryption algorithm to enhance data security in cloud computing. In\u00a02013 International Conference on Communication Systems and Network Technologies (pp. 437\u2013439).\u00a0https:\/\/doi.org\/10.1109\/CSNT.2013.97","DOI":"10.1109\/CSNT.2013.97"},{"key":"1832_CR12","doi-asserted-by":"publisher","unstructured":"Digital Signature Standard (DSS). (July 2013).\u00a0Technical report. https:\/\/doi.org\/10.6028\/nist.fips.186-4","DOI":"10.6028\/nist.fips.186-4"},{"issue":"4","key":"1832_CR13","doi-asserted-by":"publisher","first-page":"322","DOI":"10.1145\/945511.945515","volume":"13","author":"P Hellekalek","year":"2003","unstructured":"Hellekalek, P., & Wegenkittl, S. (2003). Empirical evidence concerning AES. ACM Transactions on Modeling and Computer Simulation, 13(4), 322\u2013333. https:\/\/doi.org\/10.1145\/945511.945515","journal-title":"ACM Transactions on Modeling and Computer Simulation"},{"key":"1832_CR14","doi-asserted-by":"publisher","unstructured":"Attaullah, J., S. S., & Shah, T. (2017).\u00a0A novel algebraic technique for the construction of strong substitution box. Springer.\u00a0https:\/\/doi.org\/10.1007\/s11277-017-5054-x","DOI":"10.1007\/s11277-017-5054-x"},{"key":"1832_CR15","doi-asserted-by":"crossref","unstructured":"Biryukov, A., & Khovratovich, D. (2009).\u00a0Related-key cryptanalysis of the full AES-192 and AES-256. In Matsui, M. (Ed.), Advances in Cryptology \u2013 ASIACRYPT 2009\u00a0(pp. 1\u201318). Springer, Berlin, Heidelberg.","DOI":"10.1007\/978-3-642-10366-7_1"},{"key":"1832_CR16","doi-asserted-by":"publisher","unstructured":"Dworkin, M. J. (2007).\u00a0Recommendation for block cipher modes of operation. Technical report. https:\/\/doi.org\/10.6028\/nist.sp.800-38d","DOI":"10.6028\/nist.sp.800-38d"},{"key":"1832_CR17","unstructured":"Computer Security\u00a0Division, I. T. L. (2016).\u00a0Circuit Complexity: CSRC. NIST. https:\/\/csrc.nist.gov\/projects\/circuit-complexity. Accessed 16 May 2022."},{"key":"1832_CR18","doi-asserted-by":"crossref","unstructured":"Saberi, I., Shojaie, B., & Salleh, M. (2011). Enhanced key expansion for AES-256 by using even-odd method. In\u00a02011 International Conference on Research and Innovation in Information Systems (pp. 1\u20135).","DOI":"10.1109\/ICRIIS.2011.6125708"},{"key":"1832_CR19","doi-asserted-by":"crossref","unstructured":"Boyar, J., & Peralta, R. (2012).\u00a0A small depth-16 circuit for the AES s-box. In D. Gritzalis, S. Furnell, & M.\u00a0Theoharidou (Eds.) Information Security and Privacy Research (pp. 287\u2013298). Springer, Berlin, Heidelberg.","DOI":"10.1007\/978-3-642-30436-1_24"},{"key":"1832_CR20","doi-asserted-by":"publisher","unstructured":"Fiskiran, A. M., & Lee, R. B. (2005).\u00a0On-chip lookup tables for fast symmetric-key encryption. In\u00a02005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP\u201905) (pp. 356\u2013363).\u00a0https:\/\/doi.org\/10.1109\/ASAP.2005.49","DOI":"10.1109\/ASAP.2005.49"},{"key":"1832_CR21","unstructured":"Maximov, A. (2019).\u00a0AES MixColumn with 92 XOR gates. Cryptology ePrint Archive, Report 2019\/833. https:\/\/ia.cr\/2019\/833. Accessed 16 May 2022."},{"key":"1832_CR22","doi-asserted-by":"publisher","unstructured":"Sayilar, G., & Chiou, D. (2014).\u00a0Cryptoraptor: High throughput reconfigurable cryptographic processor. In\u00a02014 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) (pp. 155\u2013161).\u00a0https:\/\/doi.org\/10.1109\/ICCAD.2014.7001346","DOI":"10.1109\/ICCAD.2014.7001346"},{"issue":"3","key":"1832_CR23","doi-asserted-by":"publisher","first-page":"536","DOI":"10.1109\/TC.2011.251","volume":"62","author":"B Liu","year":"2013","unstructured":"Liu, B., & Baas, B. M. (2013). Parallel AES encryption engines for many-core processor arrays. Computers, IEEE Transactions on, 62(3), 536\u2013547. https:\/\/doi.org\/10.1109\/TC.2011.251","journal-title":"Computers, IEEE Transactions on"},{"issue":"6","key":"1832_CR24","doi-asserted-by":"publisher","first-page":"1160","DOI":"10.1016\/j.compeleceng.2011.06.003","volume":"37","author":"L Ali","year":"2011","unstructured":"Ali, L., Aris, I., Hossain, F. S., & Roy, N. (2011). Design of an ultra high speed AES processor for next generation it security. Computers and Electrical Engineering, 37(6), 1160\u20131170. https:\/\/doi.org\/10.1016\/j.compeleceng.2011.06.003","journal-title":"Computers and Electrical Engineering"},{"key":"1832_CR25","doi-asserted-by":"publisher","unstructured":"Morioka, S., & Satoh, A. (2004). A 10-gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(7), 686\u2013691.\u00a0https:\/\/doi.org\/10.1109\/TVLSI.2004.830936","DOI":"10.1109\/TVLSI.2004.830936"},{"key":"1832_CR26","doi-asserted-by":"crossref","unstructured":"Hodjat, A., & Verbauwhede, I. (2003).\u00a0Speed-area trade-off for 10 to 100 Gbits\/s throughput AES processor. In The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003\u00a0(vol. 2, pp. 2147\u20132150). IEEE.","DOI":"10.1109\/ACSSC.2003.1292360"},{"key":"1832_CR27","unstructured":"Amphion. (2002).\u00a0CS5210-40 High Performance AES Cores. Amphion."},{"key":"1832_CR28","unstructured":"AES-GCM MACsec (IEEE 802.1AE) and FC-SP Cores GCM1\/GCM2\/GCM3. (2022). https:\/\/www.ipcores.com\/macsec802.1aegcmaesipcore.htm. Accessed 16 May 2022."},{"key":"1832_CR29","doi-asserted-by":"publisher","unstructured":"Sriniwas\u00a0Shastry, P. V., Kulkarni, A., & Sutaone, M. S. (2012).\u00a0ASIC implementation of AES. In\u00a02012 Annual IEEE India Conference (INDICON) (pp. 1255\u20131259).\u00a0https:\/\/doi.org\/10.1109\/INDCON.2012.6420811","DOI":"10.1109\/INDCON.2012.6420811"},{"key":"1832_CR30","doi-asserted-by":"publisher","unstructured":"Gu\u00fcrkaynak, F. K., Burg, A., Felber, N., Fichtner, W., Gasser, D., Hug, F., & Kaeslin, H. (2004). A 2 GB\/S balanced AES crypto-chip implementation. In Proceedings of the 14th ACM Great Lakes Symposium on VLSI. GLSVLSI \u201904 (pp. 39\u201344). Association for Computing Machinery, New York, NY, USA.\u00a0https:\/\/doi.org\/10.1145\/988952.988963","DOI":"10.1145\/988952.988963"},{"key":"1832_CR31","doi-asserted-by":"publisher","unstructured":"Cao, Q., & Li, S. (2009).\u00a0A high-throughput cost-effective ASIC implementation of the AES algorithm. In\u00a02009 IEEE 8th International Conference on ASIC (pp. 805\u2013808).\u00a0https:\/\/doi.org\/10.1109\/ASICON.2009.5351572","DOI":"10.1109\/ASICON.2009.5351572"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-022-01832-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11265-022-01832-w\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-022-01832-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,29]],"date-time":"2023-09-29T08:05:54Z","timestamp":1695974754000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11265-022-01832-w"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2,28]]},"references-count":31,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2023,7]]}},"alternative-id":["1832"],"URL":"https:\/\/doi.org\/10.1007\/s11265-022-01832-w","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2023,2,28]]},"assertion":[{"value":"16 May 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"22 October 2022","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 December 2022","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"28 February 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"There are no declarations that are applicable.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflicts of Interest"}}]}}