{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,23]],"date-time":"2026-10-23T20:47:40Z","timestamp":1792788460123,"version":"4.5.0"},"reference-count":50,"publisher":"Springer Science and Business Media LLC","issue":"9","license":[{"start":{"date-parts":[[2023,4,26]],"date-time":"2023-04-26T00:00:00Z","timestamp":1682467200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2023,4,26]],"date-time":"2023-04-26T00:00:00Z","timestamp":1682467200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"funder":[{"DOI":"10.13039\/501100011688","name":"Electronic Components and Systems for European Leadership","doi-asserted-by":"publisher","award":["783162"],"award-info":[{"award-number":["783162"]}],"id":[{"id":"10.13039\/501100011688","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100011688","name":"Electronic Components and Systems for European Leadership","doi-asserted-by":"publisher","award":["826610"],"award-info":[{"award-number":["826610"]}],"id":[{"id":"10.13039\/501100011688","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100010669","name":"H2020 LEIT Information and Communication Technologies","doi-asserted-by":"publisher","award":["780788"],"award-info":[{"award-number":["780788"]}],"id":[{"id":"10.13039\/100010669","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100005642","name":"Universit\u00e0 degli Studi di Sassari","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100005642","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2023,9]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>Image and video processing are one of the main driving application fields for the latest technology advancement of computing platforms, especially considering the adoption of neural networks for classification purposes. With the advent of Cyber Physical Systems, the design of devices for efficiently executing such applications became more challenging, due to the increase of the requirements to be considered, of the functionalities to be supported, as well as to the demand for adaptivity and connectivity. Heterogeneous computing and design automation are then turning into essential. The former guarantees a variegated set of features under strict constraints (e.g., by adopting hardware acceleration), and the latter limits development time and cost (e.g., by exploiting model-based design). In this context, the literature is still lacking adequate tooling for the design and management of neural network hardware accelerators, which can be adaptable and customizable at runtime according to the user needs. In this work, a novel almost automated toolchain based on the Open Neural Network eXchange format is presented, allowing the user to shape adaptivity right on the network model and to deploy it on a runtime reconfigurable accelerator. As a proof of concept, a Convolutional Neural Network for human\/animal classification is adopted to derive a Field Programmable Gate Array accelerator capable of trading execution time for power by changing the resources involved in the computation. The resulting accelerator, when necessary, can consume 30% less power on each layer, taking about overall 8% more time to classify an image.<\/jats:p>","DOI":"10.1007\/s11265-023-01855-x","type":"journal-article","created":{"date-parts":[[2023,4,26]],"date-time":"2023-04-26T06:02:30Z","timestamp":1682488950000},"page":"1091-1113","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["An Automated Design Flow for Adaptive Neural Network Hardware Accelerators"],"prefix":"10.1007","volume":"95","author":[{"given":"Francesco","family":"Ratto","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"\u00c1ngela Porras","family":"M\u00e1inez","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0436-2706","authenticated-orcid":false,"given":"Carlo","family":"Sau","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Paolo","family":"Meloni","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gianfranco","family":"Deriu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Stefano","family":"Delucchi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Massimo","family":"Massa","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luigi","family":"Raffo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Francesca","family":"Palumbo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2023,4,26]]},"reference":[{"key":"1855_CR1","unstructured":"An FPGA \u201cCompanion\u201d in Smartphone Design - A Lattice Semiconductor White Paper. Document ID 47335 (2012-05)."},{"key":"1855_CR2","doi-asserted-by":"crossref","unstructured":"Al-Ars, Z., et\u00a0al. (2019).\u00a0The fitoptivis ECSEL project: highly efficient distributed embedded image\/video processing in cyber-physical systems. In Conference on Computing Frontiers (pp. 333\u2013338).","DOI":"10.1145\/3310273.3323437"},{"key":"1855_CR3","doi-asserted-by":"crossref","unstructured":"Pomante, L., Palumbo, F., Rinaldi, C., Valente, G., Sau, C., Fanni, T., van\u00a0der Linden, F., Basten, T., Geilen, M., Peeren, G., Kadlec, J., J\u00e4\u00e4skel\u00e4inen, P., de\u00a0Alejandro, M. M., Saarinen, J., S\u00e4ntti, T., Zedda, M. K., Sanchez, V., Goswami, D., Al-Ars, Z., & de\u00a0Beer, A. (2020).\u00a0Design and management of image processing pipelines within CPS: 2 years of experience from the fitoptivis ECSEL project. In 23rd Euromicro Conference on Digital System Design, DSD 2020, Kranj, Slovenia, August 26-28, 2020\u00a0(pp. 378\u2013385). IEEE. Retrieved April 2023, from https:\/\/www.latticesemi.com\/-\/media\/LatticeSemi\/Documents\/WhitePapers\/AG\/AnFPGACompanioninSmartphoneDesign.ashx?document_id=47335","DOI":"10.1109\/DSD51259.2020.00067"},{"key":"1855_CR4","doi-asserted-by":"publisher","unstructured":"Beaumin, C., Sentieys, O., Casseau, E., & Carer, A. (2010).\u00a0A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design. In\u00a02010 Conference on Design and Architectures for Signal and Image Processing (DASIP) (pp. 152\u2013159).\u00a0https:\/\/doi.org\/10.1109\/DASIP.2010.5706259","DOI":"10.1109\/DASIP.2010.5706259"},{"key":"1855_CR5","doi-asserted-by":"publisher","unstructured":"Fanni, T., Rodr\u00edguez, A., Sau, C., Suriano, L., Palumbo, F., Raffo, L., & de la Torre, E. (2018).\u00a0Multi-grain reconfiguration for advanced adaptivity in cyber-physical systems. In\u00a02018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) (pp. 1\u20138).\u00a0https:\/\/doi.org\/10.1109\/RECONFIG.2018.8641705","DOI":"10.1109\/RECONFIG.2018.8641705"},{"key":"1855_CR6","doi-asserted-by":"crossref","unstructured":"Wijtvliet, M., Waeijen, L., & Corporaal, H. (2016).\u00a0Coarse grained reconfigurable architectures in the past 25 years: Overview and classification. In W. A. Najjar, & A.\u00a0Gerstlauer (Eds.),\u00a0International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016\u00a0(pp. 235\u2013244). IEEE.","DOI":"10.1109\/SAMOS.2016.7818353"},{"issue":"3","key":"1855_CR7","doi-asserted-by":"publisher","first-page":"65","DOI":"10.1109\/LES.2017.2703585","volume":"9","author":"C Sau","year":"2017","unstructured":"Sau, C., Palumbo, F., Pelcat, M., Heulot, J., Nogues, E., M\u00e9nard, D., Meloni, P., & Raffo, L. (2017). Challenging the best HEVC fractional pixel FPGA interpolators with reconfigurable and multifrequency approximate computing. IEEE Embed. Syst. Lett., 9(3), 65\u201368.","journal-title":"IEEE Embed. Syst. Lett."},{"key":"1855_CR8","doi-asserted-by":"crossref","unstructured":"Palumbo, F., Sau, C., Fanni, T., & Raffo, L. (2017).\u00a0Challenging CPS trade-off adaptivity with coarse-grained reconfiguration. In A. D. Gloria (ed.) Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2017, Rome, Italy, 21-22 September 2017, extitLecture Notes in Electrical Engineering (vol. 512, pp. 57\u201363). Springer.","DOI":"10.1007\/978-3-319-93082-4_8"},{"issue":"2","key":"1855_CR9","doi-asserted-by":"publisher","first-page":"238","DOI":"10.1109\/TCAD.2014.2384517","volume":"34","author":"CM Diniz","year":"2015","unstructured":"Diniz, C. M., Shafique, M., Bampi, S., & Henkel, J. (2015). A reconfigurable hardware architecture for fractional pixel interpolation in high efficiency video coding. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(2), 238\u2013251. https:\/\/doi.org\/10.1109\/TCAD.2014.2384517","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"1855_CR10","doi-asserted-by":"crossref","unstructured":"Coutinho\u00a0Demetrios, A. M., De\u00a0Sensi, D., Lorenzon, A. F., Georgiou, K., Nunez-Yanez, J., Eder, K., Xavier-de Souza, S. (2020).\u00a0Performance and energy trade-offs for parallel applications on heterogeneous multi-processing systems. Energies, 13(9).","DOI":"10.3390\/en13092409"},{"key":"1855_CR11","doi-asserted-by":"publisher","first-page":"118707","DOI":"10.1109\/ACCESS.2020.3005202","volume":"8","author":"L Suriano","year":"2020","unstructured":"Suriano, L., Otero, A., Rodr\u00edguez, A., S\u00e1nchez-Renedo, M., & La Torre, E. D. (2020). Exploiting multi-level parallelism for run-time adaptive inverse kinematics on heterogeneous mpsocs. IEEE Access, 8, 118707\u2013118724. https:\/\/doi.org\/10.1109\/ACCESS.2020.3005202","journal-title":"IEEE Access"},{"issue":"4","key":"1855_CR12","doi-asserted-by":"publisher","first-page":"440","DOI":"10.1504\/IJCAET.2014.065419","volume":"6","author":"S Mittal","year":"2014","unstructured":"Mittal, S. (2014). A survey of techniques for improving energy efficiency in embedded computing systems. Int. J. Comput. Aided Eng. Technol., 6(4), 440\u2013459.","journal-title":"Int. J. Comput. Aided Eng. Technol."},{"issue":"1","key":"1855_CR13","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3289185","volume":"12","author":"K Guo","year":"2019","unstructured":"Guo, K., Zeng, S., Yu, J., Wang, Y., & Yang, H. (2019). [dl] a survey of FPGA-based neural network inference accelerators. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 12(1), 1\u201326.","journal-title":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)"},{"key":"1855_CR14","unstructured":"Xilinx Vitis AI development environment. https:\/\/www.xilinx.com\/products\/design-tools\/vitis\/vitis-ai.html"},{"key":"1855_CR15","unstructured":"Xilinx Deep Learning Processing Unit. https:\/\/www.xilinx.com\/products\/intellectual-property\/dpu.html"},{"key":"1855_CR16","doi-asserted-by":"crossref","unstructured":"Yu, X., Wang, Y., Miao, J., Wu, E., Zhang, H., Meng, Y., Zhang, B., Min, B., Chen, D., & Gao, J. (2019).\u00a0A data-center FPGA acceleration platform for convolutional neural networks. In\u00a02019 29th International Conference on Field Programmable Logic and Applications (FPL) (pp. 151\u2013158). IEEE.","DOI":"10.1109\/FPL.2019.00032"},{"key":"1855_CR17","doi-asserted-by":"publisher","unstructured":"Zhang, C., Fang, Z., Zhou, P., Pan, P., & Cong, J. (2016).\u00a0Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks. In\u00a02016 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) (pp. 1\u20138).\u00a0https:\/\/doi.org\/10.1145\/2966986.2967011","DOI":"10.1145\/2966986.2967011"},{"key":"1855_CR18","doi-asserted-by":"publisher","unstructured":"Ma, Y., Cao, Y., Vrudhula, S., & S.\u00a0Seo, J. (2017).\u00a0An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. In\u00a02017 27th International Conference on Field Programmable Logic and Applications (FPL) (pp 1\u20138).\u00a0https:\/\/doi.org\/10.23919\/FPL.2017.8056824","DOI":"10.23919\/FPL.2017.8056824"},{"key":"1855_CR19","doi-asserted-by":"publisher","unstructured":"Venieris, S. I., & Bouganis, C. S. (2017).\u00a0Latency-driven design for FPGA-based convolutional neural networks. In\u00a02017 27th International Conference on Field Programmable Logic and Applications (FPL) (pp. 1\u20138).\u00a0https:\/\/doi.org\/10.23919\/FPL.2017.8056828","DOI":"10.23919\/FPL.2017.8056828"},{"key":"1855_CR20","doi-asserted-by":"publisher","unstructured":"Gokhale, V., Zaidy, A., Chang, A. X. M., Culurciello, E. (2017).\u00a0Snowflake: An efficient hardware accelerator for convolutional neural networks. In\u00a02017 IEEE International Symposium on Circuits and Systems (ISCAS)\u00a0(pp. 1\u20134).\u00a0https:\/\/doi.org\/10.1109\/ISCAS.2017.8050809","DOI":"10.1109\/ISCAS.2017.8050809"},{"key":"1855_CR21","doi-asserted-by":"crossref","unstructured":"Qiu, J., Wang, J., Yao, S., Guo, K., Li, B., Zhou, E., Yu, J., Tang, T., Xu, N., Song, S., Wang, Y., & Yang, H. (2016).\u00a0Going deeper with embedded FPGA platform for convolutional neural network. In Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA \u201916 (pp. 26\u201335). ACM, New York, NY, USA.\u00a0https:\/\/doi.org\/10.1145\/2847263.2847265. http:\/\/doi.acm.org\/10.1145\/2847263.2847265","DOI":"10.1145\/2847263.2847265"},{"key":"1855_CR22","doi-asserted-by":"publisher","unstructured":"Meloni, P., Capotondi, A., Deriu, G., Brian, M., Conti, F., Rossi, D., Raffo, L., & Benini, L. (2018).\u00a0Neuraghe: Exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on ZYNQ SOCS.\u00a0ACM Transactions on Reconfigurable Technology and Systems,\u00a011(3).\u00a0https:\/\/doi.org\/10.1145\/3284357","DOI":"10.1145\/3284357"},{"issue":"3","key":"1855_CR23","doi-asserted-by":"publisher","first-page":"348","DOI":"10.1109\/JETCAS.2020.3014503","volume":"10","author":"M Carreras","year":"2020","unstructured":"Carreras, M., Deriu, G., Raffo, L., Benini, L., & Meloni, P. (2020). Optimizing temporal convolutional network inference on FPGA-based accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 10(3), 348\u2013361. https:\/\/doi.org\/10.1109\/JETCAS.2020.3014503","journal-title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems"},{"key":"1855_CR24","doi-asserted-by":"publisher","unstructured":"Prost-Boucle, A., Bourge, A., Petrot, F., Alemdar, H., Caldwell, N., & Leroy, V. (2017).\u00a0Scalable high-performance architecture for convolutional ternary neural networks on FPGA. In\u00a02017 27th International Conference on Field Programmable Logic and Applications (FPL) (pp. 1\u20137).\u00a0https:\/\/doi.org\/10.23919\/FPL.2017.8056850","DOI":"10.23919\/FPL.2017.8056850"},{"key":"1855_CR25","doi-asserted-by":"publisher","unstructured":"Umuroglu, Y., Fraser, N., Gambardella, G., Blott, M., Leong, P., Jahre, M., & Vissers, K. (2017).\u00a0Finn: A framework for fast, scalable binarized neural network inference. In Proceedings of the 2017 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA \u201917 (pp. 65\u201374). ACM, New York, NY, USA.\u00a0https:\/\/doi.org\/10.1145\/3020078.3021744. http:\/\/doi.acm.org\/10.1145\/3020078.3021744","DOI":"10.1145\/3020078.3021744"},{"key":"1855_CR26","doi-asserted-by":"crossref","unstructured":"Rasoulinezhad, S., Zhou, H., Wang, L., & Leong, P. H. W. (2019).\u00a0PIR-DSP: An FPGA DSP block architecture for multi-precision deep neural networks. In\u00a02019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (pp. 35\u201344).","DOI":"10.1109\/FCCM.2019.00015"},{"key":"1855_CR27","doi-asserted-by":"crossref","unstructured":"Wang, E., Davis, J. J., Cheung, P. Y., & Constantinides, G. (2020).\u00a0Lutnet: Learning FPGA configurations for highly efficient neural network inference. IEEE Transactions on Computers.","DOI":"10.1109\/TC.2020.2978817"},{"key":"1855_CR28","doi-asserted-by":"crossref","unstructured":"Meloni, P., Loi, D., Deriu, G., Pimentel, A. D., Sapra, D., Moser, B., Shepeleva, N., Conti, F., Benini, L., Ripolles, O., Solans, D., Pintor, M., Biggio, B., Stefanov, T. P., Minakova, S., Fragoulis, N., Theodorakopoulos, I., Masin, M., & Palumbo, F. (2018).\u00a0ALOHA: an architectural-aware framework for deep learning at the edge. In M.\u00a0Martina, & W.\u00a0Fornaciari (Eds.),\u00a0Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, INTESA@ESWEEK 2018, Turin, Italy, October 04-04, 2018\u00a0(pp. 19\u201326). ACM.","DOI":"10.1145\/3285017.3285019"},{"key":"1855_CR29","doi-asserted-by":"publisher","unstructured":"Meloni, P., Loi, D., Deriu, G., Carreras, M., Conti, F., Capotondi, A., & Rossi, D. (2019).\u00a0Exploring Neuraghe: A customizable template for APSOC-based CNN inference at the edge. IEEE Embedded Systems Letters, PP, 1\u20131.\u00a0https:\/\/doi.org\/10.1109\/LES.2019.2947312","DOI":"10.1109\/LES.2019.2947312"},{"issue":"10","key":"1855_CR30","doi-asserted-by":"publisher","first-page":"1591","DOI":"10.1109\/TCAD.2015.2513673","volume":"35","author":"R Nane","year":"2016","unstructured":"Nane, R., Sima, V., Pilato, C., Choi, J., Fort, B., Canis, A., Chen, Y. T., Hsiao, H., Brown, S., Ferrandi, F., Anderson, J., & Bertels, K. (2016). A survey and evaluation of FPGA high-level synthesis tools. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(10), 1591\u20131604. https:\/\/doi.org\/10.1109\/TCAD.2015.2513673","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"1855_CR31","doi-asserted-by":"crossref","unstructured":"Pursley, D., & Yeh, T. (2017).\u00a0High-level low-power system design optimization. In\u00a0Symposium on\u00a0VLSI Design, Automation and Test (pp. 1\u20134).","DOI":"10.1109\/VLSI-DAT.2017.7939656"},{"key":"1855_CR32","unstructured":"Xilinx: Vivado Design Suite User Guide - High-Level Synthesis, UG902"},{"issue":"3","key":"1855_CR33","doi-asserted-by":"publisher","first-page":"69","DOI":"10.1109\/LES.2018.2882989","volume":"11","author":"C Rubattu","year":"2019","unstructured":"Rubattu, C., Palumbo, F., Sau, C., Salvador, R., S\u00e9rot, J., Desnos, K., Raffo, L., & Pelcat, M. (2019). Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators. IEEE Embedded Systems Letters, 11(3), 69\u201372. https:\/\/doi.org\/10.1109\/LES.2018.2882989","journal-title":"IEEE Embedded Systems Letters"},{"key":"1855_CR34","doi-asserted-by":"publisher","unstructured":"Compton, K., & Hauck, S. (2002). Reconfigurable computing: A survey of systems and software.\u00a034(2), 171\u2013210. https:\/\/doi.org\/10.1145\/508352.508353","DOI":"10.1145\/508352.508353"},{"key":"1855_CR35","doi-asserted-by":"publisher","unstructured":"Fanni, T., Sau, C., Raffo, L., & Palumbo, F. (2015). Automated power gating methodology for dataflow-based reconfigurable systems. https:\/\/doi.org\/10.1145\/2742854.2747285. Cited By 9","DOI":"10.1145\/2742854.2747285"},{"key":"1855_CR36","doi-asserted-by":"publisher","unstructured":"Li, L., Sau, C., Fanni, T., Li, J., Viitanen, T., Christophe, F., Palumbo, F., Raffo, L., Huttunen, H., Takala, J., Bhattacharyya, S. S. (2019).\u00a0An integrated hardware\/software design methodology for signal processing systems. Journal of Systems Architecture,\u00a093, 1\u201319. https:\/\/doi.org\/10.1016\/j.sysarc.2018.12.010,\u00a0https:\/\/www.sciencedirect.com\/science\/article\/pii\/S1383762118301735","DOI":"10.1016\/j.sysarc.2018.12.010"},{"key":"1855_CR37","doi-asserted-by":"publisher","unstructured":"Bezati, E., Casale-Brunet, S., Mosqueron, R., & Mattavelli, M. (2019).\u00a0An heterogeneous compiler of dataflow programs for ZYNQ platforms. In ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (pp. 1537\u20131541).\u00a0https:\/\/doi.org\/10.1109\/ICASSP.2019.8682525","DOI":"10.1109\/ICASSP.2019.8682525"},{"key":"1855_CR38","doi-asserted-by":"crossref","unstructured":"S\u00e9rot, J., & Berry, F. (2014).\u00a0High-level dataflow programming for reconfigurable computing. In\u00a0Symposium on Computer Architecture and High Performance Computing Work (pp. 72\u201377).","DOI":"10.1109\/SBAC-PADW.2014.18"},{"key":"1855_CR39","doi-asserted-by":"publisher","unstructured":"Sau, C., Fanni, T., Rubattu, C., Raffo, L., & Palumbo, F. (2021).\u00a0The multi-dataflow composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design. Microprocessors and Microsystems,\u00a080, 103326. https:\/\/doi.org\/10.1016\/j.micpro.2020.103326, https:\/\/www.sciencedirect.com\/science\/article\/pii\/S0141933120304853","DOI":"10.1016\/j.micpro.2020.103326"},{"key":"1855_CR40","doi-asserted-by":"crossref","unstructured":"Szegedy, C., Vanhoucke, V., Ioffe, S., Shlens, J., & Wojna, Z. (2015).\u00a0Rethinking the inception architecture for computer vision. CoRR abs\/1512.00567.","DOI":"10.1109\/CVPR.2016.308"},{"key":"1855_CR41","doi-asserted-by":"crossref","unstructured":"Sau, C., Rinaldi, C., Pomante, L., Palumbo, F., Valente, G., Fanni, T., Martinez, M., van\u00a0der Linden, F., Basten, T., Geilen, M., Peeren, G., Kadlec, J., J\u00e4\u00e4skel\u00e4inen, P., Bulej, L., Barranco, F., Saarinen, J., S\u00e4ntti, T., Zedda, M.K., Sanchez, V., Nikkhah, S.T., Goswami, D., Amat, G., Mar\u0161\u00edk, L., van Helvoort, M., Medina, L., Al-Ars, Z., & de\u00a0Beer, A. (2021).\u00a0Design and management of image processing pipelines within CPS: Acquired experience towards the end of the Fitoptivis Ecsel project. Microprocessors and Microsystems,\u00a087.","DOI":"10.1016\/j.micpro.2021.104350"},{"key":"1855_CR42","unstructured":"Agarap, A. F. (2018).\u00a0Deep learning using rectified linear units (RELU). CoRR abs\/1803.08375. http:\/\/arxiv.org\/abs\/1803.08375"},{"key":"1855_CR43","unstructured":"PyTorch: Batchnorm2d (2019).\u00a0https:\/\/pytorch.org\/docs\/stable\/generated\/torch.nn.BatchNorm2d.html"},{"key":"1855_CR44","doi-asserted-by":"crossref","unstructured":"Ding, B., Qian, H., & Zhou, J. (2018).\u00a0Activation functions and their characteristics in deep neural networks.","DOI":"10.1109\/CCDC.2018.8407425"},{"key":"1855_CR45","doi-asserted-by":"crossref","unstructured":"Zhang Zhifei, S. Y., & Qi, H. (2017).\u00a0Age progression\/regression by conditional adversarial autoencoder. In IEEE Conference on Computer Vision and Pattern Recognition (CVPR). IEEE.","DOI":"10.1109\/CVPR.2017.463"},{"key":"1855_CR46","unstructured":"Corrado, A. (2019).\u00a0Animal-10 dataset. https:\/\/www.kaggle.com\/alessiocorrado99\/animals10"},{"key":"1855_CR47","unstructured":"Bai, J., Lu, F., Zhang, K., et\u00a0al. (2019).\u00a0Onnx: Open neural network exchange.\u00a0Retrieved April 2023, from https:\/\/docs.xilinx.com\/v\/u\/en-US\/ug902-vivado-high-level-synthesis,\u00a0https:\/\/github.com\/onnx\/onnx"},{"key":"1855_CR48","unstructured":"TensorFlow: Tensorflow core v2.4.1 (2020).\u00a0https:\/\/www.tensorflow.org\/api_docs\/python\/tf\/nn\/conv2d"},{"key":"1855_CR49","unstructured":"Keras ONNX: Keras to ONNX converter (2021). https:\/\/github.com\/onnx\/keras-onnx"},{"key":"1855_CR50","unstructured":"ONNxmltools: ONNxmltools library (2021). https:\/\/github.com\/onnx\/onnxmltools"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-023-01855-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11265-023-01855-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-023-01855-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,9]],"date-time":"2023-10-09T08:17:46Z","timestamp":1696839466000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11265-023-01855-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4,26]]},"references-count":50,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2023,9]]}},"alternative-id":["1855"],"URL":"https:\/\/doi.org\/10.1007\/s11265-023-01855-x","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,4,26]]},"assertion":[{"value":"3 April 2021","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 February 2023","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 February 2023","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"26 April 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}