{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,25]],"date-time":"2026-01-25T03:35:53Z","timestamp":1769312153659,"version":"3.49.0"},"reference-count":18,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2023,4,27]],"date-time":"2023-04-27T00:00:00Z","timestamp":1682553600000},"content-version":"vor","delay-in-days":26,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"funder":[{"DOI":"10.13039\/501100004837","name":"Ministerio de Ciencia e Innovaci\u00f3n","doi-asserted-by":"publisher","award":["RYC2018-025384-I"],"award-info":[{"award-number":["RYC2018-025384-I"]}],"id":[{"id":"10.13039\/501100004837","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100012818","name":"Comunidad de Madrid","doi-asserted-by":"publisher","award":["APOYO-JOVENES-21-TL23SB-116-I4FOMC"],"award-info":[{"award-number":["APOYO-JOVENES-21-TL23SB-116-I4FOMC"]}],"id":[{"id":"10.13039\/100012818","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003759","name":"Universidad Polit\u00e9cnica de Madrid","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003759","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2023,4]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>In this paper, we propose two efficient implementations of complex multipliers on field-programmable gate arrays (FPGAs) using DSP slices. The first implementation aims for high throughput and the second one for low area. By mapping these circuits to the DSP slices in the FPGA, the proposed implementations have the advantage that they only require three DSP slices. Experimental results show that the proposed high-throughput implementation saves hardware resources with respect to previous approaches, while reaching the highest achievable clock frequency. Alternatively, the proposed low-area implementation reduces the amount of hardware resources even further at the cost of reducing the clock frequency.<\/jats:p>","DOI":"10.1007\/s11265-023-01867-7","type":"journal-article","created":{"date-parts":[[2023,4,27]],"date-time":"2023-04-27T08:02:16Z","timestamp":1682582536000},"page":"543-550","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":20,"title":["Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices"],"prefix":"10.1007","volume":"95","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9461-8906","authenticated-orcid":false,"given":"Pedro","family":"Paz","sequence":"first","affiliation":[]},{"given":"Mario","family":"Garrido","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,4,27]]},"reference":[{"key":"1867_CR1","doi-asserted-by":"crossref","unstructured":"Garrido, M., Qureshi, F., Takala, J., & Gustafsson, O. (2019). Hardware architectures for the fast Fourier transform. In: S. S. Bhattacharyya, E. F. Deprettere, & R.\u00a0Leupers, J.\u00a0Takala (Eds.) Handbook of Signal Processing Systems (3rd ed.). Springer.","DOI":"10.1007\/978-3-319-91734-4_17"},{"key":"1867_CR2","doi-asserted-by":"crossref","unstructured":"Qureshi, F., Takala, J., & Bhattacharyya, S. (2020). Rotators in fast Fourier transforms. In: S. S. Bhattacharyya, M.\u00a0Potkonjak, S.\u00a0 & Velipasalar (Eds.), Embedded, Cyber-Physical, and IoT Systems: Essays Dedicated to Marilyn Wolf on the Occasion of Her 60th Birthday. Springer International Publishing.","DOI":"10.1007\/978-3-030-16949-7"},{"issue":"9","key":"1867_CR3","doi-asserted-by":"publisher","first-page":"2486","DOI":"10.1109\/TVLSI.2017.2710479","volume":"25","author":"C Ingemarsson","year":"2017","unstructured":"Ingemarsson, C., K\u00e4llstr\u00f6m, P., Qureshi, F., & Gustafsson, O. (2017). Efficient FPGA mapping of pipeline SDF FFT cores. IEEE Transactions on VLSI Systems, 25(9), 2486\u20132497.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"1867_CR4","doi-asserted-by":"crossref","unstructured":"Rao, K. D., Gangadhar, C., & Korrai, P. K. (2016). FPGA implementation of complex multiplier using minimum delay Vedic real multiplier architecture. In Proceedings on IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (pp. 580\u2013584).","DOI":"10.1109\/UPCON.2016.7894719"},{"key":"1867_CR5","doi-asserted-by":"crossref","unstructured":"\u017d\u00e1dn\u00edk, J., & Takala, J. (2019). Low-power programmable processor for fast Fourier transform based on transport triggered architecture. In Proceedings on International Conference on Acoustics, Speech, and Signal Processing (pp. 1423\u20131427).","DOI":"10.1109\/ICASSP.2019.8682289"},{"key":"1867_CR6","unstructured":"Xilinx - Complex multiplier v6.0 (2021). Retrieved November 16, 2021, from https:\/\/docs.xilinx.com\/v\/u\/en-US\/pg104-cmpy"},{"key":"1867_CR7","doi-asserted-by":"crossref","unstructured":"Du, J., Chen, K., Yin, P., Yan, C., & Liu, W. (2021). Design of an approximate FFT processor based on approximate complex multipliers. In IEEE Computer Society Annual Symposium on VLSI (pp. 308\u2013313).","DOI":"10.1109\/ISVLSI51109.2021.00063"},{"key":"1867_CR8","doi-asserted-by":"crossref","unstructured":"Fonseca, M. B., Martins, J. B. S., & da\u00a0Costa, E. A. C. (2011). Design of pipelined butterflies from radix-2 FFT with decimation in time algorithm using efficient adder compressors. In Proceedings on IEEE Latin American Symposium on Circuits and Systems (pp. 1\u20134).","DOI":"10.1109\/LASCAS.2011.5750281"},{"issue":"17","key":"1867_CR9","doi-asserted-by":"publisher","first-page":"2903","DOI":"10.1155\/ASP.2005.2903","volume":"2005","author":"MD Macleod","year":"2005","unstructured":"Macleod, M. D. (2005). Multiplierless implementation of rotators and FFTs. EURASIP Journal on Advances in Signal Processing, 2005(17), 2903\u20132910.","journal-title":"EURASIP Journal on Advances in Signal Processing"},{"issue":"2","key":"1867_CR10","doi-asserted-by":"publisher","first-page":"113","DOI":"10.1007\/s11265-006-7265-3","volume":"43","author":"J Takala","year":"2006","unstructured":"Takala, J., & Punkka, K. (2006). Scalable FFT processors and pipelined butterfly units. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 43(2), 113\u2013123.","journal-title":"Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology"},{"key":"1867_CR11","doi-asserted-by":"crossref","unstructured":"Wenzler, A., & Luder, E. (1995). New structures for complex multipliers and their noise analysis. In Proceedings on IEEE International Symposium on Circuits and Systems (Vol.\u00a02, pp. 1432\u20131435).","DOI":"10.1109\/ISCAS.1995.521402"},{"key":"1867_CR12","unstructured":"Xilinx - 7 Series DSP48E1 Slice. (2018). Retrieved November 16, 2021, from https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug479_7Series_DSP48E1.pdf"},{"key":"1867_CR13","unstructured":"Xilinx Ultrascale architecture DSP Slice. (2021). Retrieved November 16, 2021, from https:\/\/docs.xilinx.com\/v\/u\/en-US\/ug579-ultrascale-dsp"},{"key":"1867_CR14","unstructured":"Xilinx 7 series FPGAs data sheet (2020). Retrieved November 16, 2021, from https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds180_7Series_Overview.pdf"},{"key":"1867_CR15","unstructured":"Xilinx Ultrascale architecture and product data sheet: Overview. (2022). Retrieved November 16, 2021, from https:\/\/docs.xilinx.com\/v\/u\/en-US\/ds890-ultrascale-overview"},{"issue":"3","key":"1867_CR16","doi-asserted-by":"publisher","first-page":"757","DOI":"10.1109\/JSSC.2011.2176163","volume":"47","author":"CH Yang","year":"2012","unstructured":"Yang, C. H., Yu, T. H., & Markovic, D. (2012). Power and area minimization of reconfigurable FFT processors: A 3GPP-LTE example. IEEE Journal Solid-State Circuits, 47(3), 757\u2013768.","journal-title":"IEEE Journal Solid-State Circuits"},{"key":"1867_CR17","unstructured":"Xilinx 7 series FPGAs configurable logic block user guide. (2016). Retrieved November 16, 2021, from https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug474_7Series_CLB.pdf"},{"issue":"1","key":"1867_CR18","doi-asserted-by":"publisher","first-page":"322","DOI":"10.1109\/TCSI.2020.3031688","volume":"68","author":"M Garrido","year":"2021","unstructured":"Garrido, M., & Malag\u00f3n, P. (2021). The constant multiplier FFT. IEEE Transactions on Circuits and Systems I, 68(1), 322\u2013335.","journal-title":"IEEE Transactions on Circuits and Systems I"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-023-01867-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11265-023-01867-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-023-01867-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,17]],"date-time":"2023-05-17T14:41:43Z","timestamp":1684334503000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11265-023-01867-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4]]},"references-count":18,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2023,4]]}},"alternative-id":["1867"],"URL":"https:\/\/doi.org\/10.1007\/s11265-023-01867-7","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,4]]},"assertion":[{"value":"7 July 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"17 March 2023","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"1 April 2023","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 April 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}