{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,17]],"date-time":"2025-11-17T02:15:20Z","timestamp":1763345720390,"version":"3.45.0"},"reference-count":114,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2025,11,17]],"date-time":"2025-11-17T00:00:00Z","timestamp":1763337600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,11,17]],"date-time":"2025-11-17T00:00:00Z","timestamp":1763337600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/501100015494","name":"Instituto de Telecomunica\u00e7\u00f5es","doi-asserted-by":"crossref","award":["2022.06780.PTDC","LA\/P\/0109\/2020"],"award-info":[{"award-number":["2022.06780.PTDC","LA\/P\/0109\/2020"]}],"id":[{"id":"10.13039\/501100015494","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Funca\u00e7\u00f5o para a Ci\u00eancia e Tecnologia","award":["2020.07124.BD"],"award-info":[{"award-number":["2020.07124.BD"]}]},{"name":"Digital European Programme","award":["Grant Agreement 101083770"],"award-info":[{"award-number":["Grant Agreement 101083770"]}]},{"name":"EU Recovery and Resilience Plan","award":["774"],"award-info":[{"award-number":["774"]}]},{"DOI":"10.13039\/501100015494","name":"Instituto de Telecomunica\u00e7\u00f5es","doi-asserted-by":"crossref","award":["UID\/50008\/2023 IT"],"award-info":[{"award-number":["UID\/50008\/2023 IT"]}],"id":[{"id":"10.13039\/501100015494","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2026,6]]},"DOI":"10.1007\/s11265-025-01974-7","type":"journal-article","created":{"date-parts":[[2025,11,17]],"date-time":"2025-11-17T02:11:31Z","timestamp":1763345491000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["An Experimental Exploration of In-Memory Computing for Multi-Layer Perceptrons"],"prefix":"10.1007","volume":"98","author":[{"given":"Pedro","family":"Carrinho","sequence":"first","affiliation":[]},{"given":"Hamid","family":"Moghadaspour","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5266-9740","authenticated-orcid":false,"given":"Oscar","family":"Ferraz","sequence":"additional","affiliation":[]},{"given":"Jo\u00e3o","family":"Dinis Ferreira","sequence":"additional","affiliation":[]},{"given":"Yann","family":"Falevoz","sequence":"additional","affiliation":[]},{"given":"Vitor","family":"Silva","sequence":"additional","affiliation":[]},{"given":"Gabriel","family":"Falcao","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,11,17]]},"reference":[{"key":"1974_CR1","unstructured":"Taylor. P. Volume of Data\/information Created, Captured, Copied, and Consumed Worldwide from 2010 to 2025. Accessed: 2023-01-30. https:\/\/www.statista.com\/statistics\/871513\/worldwide-data-created"},{"issue":"6","key":"1974_CR2","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1147\/JRD.2019.2934048","volume":"63","author":"S Ghose","year":"2019","unstructured":"Ghose, S., Boroumand, A., Kim, J. S., G\u00f3mez-Luna, J., & Mutlu, O. (2019). Processing-in-memory: A workload-driven perspective. IBM Journal of Research and Development, 63(6), 3\u20131.","journal-title":"IBM Journal of Research and Development"},{"key":"1974_CR3","doi-asserted-by":"publisher","first-page":"28","DOI":"10.1016\/j.micpro.2019.01.009","volume":"67","author":"O Mutlu","year":"2019","unstructured":"Mutlu, O., Ghose, S., G\u00f3mez-Luna, J., & Ausavarungnirun, R. (2019). Processing data where it makes sense: Enabling in-memory computation. Microprocessors and Microsystems, 67, 28\u201341.","journal-title":"Microprocessors and Microsystems"},{"key":"1974_CR4","doi-asserted-by":"crossref","unstructured":"Mutlu, O., Ghose, S., G\u00f3mez-Luna, J., Ausavarungnirun, R. (2022). A modern primer on processing in memory. In Emerging computing: from devices to systems: looking beyond moore and von neumann (pp. 171\u2013243). Springer","DOI":"10.1007\/978-981-16-7487-7_7"},{"key":"1974_CR5","doi-asserted-by":"crossref","unstructured":"Falevoz, Y., & Legriel, J. (2023). Energy efficiency impact of processing in memory: A comprehensive review of workloads on the upmem architecture. In European conference on parallel processing (pp. 155\u2013166). Springer","DOI":"10.1007\/978-3-031-48803-0_13"},{"key":"1974_CR6","doi-asserted-by":"crossref","unstructured":"Boroumand, A., Ghose, S., Kim, Y., Ausavarungnirun, R., Shiu, E., Thakur, R., ... & Mutlu, O. (2018). Google workloads for consumer devices: Mitigating data movement bottlenecks. In Proceedings of the twenty-third international conference on architectural support for programming languages and operating systems (pp. 316\u2013331)","DOI":"10.1145\/3173162.3173177"},{"key":"1974_CR7","unstructured":"Upmem: UPMEM Website. Accessed: 2023-01-30. https:\/\/www.upmem.com"},{"key":"1974_CR8","doi-asserted-by":"crossref","unstructured":"Carrinho, P., Ferraz, O., Ferreira, J. D., Falevoz, Y., Silva, V., & Falcao, G. (2024). Processing multi-layer perceptrons in-memory. In 2024 IEEE Workshop on signal processing systems (SiPS) (pp. 7\u201312). IEEE","DOI":"10.1109\/SiPS62058.2024.00010"},{"key":"1974_CR9","doi-asserted-by":"publisher","first-page":"71","DOI":"10.1016\/j.iotcps.2023.02.004","volume":"3","author":"R Singh","year":"2023","unstructured":"Singh, R., & Gill, S. S. (2023). Edge ai: a survey. Internet of Things and Cyber-Physical Systems, 3, 71\u201392.","journal-title":"Internet of Things and Cyber-Physical Systems"},{"key":"1974_CR10","volume":"38","author":"R Desislavov","year":"2023","unstructured":"Desislavov, R., Mart\u00ednez-Plumed, F., & Hern\u00e1ndez-Orallo, J. (2023). Trends in ai inference energy consumption: Beyond the performance-vs-parameter laws of deep learning. Sustainable Computing: Informatics and Systems, 38, Article 100857.","journal-title":"Sustainable Computing: Informatics and Systems"},{"key":"1974_CR11","doi-asserted-by":"crossref","unstructured":"G\u00f3mez-Luna, J., El\u00a0Hajj, I., Fernandez, I., Giannoula, C., Oliveira, G.F., & Mutlu, O. (2021). Benchmarking memory-centric computing systems: Analysis of real processing-in-memory hardware. In 2021 12th International green and sustainable computing conference (IGSC) (pp. 1\u20137). IEEE","DOI":"10.1109\/IGSC54211.2021.9651614"},{"issue":"11","key":"1974_CR12","doi-asserted-by":"publisher","first-page":"00938","DOI":"10.1016\/j.heliyon.2018.e00938","volume":"4","author":"OI Abiodun","year":"2018","unstructured":"Abiodun, O. I., Jantan, A., Omolara, A. E., Dada, K. V., Mohamed, N. A., & Arshad, H. (2018). State-of-the-art in artificial neural network applications: A survey. Heliyon, 4(11), 00938.","journal-title":"Heliyon"},{"issue":"5","key":"1974_CR13","doi-asserted-by":"publisher","first-page":"146","DOI":"10.3390\/fi14050146","volume":"14","author":"A Asad","year":"2022","unstructured":"Asad, A., Kaur, R., & Mohammadi, F. (2022). A survey on memory subsystems for deep neural network accelerators. Future Internet, 14(5), 146.","journal-title":"Future Internet"},{"key":"1974_CR14","doi-asserted-by":"crossref","unstructured":"Oliveira, G. F., G\u00f3mez-Luna, J., Orosa, L., Ghose, S., Vijaykumar, N., Fernandez, I., & Mutlu, O. (2021). Damov: A new methodology and benchmark suite for evaluating data movement bottlenecks. IEEE Access, 9, 134457\u2013134502.","DOI":"10.1109\/ACCESS.2021.3110993"},{"key":"1974_CR15","doi-asserted-by":"publisher","first-page":"746","DOI":"10.1007\/s11704-016-6159-1","volume":"11","author":"Z Li","year":"2017","unstructured":"Li, Z., Wang, Y., Zhi, T., & Chen, T. (2017). A survey of neural network accelerators. Frontiers of Computer Science, 11, 746\u2013761.","journal-title":"Frontiers of Computer Science"},{"key":"1974_CR16","doi-asserted-by":"crossref","unstructured":"Seshadri, V., Lee, D., Mullins, T., Hassan, H., Boroumand, A., Kim, J., ... & Mowry, T. C. (2017). Ambit: In-memory accelerator for bulk bitwise operations using commodity dram technology. In Proceedings of the 50th Annual IEEE\/ACM International Symposium on Microarchitecture (pp. 273\u2013287)","DOI":"10.1145\/3123939.3124544"},{"key":"1974_CR17","doi-asserted-by":"crossref","unstructured":"Yang, T.-J., Chen, Y.-H., Emer, J., Sze, V. (2017). A method to estimate the energy consumption of deep neural networks. In 2017 51st Asilomar Conference on Signals, Systems, and Computers (pp. 1916\u20131920). IEEE","DOI":"10.1109\/ACSSC.2017.8335698"},{"key":"1974_CR18","doi-asserted-by":"crossref","unstructured":"Szegedy, C., Liu, W., Jia, Y., Sermanet, P., Reed, S., Anguelov, D., ... & Rabinovich, A. (2015). Going deeper with convolutions. In Proceedings of the IEEE conference on computer vision and pattern recognition (CVPR)","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"1974_CR19","doi-asserted-by":"crossref","unstructured":"Angizi, S., He, Z., Rakin, A. S., & Fan, D. (2018). Cmp-pim: an energy-efficient comparator-based processing-in-memory neural network accelerator. In Proceedings of the 55th annual design automation conference (pp. 1\u20136)","DOI":"10.1145\/3195970.3196009"},{"key":"1974_CR20","doi-asserted-by":"crossref","unstructured":"Imani, M., Gupta, S., Kim, Y., Rosing, T. (2019). Floatpim: In-memory acceleration of deep neural network training with high precision. In Proceedings of the 46th international symposium on computer architecture (pp. 802\u2013815)","DOI":"10.1145\/3307650.3322237"},{"key":"1974_CR21","doi-asserted-by":"crossref","unstructured":"Shafiee, A., Nag, A., Muralimanohar, N., Balasubramonian, R., Strachan, J. P., Hu, M., & Srikumar, V. (2016). Isaac: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars. ACM SIGARCH Computer Architecture News, 44(3), 14\u201326.","DOI":"10.1145\/3007787.3001139"},{"key":"1974_CR22","doi-asserted-by":"crossref","unstructured":"Chi, P., Li, S., Xu, C., Zhang, T., Zhao, J., Liu, Y., & Xie, Y. (2016). Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory. ACM SIGARCH Computer Architecture News, 44(3), 27\u201339.","DOI":"10.1145\/3007787.3001140"},{"key":"1974_CR23","doi-asserted-by":"crossref","unstructured":"Liu, J., Zhao, H., Ogleari, M. A., Li, D., & Zhao, J. (2018). Processing-in-memory for energy-efficient neural network training: A heterogeneous approach. In 2018 51st Annual IEEE\/ACM international symposium on microarchitecture (MICRO) (pp. 655\u2013668). IEEE","DOI":"10.1109\/MICRO.2018.00059"},{"issue":"4","key":"1974_CR24","doi-asserted-by":"publisher","first-page":"1093","DOI":"10.1109\/JSSC.2020.3039206","volume":"56","author":"J-H Kim","year":"2021","unstructured":"Kim, J.-H., Lee, J., Lee, J., Heo, J., & Kim, J.-Y. (2021). Z-pim: A sparsity-aware processing-in-memory architecture with fully variable weight bit-precision for energy-efficient deep neural networks. IEEE Journal of Solid-State Circuits, 56(4), 1093\u20131104.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"1974_CR25","volume-title":"Enna: An efficient neural network accelerator design based on adc-free compute-in-memory subarrays","author":"H Jiang","year":"2022","unstructured":"Jiang, H., Huang, S., Li, W., & Yu, S. (2022). Enna: An efficient neural network accelerator design based on adc-free compute-in-memory subarrays. IEEE Transactions on Circuits and Systems I: Regular Papers."},{"key":"1974_CR26","doi-asserted-by":"crossref","unstructured":"Ankit, A., Hajj, I. E., Chalamalasetti, S. R., Ndu, G., Foltin, M., Williams, R. S., ... & Milojicic, D. S. (2019) Puma: A programmable ultra-efficient memristor-based accelerator for machine learning inference. In Proceedings of the twenty-fourth international conference on architectural support for programming languages and operating systems (pp. 715\u2013731)","DOI":"10.1145\/3297858.3304049"},{"key":"1974_CR27","doi-asserted-by":"crossref","unstructured":"Angizi, S., He, Z., & Fan, D. (2019). Parapim: a parallel processing-in-memory accelerator for binary-weight deep neural networks. In Proceedings of the 24th Asia and South Pacific design automation conference (pp. 127\u2013132)","DOI":"10.1145\/3287624.3287644"},{"key":"1974_CR28","doi-asserted-by":"crossref","unstructured":"Kim, H., Chen, Q., Yoo, T., Kim, T. T.-H., & Kim, B. (2019). A bit-precision reconfigurable digital in-memory computing macro for energy-efficient processing of artificial neural networks. In 2019 International SoC design conference (ISOCC) (pp. 166\u2013167). IEEE","DOI":"10.1109\/ISOCC47750.2019.9027679"},{"key":"1974_CR29","doi-asserted-by":"crossref","unstructured":"Ham, H., Cho, H., Kim, M., Park, J., Hong, J., Sung, H., & Kim, G. (2021). Near-data processing in memory expander for dnn acceleration on gpus. IEEE Computer Architecture Letters, 20(2), 171\u2013174.","DOI":"10.1109\/LCA.2021.3126450"},{"key":"1974_CR30","doi-asserted-by":"crossref","unstructured":"Ke, L., Zhang, X., So, J., Lee, J. G., Kang, S. H., Lee, S., ... & Lee, H. H. S. (2021). Near-memory processing in action: Accelerating personalized recommendation with axdimm. IEEE Micro,42(1), 116\u2013127 (2021)","DOI":"10.1109\/MM.2021.3097700"},{"key":"1974_CR31","doi-asserted-by":"crossref","unstructured":"Lee, S., Kang, S. H., Lee, J., Kim, H., Lee, E., Seo, S., ... & Kim, N. S. (2021). Hardware architecture and software stack for pim based on commercial dram technology: Industrial product. In 2021 ACM\/IEEE 48th annual international symposium on computer architecture (ISCA) (pp. 43\u201356). IEEE","DOI":"10.1109\/ISCA52012.2021.00013"},{"key":"1974_CR32","doi-asserted-by":"crossref","unstructured":"Devaux, F. (2019). The true processing in memory accelerator. In 2019 IEEE Hot Chips 31 Symposium (HCS) (pp. 1\u201324). IEEE Computer Society","DOI":"10.1109\/HOTCHIPS.2019.8875680"},{"key":"1974_CR33","doi-asserted-by":"crossref","unstructured":"G\u00f3mez-Luna, J., Hajj, I. E., Fernandez, I., Giannoula, C., Oliveira, G. F., & Mutlu, O. (2021). Benchmarking a new paradigm: An experimental analysis of a real processing-in-memory architecture. arXiv:2105.03814","DOI":"10.1109\/ACCESS.2022.3174101"},{"key":"1974_CR34","unstructured":"Upmem: Upmem User Manual. https:\/\/sdk.upmem.com\/2023.1.0\/ Accessed 2023-02-27"},{"key":"1974_CR35","unstructured":"Upmem. (2022). UPMEM Processing In-Memory (PIM) Ultra-efficient acceleration for data-intensive applications. Upmem: Technical report."},{"key":"1974_CR36","first-page":"12077","volume":"34","author":"E Xie","year":"2021","unstructured":"Xie, E., Wang, W., Yu, Z., Anandkumar, A., Alvarez, J. M., & Luo, P. (2021). SegFormer: Simple and efficient design for semantic segmentation with transformers. Advances in Neural Information Processing Systems, 34, 12077\u201312090.","journal-title":"Advances in Neural Information Processing Systems"},{"key":"1974_CR37","first-page":"18261","volume":"33","author":"Y Liu","year":"2020","unstructured":"Liu, Y., Gao, Y., & Yin, W. (2020). An improved analysis of stochastic gradient descent with momentum. Advances in Neural Information Processing Systems, 33, 18261\u201318271.","journal-title":"Advances in Neural Information Processing Systems"},{"issue":"2","key":"1974_CR38","doi-asserted-by":"publisher","first-page":"179","DOI":"10.1111\/j.1469-1809.1936.tb02137.x","volume":"7","author":"RA Fisher","year":"1936","unstructured":"Fisher, R. A. (1936). The use of multiple measurements in taxonomic problems. Annals of Eugenics, 7(2), 179\u2013188.","journal-title":"Annals of Eugenics"},{"issue":"4","key":"1974_CR39","doi-asserted-by":"publisher","first-page":"853","DOI":"10.1162\/089976699300016467","volume":"11","author":"NN Schraudolph","year":"1999","unstructured":"Schraudolph, N. N. (1999). A fast, compact approximation of the exponential function. Neural Computation, 11(4), 853\u2013862.","journal-title":"Neural Computation"},{"key":"1974_CR40","doi-asserted-by":"crossref","unstructured":"Carrinho, P., Ferraz, O., Ferreira, J.D., Falevoz, Y., Silva, V., & Falcao, G. (2024). Processing Multi-Layer Perceptrons In-Memory. In 2024 IEEE Workshop on Signal Processing Systems (SiPS) (pp. 7\u201312). IEEE","DOI":"10.1109\/SiPS62058.2024.00010"},{"key":"1974_CR41","unstructured":"Deploy ai-powered autonomous machines at scale. https:\/\/www.nvidia.com\/en-eu\/autonomous-machines\/embedded-systems\/jetson-agx-xavier\/. [Online; accessed 2025-03-19]"},{"issue":"11","key":"1974_CR42","doi-asserted-by":"publisher","first-page":"2278","DOI":"10.1109\/5.726791","volume":"86","author":"Y LeCun","year":"1998","unstructured":"LeCun, Y., Bottou, L., Bengio, Y., & Haffner, P. (1998). Gradient-based learning applied to document recognition. Proceedings of the IEEE, 86(11), 2278\u20132324.","journal-title":"Proceedings of the IEEE"},{"key":"1974_CR43","unstructured":"Simonyan, K., & Zisserman, A. (2014). Very deep convolutional networks for large-scale image recognition. arXiv:1409.1556"},{"key":"1974_CR44","doi-asserted-by":"crossref","unstructured":"Lee, D., Hyun, B., Kim, T., & Rhu, M. (2024). PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems. arXiv:2409.06204","DOI":"10.1109\/MICRO61859.2024.00053"},{"issue":"3","key":"1974_CR45","doi-asserted-by":"publisher","first-page":"2473","DOI":"10.1109\/TCC.2022.3207145","volume":"11","author":"KD Duy","year":"2023","unstructured":"Duy, K. D., & Lee, H. (2023). Se-pim: In-memory acceleration of data-intensive confidential computing. IEEE Transactions on Cloud Computing, 11(3), 2473\u20132490. https:\/\/doi.org\/10.1109\/TCC.2022.3207145","journal-title":"IEEE Transactions on Cloud Computing"},{"key":"1974_CR46","doi-asserted-by":"crossref","unstructured":"Jia, Z., Zhan, J., Wang, L., Luo, C., Gao, W., Jin, Y., & Zhang, L. (2016). Understanding big data analytics workloads on modern processors. IEEE Transactions on Parallel and Distributed Systems, 28(6), 1797\u20131810.","DOI":"10.1109\/TPDS.2016.2625244"},{"key":"1974_CR47","doi-asserted-by":"crossref","unstructured":"Kanev, S., Darago, J. P., Hazelwood, K., Ranganathan, P., Moseley, T., & Wei, G.-Y., Brooks, D. (2015). Profiling a warehouse-scale computer. In Proceedings of the 42nd annual international symposium on computer architecture (pp. 158\u2013169)","DOI":"10.1145\/2749469.2750392"},{"key":"1974_CR48","doi-asserted-by":"crossref","unstructured":"Lee, S., Kim, K., Oh, S., Park, J., Hong, G., Ka, D., ... & Cho, J. (2022). A 1ynm 1.25 v 8gb, 16gb\/s\/pin gddr6-based accelerator-in-memory supporting 1tflops mac operation and various activation functions for deep-learning applications. In 2022 IEEE International Solid-State Circuits Conference (ISSCC), vol. 65, (pp. 1\u20133). IEEE","DOI":"10.1109\/ISSCC42614.2022.9731711"},{"key":"1974_CR49","doi-asserted-by":"crossref","unstructured":"Niu, D., Li, S., Wang, Y., Han, W., Zhang, Z., Guan, Y., ... & Xie, Y. (2022). 184qps\/w 64mb\/mm 2 3d logic-to-dram hybrid bonding with process-near-memory engine for recommendation system. In: 2022 IEEE International Solid-State Circuits Conference (ISSCC), vol. 65, pp. 1\u20133. IEEE","DOI":"10.1109\/ISSCC42614.2022.9731694"},{"key":"1974_CR50","doi-asserted-by":"crossref","unstructured":"Giannoula, C., Vijaykumar, N., Papadopoulou, N., Karakostas, V., Fernandez, I., G\u00f3mez-Luna, J., ... & Mutlu, O. (2021). Syncron: Efficient synchronization support for near-data-processing architectures. In 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), (pp. 263\u2013276). IEEE","DOI":"10.1109\/HPCA51647.2021.00031"},{"key":"1974_CR51","doi-asserted-by":"crossref","unstructured":"Ahn, J., Hong, S., Yoo, S., Mutlu, O., & Choi, K. (2015). A scalable processing-in-memory accelerator for parallel graph processing. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, (pp. 105\u2013117)","DOI":"10.1145\/2749469.2750386"},{"key":"1974_CR52","doi-asserted-by":"crossref","unstructured":"Boroumand, A., Ghose, S., Patel, M., Hassan, H., Lucia, B., Ausavarungnirun, R., ... & Mutlu, O. (2019) Conda: Efficient cache coherence support for near-data accelerators. In Proceedings of the 46th International Symposium on Computer Architecture, (pp. 629\u2013642)","DOI":"10.1145\/3307650.3322266"},{"key":"1974_CR53","doi-asserted-by":"crossref","unstructured":"Singh, G., G\u00f3mez-Luna, J., Mariani, G., Oliveira, G. F., Corda, S., Stuijk, S., ... & Corporaal, H. (2019) Near-memory computing application performance prediction via ensemble learning. In Proceedings of the 56th annual design automation conference 2019, (pp. 1\u20136)","DOI":"10.1145\/3316781.3317867"},{"key":"1974_CR54","doi-asserted-by":"crossref","unstructured":"Fernandez, I., Quislant, R., Guti\u00e9rrez, E., Plata, O., Giannoula, C., Alser, M., ... & Mutlu, O. (2020). Natsa: a near-data processing accelerator for time series analysis. In 2020 IEEE 38th International conference on computer design (ICCD), (pp. 120\u2013129). IEEE","DOI":"10.1109\/ICCD50377.2020.00035"},{"key":"1974_CR55","doi-asserted-by":"crossref","unstructured":"Cali, D. S., Kalsi, G. S., Bing\u00f6l, Z., Firtina, C., Subramanian, L., Kim, J. S., ... & Mutlu, O. (2020). Genasm: A high-performance, low-power approximate string matching acceleration framework for genome sequence analysis. In 2020 53rd Annual IEEE\/ACM international symposium on microarchitecture (MICRO), (pp. 951\u2013966). IEEE","DOI":"10.1109\/MICRO50266.2020.00081"},{"key":"1974_CR56","doi-asserted-by":"crossref","unstructured":"Kim, J. S., Senol Cali, D., Xin, H., Lee, D., Ghose, S., Alser, M., & Mutlu, O. (2018). Grim-filter: Fast seed location filtering in dna read mapping using processing-in-memory technologies. BMC Genomics, 19(2), 23\u201340.","DOI":"10.1186\/s12864-018-4460-0"},{"key":"1974_CR57","doi-asserted-by":"crossref","unstructured":"Augusta, A., & Idreos, S. (2015). Jafar: Near-data processing for databases. In Proceedings of the 2015 ACM SIGMOD international conference on management of data, (pp. 2069\u20132070)","DOI":"10.1145\/2723372.2764942"},{"key":"1974_CR58","doi-asserted-by":"crossref","unstructured":"Zhu, Q., Graf, T., Sumbul, H. E., Pileggi, L., & Franchetti, F.: Accelerating sparse matrix-matrix multiplication with 3d-stacked logic-in-memory hardware. In 2013 IEEE High performance extreme computing conference (HPEC), (pp. 1\u20136). IEEE","DOI":"10.1109\/HPEC.2013.6670336"},{"issue":"3S","key":"1974_CR59","doi-asserted-by":"publisher","first-page":"131","DOI":"10.1145\/2872887.2750397","volume":"43","author":"B Akin","year":"2015","unstructured":"Akin, B., Franchetti, F., & Hoe, J. C. (2015). Data reorganization in memory using 3d-stacked dram. ACM SIGARCH Computer Architecture News, 43(3S), 131\u2013143.","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"1974_CR60","doi-asserted-by":"crossref","unstructured":"Hsieh, K., Khan, S., Vijaykumar, N., Chang, K. K., Boroumand, A., Ghose, S., & Mutlu, O. (2016). Accelerating pointer chasing in 3d-stacked memory: Challenges, mechanisms, evaluation. In 2016 IEEE 34th International Conference on Computer Design (ICCD), (pp. 25\u201332). IEEE","DOI":"10.1109\/ICCD.2016.7753257"},{"key":"1974_CR61","doi-asserted-by":"crossref","unstructured":"Singh, G., Diamantopoulos, D., Hagleitner, C., Gomez-Luna, J., Stuijk, S., Mutlu, O., & Corporaal, H. (2020). Nero: A near high-bandwidth memory stencil accelerator for weather prediction modeling. In 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), (pp. 9\u201317). IEEE","DOI":"10.1109\/FPL50879.2020.00014"},{"issue":"3S","key":"1974_CR62","doi-asserted-by":"publisher","first-page":"336","DOI":"10.1145\/2872887.2750385","volume":"43","author":"J Ahn","year":"2015","unstructured":"Ahn, J., Yoo, S., Mutlu, O., & Choi, K. (2015). Pim-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture. ACM SIGARCH Computer Architecture News, 43(3S), 336\u2013348.","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"1974_CR63","doi-asserted-by":"crossref","unstructured":"Nai, L., Hadidi, R., Sim, J., Kim, H., Kumar, P., & Kim, H. (2017). Graphpim: Enabling instruction-level pim offloading in graph computing frameworks. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), (pp. 457\u2013468). IEEE","DOI":"10.1109\/HPCA.2017.54"},{"key":"1974_CR64","doi-asserted-by":"crossref","unstructured":"Hadidi, R., Nai, L., Kim, H., & Kim, H.: Cairo: A compiler-assisted technique for enabling instruction-level offloading of processing-in-memory. ACM Transactions on Architecture and Code Optimization (TACO),14(4), 1\u201325","DOI":"10.1145\/3155287"},{"key":"1974_CR65","doi-asserted-by":"crossref","unstructured":"Hsieh, K., Ebrahimi, E., Kim, G., Chatterjee, N., O\u2019Connor, M., Vijaykumar, N., & Keckler, S. W. (2016). Transparent offloading and mapping (tom) enabling programmer-transparent near-data processing in gpu systems. ACM SIGARCH Computer Architecture News, 44(3), 204\u2013216.","DOI":"10.1145\/3007787.3001159"},{"key":"1974_CR66","doi-asserted-by":"crossref","unstructured":"Kim, G., Chatterjee, N., O\u2019Connor, M., & Hsieh, K. (2017). Toward standardized near-data processing with unrestricted data placement for gpus. In Proceedings of the international conference for high performance computing, networking, storage and analysis, (pp. 1\u201312)","DOI":"10.1145\/3126908.3126965"},{"key":"1974_CR67","doi-asserted-by":"crossref","unstructured":"Pattnaik, A., Tang, X., Jog, A., Kayiran, O., Mishra, A. K., Kandemir, M. T., ... & Das, C. R. (2016). Scheduling techniques for gpu architectures with processing-in-memory capabilities. In Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, (pp. 31\u201344)","DOI":"10.1145\/2967938.2967940"},{"key":"1974_CR68","doi-asserted-by":"crossref","unstructured":"Zhang, D., Jayasena, N., Lyashevsky, A., Greathouse, J. L., Xu, L., & Ignatowski, M. (2014). Top-pim: Throughput-oriented programmable processing in memory. In Proceedings of the 23rd international symposium on high-performance parallel and distributed computing, (pp. 85\u201398)","DOI":"10.1145\/2600212.2600213"},{"key":"1974_CR69","doi-asserted-by":"crossref","unstructured":"Asghari-Moghaddam, H., Son, Y. H., Ahn, J. H., & Kim, N. S. (2016). Chameleon: Versatile and practical near-dram acceleration architecture for large memory systems. In 2016 49th Annual IEEE\/ACM international symposium on microarchitecture (MICRO) (pp. 1\u201313). IEEE","DOI":"10.1109\/MICRO.2016.7783753"},{"key":"1974_CR70","doi-asserted-by":"crossref","unstructured":"Gao, M., & Kozyrakis, C. (2016). Hrl: Efficient and flexible reconfigurable logic for near-data processing. In 2016 IEEE International symposium on high performance computer architecture (HPCA) (pp. 126\u2013137). Ieee","DOI":"10.1109\/HPCA.2016.7446059"},{"key":"1974_CR71","unstructured":"Guo, Q., Alachiotis, N., Akin, B., Sadi, F., Xu, G., Low, T.-M., Pileggi, L., Hoe, J.C., Franchetti, F.: 3D-stacked memory-side acceleration: Accelerator and system design. WoNDP (2014)"},{"key":"1974_CR72","doi-asserted-by":"crossref","unstructured":"Aga, S., Jeloka, S., Subramaniyan, A., Narayanasamy, S., Blaauw, D., & Das, R. (2017). Compute caches. In: 2017 IEEE International symposium on high performance computer architecture (HPCA), (pp. 481\u2013492). IEEE","DOI":"10.1109\/HPCA.2017.21"},{"key":"1974_CR73","doi-asserted-by":"crossref","unstructured":"Eckert, C., Wang, X., Wang, J., Subramaniyan, A., Iyer, R., Sylvester, D., ... & Das, R. (2018). Neural cache: Bit-serial in-cache acceleration of deep neural networks. In 2018 ACM\/IEEE 45Th Annual international symposium on computer architecture (ISCA), (pp. 383\u2013396). IEEE","DOI":"10.1109\/ISCA.2018.00040"},{"key":"1974_CR74","doi-asserted-by":"crossref","unstructured":"Fujiki, D., Mahlke, S., & Das, R. (2019). Duality cache for data parallel acceleration. In Proceedings of the 46th international symposium on computer architecture, (pp. 397\u2013410)","DOI":"10.1145\/3307650.3322257"},{"key":"1974_CR75","doi-asserted-by":"crossref","unstructured":"Kang, M., Keel, M.-S., Shanbhag, N. R., Eilert, S., & Curewitz, K. (2014). An energy-efficient vlsi architecture for pattern recognition via deep embedding of computation in sram. In: 2014 IEEE International conference on acoustics, speech and signal processing (ICASSP), (pp. 8326\u20138330). IEEE","DOI":"10.1109\/ICASSP.2014.6855225"},{"key":"1974_CR76","doi-asserted-by":"crossref","unstructured":"Chen, P.-Y., Peng, X., & Yu, S. (2017). Neurosim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures. In 2017 IEEE International electron devices meeting (IEDM), (pp. 6\u20131). IEEE","DOI":"10.1109\/IEDM.2017.8268337"},{"key":"1974_CR77","doi-asserted-by":"crossref","unstructured":"Seshadri, V., Kim, Y., Fallin, C., Lee, D., Ausavarungnirun, R., Pekhimenko, G., ... & Mowry, T. C. (2013). Rowclone: Fast and energy-efficient in-dram bulk data copy and initialization. In Proceedings of the 46th Annual IEEE\/ACM international symposium on microarchitecture, (pp. 185\u2013197)","DOI":"10.1145\/2540708.2540725"},{"key":"1974_CR78","doi-asserted-by":"crossref","unstructured":"Kim, J. S., Patel, M., Hassan, H., Orosa, L., & Mutlu, O. (2019). D-range: Using commodity dram devices to generate true random numbers with low latency and high throughput. In 2019 IEEE International symposium on high performance computer architecture (HPCA), (pp. 582\u2013595). IEEE","DOI":"10.1109\/HPCA.2019.00011"},{"key":"1974_CR79","doi-asserted-by":"crossref","unstructured":"Gao, F., Tziantzioulis, G., & Wentzlaff, D. (2019). Computedram: In-memory compute using off-the-shelf drams. In Proceedings of the 52nd Annual IEEE\/ACM international symposium on microarchitecture, (pp. 100\u2013113)","DOI":"10.1145\/3352460.3358260"},{"key":"1974_CR80","doi-asserted-by":"crossref","unstructured":"Li, S., Niu, D., Malladi, K. T., Zheng, H., Brennan, B., & Xie, Y. (2017). Drisa: A dram-based reconfigurable in-situ accelerator. In Proceedings of the 50th Annual IEEE\/ACM international symposium on microarchitecture, (pp. 288\u2013301)","DOI":"10.1145\/3123939.3123977"},{"key":"1974_CR81","doi-asserted-by":"crossref","unstructured":"Hajinazar, N., Oliveira, G. F., Gregorio, S., Ferreira, J. D., Ghiasi, N. M., Patel, M., ... & Mutlu, O. (2021). Simdram: a framework for bit-serial simd processing using dram. In Proceedings of the 26th ACM international conference on architectural support for programming languages and operating systems, (pp. 329\u2013345)","DOI":"10.1145\/3445814.3446749"},{"key":"1974_CR82","doi-asserted-by":"crossref","unstructured":"Olgun, A., Patel, M., Ya\u011fl\u0131k\u00e7\u0131, A. G., Luo, H., Kim, J. S., Bostanc\u0131, F. N., ... & Mutlu, O. (2021). Quac-trng: High-throughput true random number generation using quadruple row activation in commodity dram chips. In 2021 ACM\/IEEE 48th annual international symposium on computer architecture (ISCA), (pp. 944\u2013957). IEEE","DOI":"10.1109\/ISCA52012.2021.00078"},{"key":"1974_CR83","doi-asserted-by":"crossref","unstructured":"Li, S., Xu, C., Zou, Q., Zhao, J., Lu, Y., & Xie, Y. (2016). Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. In Proceedings of the 53rd annual design automation conference, (pp. 1\u20136)","DOI":"10.1145\/2897937.2898064"},{"key":"1974_CR84","doi-asserted-by":"crossref","unstructured":"Angizi, S., He, Z., & Fan, D. (2018). Pima-logic: A novel processing-in-memory architecture for highly flexible and energy-efficient logic computation. In: Proceedings of the 55th annual design automation conference, (pp. 1\u20136)","DOI":"10.1145\/3195970.3196092"},{"key":"1974_CR85","doi-asserted-by":"crossref","unstructured":"Angizi, S., Sun, J., Zhang, W., & Fan, D. (2019). Aligns: A processing-in-memory accelerator for dna short read alignment leveraging sot-mram. In Proceedings of the 56th Annual Design Automation Conference 2019, (pp. 1\u20136)","DOI":"10.1145\/3316781.3317764"},{"issue":"11","key":"1974_CR86","doi-asserted-by":"publisher","first-page":"1429","DOI":"10.1016\/j.mejo.2014.06.006","volume":"45","author":"Y Levy","year":"2014","unstructured":"Levy, Y., Bruck, J., Cassuto, Y., Friedman, E. G., Kolodny, A., Yaakobi, E., & Kvatinsky, S. (2014). Logic operations in memory using a memristive akers array. Microelectronics Journal, 45(11), 1429\u20131437.","journal-title":"Microelectronics Journal"},{"key":"1974_CR87","doi-asserted-by":"crossref","unstructured":"Kvatinsky, S., Belousov, D., Liman, S., Satat, G., Wald, N., Friedman, E. G., & Weiser, U. C. (2014). Magic\u2013memristor-aided logic. IEEE Transactions on Circuits and Systems II: Express Briefs, 61(11), 895\u2013899.","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"1974_CR88","doi-asserted-by":"crossref","unstructured":"Kvatinsky, S., Kolodny, A., Weiser, U. C., & Friedman, E. G. (2011). Memristor-based imply logic design procedure. In: 2011 IEEE 29th International conference on computer design (ICCD), (pp. 142\u2013147). IEEE","DOI":"10.1109\/ICCD.2011.6081389"},{"key":"1974_CR89","doi-asserted-by":"crossref","unstructured":"Kvatinsky, S., Satat, G., Wald, N., Friedman, E. G., Kolodny, A., & Weiser, U. C. (2013). Memristor-based material implication (imply) logic: Design principles and methodologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,22(10), 2054\u20132066","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"1974_CR90","doi-asserted-by":"crossref","unstructured":"Gaillardon, P. E., Amar\u00fa, L., Siemon, A., Linn, E., Waser, R., Chattopadhyay, A., & De Micheli, G. (2016). The programmable logic-in-memory (plim) computer. In: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), (pp. 427\u2013432). Ieee","DOI":"10.3850\/9783981537079_0970"},{"key":"1974_CR91","doi-asserted-by":"crossref","unstructured":"Bhattacharjee, D., Devadoss, R., & Chattopadhyay, A. (2017). Revamp: Reram based vliw architecture for in-memory computing. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, (pp. 782\u2013787). IEEE","DOI":"10.23919\/DATE.2017.7927095"},{"key":"1974_CR92","doi-asserted-by":"crossref","unstructured":"Hamdioui, S., Xie, L., Du Nguyen, H. A., Taouil, M., Bertels, K., Corporaal, H., ... & Van Lunteren, J. (2015). Memristor based computation-in-memory architecture for data-intensive applications. In 2015 Design, automation & test in Europe conference & exhibition (DATE), (pp. 1718\u20131725). IEEE","DOI":"10.7873\/DATE.2015.1136"},{"key":"1974_CR93","doi-asserted-by":"crossref","unstructured":"Xie, L., Du\u00a0Nguyen, H. A., Taouil, M., Hamdioui, S., & Bertels, K. (2015). Fast boolean logic mapped on memristor crossbar. In 2015 33rd IEEE International conference on computer design (ICCD), (pp. 335\u2013342). IEEE","DOI":"10.1109\/ICCD.2015.7357122"},{"key":"1974_CR94","doi-asserted-by":"crossref","unstructured":"Yu, J., Du\u00a0Nguyen, H. A., Xie, L., Taouil, M., & Hamdioui, S. (2018). Memristive devices for computation-in-memory. In 2018 Design, automation & test in Europe conference & exhibition (DATE), (pp. 1646\u20131651). IEEE","DOI":"10.23919\/DATE.2018.8342278"},{"key":"1974_CR95","doi-asserted-by":"crossref","unstructured":"Zheng, L., Shin, S., Lloyd, S., Gokhale, M., Kim, K., & Kang, S.-M. (2016). Rram-based tcams for pattern search. In 2016 IEEE International symposium on circuits and systems (ISCAS), (pp. 1382\u20131385). IEEE","DOI":"10.1109\/ISCAS.2016.7527507"},{"key":"1974_CR96","doi-asserted-by":"crossref","unstructured":"Xi, Y., Gao, B., Tang, J., Chen, A., Chang, M. F., Hu, X. S., & Wu, H. (2020). In-memory learning with analog resistive switching memory: A review and perspective. Proceedings of the IEEE, 109(1), 14\u201342.","DOI":"10.1109\/JPROC.2020.3004543"},{"key":"1974_CR97","doi-asserted-by":"crossref","unstructured":"Ankit, A., El Hajj, I., Chalamalasetti, S. R., Agarwal, S., Marinella, M., Foltin, M., & Roy, K. (2020). Panther: A programmable architecture for neural network training harnessing energy-efficient reram. IEEE Transactions on Computers, 69(8), 1128\u20131142.","DOI":"10.1109\/TC.2020.2998456"},{"key":"1974_CR98","doi-asserted-by":"crossref","unstructured":"Ambrosi, J., Ankit, A., Antunes, R., Chalamalasetti, S. R., Chatterjee, S., El Hajj, I., ... & Strachan, J. P. (2018). Hardware-software co-design for an analog-digital accelerator for machine learning. In 2018 IEEE International conference on rebooting computing (ICRC), (pp. 1\u201313). IEEE","DOI":"10.1109\/ICRC.2018.8638612"},{"key":"1974_CR99","doi-asserted-by":"crossref","unstructured":"Bruel, P., Chalamalasetti, S. R., Dalton, C., El Hajj, I., Goldman, A., Graves, C., ... & Strachan, J. P. (2017). Generalize or die: Operating systems support for memristor-based accelerators. In 2017 IEEE International conference on rebooting computing (ICRC), (pp. 1\u20138). IEEE","DOI":"10.1109\/ICRC.2017.8123649"},{"key":"1974_CR100","doi-asserted-by":"crossref","unstructured":"Huang, S., Ankit, A., Silveira, P., Antunes, R., Chalamalasetti, S. R., El Hajj, I., ... & Milojicic, D. (2021). Mixed precision quantization for reram-based dnn inference accelerators. In Proceedings of the 26th Asia and South Pacific design automation conference, (pp. 372\u2013377)","DOI":"10.1145\/3394885.3431554"},{"key":"1974_CR101","doi-asserted-by":"crossref","unstructured":"Ferreira, J. D., Falcao, G., G\u00f3mez-Luna, J., Alser, M., Orosa, L., Sadrosadati, M., ... & Mutlu, O. (2022). pLUTo: Enabling massively parallel computation in dram via lookup tables. In 2022 55th IEEE\/ACM International symposium on microarchitecture (MICRO), (pp. 900\u2013919). IEEE","DOI":"10.1109\/MICRO56248.2022.00067"},{"key":"1974_CR102","doi-asserted-by":"crossref","unstructured":"Das, P., Sutradhar, P. R., Indovina, M., Dinakarrao, S. M. P., & Ganguly, A. (2022). Implementation and evaluation of deep neural networks in commercially available processing in memory hardware. In 2022 IEEE 35th International system-on-chip conference (SOCC), (pp. 1\u20136). IEEE","DOI":"10.1109\/SOCC56010.2022.9908126"},{"key":"1974_CR103","unstructured":"Nider, J., Mustard, C., Zoltan, A., Ramsden, J., Liu, L., Grossbard, J., ... & Fedorova, A. (2021). A case study of processing-in-memory in off-the-shelf systems. In USENIX annual technical conference, (pp. 117\u2013130)"},{"key":"1974_CR104","unstructured":"Abou-Assaleh, T., & Ai, W. (2004). Survey of global regular expression print (grep) tools. Proceedings of Citeseer, Topics in Program Comprehension, 1\u20138"},{"key":"1974_CR105","doi-asserted-by":"crossref","unstructured":"G\u00f3mez-Luna, J., Guo, Y., Brocard, S., Legriel, J., Cimadomo, R., Oliveira, G. F., ... & Mutlu, O. (2022). An experimental evaluation of machine learning training on a real processing-in-memory system. arXiv:2207.07886","DOI":"10.1109\/ISVLSI54635.2022.00064"},{"key":"1974_CR106","doi-asserted-by":"crossref","unstructured":"G\u00f3mez-Luna, J., Guo, Y., Brocard, S., Legriel, J., Cimadomo, R., Oliveira, G. F., ... & Mutlu, O. (2022). Machine learning training on a real processing-in-memory system. In 2022 IEEE Computer society annual symposium on VLSI (ISVLSI), (pp. 292\u2013295). IEEE","DOI":"10.1109\/ISVLSI54635.2022.00064"},{"key":"1974_CR107","doi-asserted-by":"crossref","unstructured":"Giannoula, C., Fernandez, I., G\u00f3mez-Luna, J., Koziris, N., Goumas, G., Mutlu, O. (2022). Sparsep: Towards efficient sparse matrix vector multiplication on real processing-in-memory systems. arXiv:2201.05072","DOI":"10.1109\/ISVLSI54635.2022.00063"},{"key":"1974_CR108","doi-asserted-by":"crossref","unstructured":"Kang, H., Zhao, Y., Blelloch, G. E., Dhulipala, L., Gu, Y., McGuffey, C., & Gibbons, P. B. (2022). Pim-tree: A skew-resistant index for processing-in-memory. arXiv:2211.10516","DOI":"10.14778\/3574245.3574275"},{"key":"1974_CR109","unstructured":"Lavenier, D., Deltel, C., Furodet, D., & Roy, J.-F. (2016). Blast on upmem. PhD thesis, INRIA Rennes-Bretagne Atlantique"},{"issue":"3","key":"1974_CR110","doi-asserted-by":"publisher","first-page":"403","DOI":"10.1016\/S0022-2836(05)80360-2","volume":"215","author":"SF Altschul","year":"1990","unstructured":"Altschul, S. F., Gish, W., Miller, W., Myers, E. W., & Lipman, D. J. (1990). Basic local alignment search tool. Journal of Molecular Biology, 215(3), 403\u2013410.","journal-title":"Journal of Molecular Biology"},{"key":"1974_CR111","doi-asserted-by":"crossref","unstructured":"Lavenier, D., Cimadomo, R., & Jodin, R. (2020). Variant calling parallelization on processor-in-memory architecture. In 2020 IEEE International Conference on Bioinformatics and Biomedicine (BIBM), (pp. 204\u2013207). IEEE","DOI":"10.1109\/BIBM49941.2020.9313351"},{"key":"1974_CR112","doi-asserted-by":"crossref","unstructured":"Diab, S., Nassereldine, A., Alser, M., G\u00f3mez-Luna, J., Mutlu, O., & Hajj, I. E. (2022). A framework for high-throughput sequence alignment using real processing-in-memory systems. arXiv:2208.01243","DOI":"10.1093\/bioinformatics\/btad155"},{"key":"1974_CR113","unstructured":"Carrinho, P. UPMEM GEMM. Accessed: 2025-09-14. https:\/\/github.com\/PedroCarrinhoRibeiro\/UPMEMspsGEMM"},{"key":"1974_CR114","unstructured":"Carrinho, P. UPMEM MLP. Accessed: 2025-09-14. https:\/\/github.com\/PedroCarrinhoRibeiro\/UPMEMspsMLP"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-025-01974-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11265-025-01974-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-025-01974-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,17]],"date-time":"2025-11-17T02:11:48Z","timestamp":1763345508000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11265-025-01974-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11,17]]},"references-count":114,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2026,6]]}},"alternative-id":["1974"],"URL":"https:\/\/doi.org\/10.1007\/s11265-025-01974-7","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,11,17]]},"assertion":[{"value":"21 March 2025","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 September 2025","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 September 2025","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"17 November 2025","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}],"article-number":"1"}}