{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,22]],"date-time":"2026-04-22T19:27:14Z","timestamp":1776886034458,"version":"3.51.2"},"reference-count":33,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2016,6,3]],"date-time":"2016-06-03T00:00:00Z","timestamp":1464912000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Wireless Pers Commun"],"published-print":{"date-parts":[[2017,6]]},"DOI":"10.1007\/s11277-016-3385-7","type":"journal-article","created":{"date-parts":[[2016,6,3]],"date-time":"2016-06-03T08:57:37Z","timestamp":1464944257000},"page":"2259-2273","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":16,"title":["An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box"],"prefix":"10.1007","volume":"94","author":[{"given":"Sridevi Sathya","family":"Priya","sequence":"first","affiliation":[]},{"given":"Palanivel","family":"Karthigaikumar","sequence":"additional","affiliation":[]},{"given":"N. M.","family":"Siva Mangai","sequence":"additional","affiliation":[]},{"given":"P.","family":"Kirti Gaurav Das","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,6,3]]},"reference":[{"key":"3385_CR1","unstructured":"Liberatori, M., Otero, F., Bonadero, J. C., & Castifieira, J. (2007). AES-128 Cipher. High speed, low cost FPGA implementation. In 3rd southern proceedings of the IEEE conference on programmable logic, SPL\u201907 (pp. 195\u2013198)."},{"key":"3385_CR2","doi-asserted-by":"crossref","first-page":"1014","DOI":"10.1016\/j.mejo.2014.05.004","volume":"45","author":"RR Farashahi","year":"2014","unstructured":"Farashahi, R. R., Rashidi, B., & Sayedi, S. M. (2014). FPGA based fast and high-throughput 2-slow returning 128-bit AES encryption algorithm. Microelectronic Journal, 45, 1014\u20131025.","journal-title":"Microelectronic Journal"},{"issue":"1","key":"3385_CR3","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1049\/iet-ifs:20060059","volume":"1","author":"T Good","year":"2007","unstructured":"Good, T., & Benaissa, M. (2007). Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment). IET Information Security, 1(1), 1\u201310.","journal-title":"IET Information Security"},{"issue":"9","key":"3385_CR4","first-page":"1","volume":"3","author":"K Sireesha","year":"2013","unstructured":"Sireesha, K., & Madhava Rao, S. (2013). A novel approach of area optimized and pipelined FPGA implementation of AES encryption and decryption. International Journal of Scientific Research, 3(9), 1\u20135.","journal-title":"International Journal of Scientific Research"},{"key":"3385_CR5","doi-asserted-by":"crossref","unstructured":"Gielata, A., Russek, P., & Wiatr, K. (2008). AES hardware implementation in FPGA for algorithm acceleration purpose. In Proceedings of the international conference on signals and electronic systems (ICSES) (pp. 137\u2013140), September 14\u201317, 2008.","DOI":"10.1109\/ICSES.2008.4673377"},{"issue":"2","key":"3385_CR6","first-page":"110","volume":"1","author":"S Adib El","year":"2012","unstructured":"El Adib, S., & Raissouni, N. (2012). AES encryption algorithm hardware implementation architecture: Resource and execution time optimization. International Journal of Information and Network Security, 1(2), 110\u2013118.","journal-title":"International Journal of Information and Network Security"},{"key":"3385_CR7","doi-asserted-by":"crossref","unstructured":"Good, T., & Benaissa, M. (2005). AES on FPGA from the fastest to the smallest. Lecture Notes Computer Science (Vol. 3659, pp. 427\u2013440).","DOI":"10.1007\/11545262_31"},{"issue":"15","key":"3385_CR8","doi-asserted-by":"crossref","first-page":"0975","DOI":"10.5120\/331-502","volume":"1","author":"Ayushi","year":"2010","unstructured":"Ayushi. (2010). A symmetric key cryptographic algorithm. International Journal of Computer Applications, 1(15), 0975\u20138887.","journal-title":"International Journal of Computer Applications"},{"key":"3385_CR9","first-page":"13","volume":"1","author":"M Feldhofer","year":"2005","unstructured":"Feldhofer, M., Wolkerstorfer, J., & Rijmen, V. (2005). AES implementation on a grain of sand. Proceedings of the Institute of Electrical and Electronics Engineers, Information Security, 1, 13\u201320.","journal-title":"Proceedings of the Institute of Electrical and Electronics Engineers, Information Security"},{"issue":"9\u201310","key":"3385_CR10","first-page":"265","volume":"56","author":"M Mali","year":"2005","unstructured":"Mali, M., Novak, F., & Bi, A. (2005). Hardware implementation of AES algorithm. Journal of Electrical Engineering, 56(9\u201310), 265\u2013269.","journal-title":"Journal of Electrical Engineering"},{"key":"3385_CR11","unstructured":"Advanced Encryption Standard (AES), November 26, 2001."},{"issue":"4","key":"3385_CR12","first-page":"406","volume":"8","author":"SM Wadi","year":"2013","unstructured":"Wadi, S. M., & Zainal, N. (2013). A low cost implementation of modified advanced encryption standard algorithm using 8085a microprocessor. Journal of Engineering Science and Technology, 8(4), 406\u2013415.","journal-title":"Journal of Engineering Science and Technology"},{"issue":"4","key":"3385_CR13","doi-asserted-by":"crossref","first-page":"43","DOI":"10.5121\/ijnsa.2014.6404","volume":"6","author":"R Masram","year":"2014","unstructured":"Masram, R., Shahare, V., Abraham, J., & Moona, R. (2014). Analysis and comparison of symmetric key cryptographic algorithms based on various file features. International Journal of Network Security & Its Applications (IJNSA), 6(4), 43\u201352.","journal-title":"International Journal of Network Security & Its Applications (IJNSA)"},{"issue":"6","key":"3385_CR14","doi-asserted-by":"crossref","first-page":"347","DOI":"10.1016\/j.mejo.2010.04.004","volume":"41","author":"P Karthigai Kumar","year":"2010","unstructured":"Karthigaikumar, P., & Baskaran, K. (2010). An ASIC implementation of low power and high throughput blowfish crypto algorithm. Microelectronics Journal, 41(6), 347\u2013355.","journal-title":"Microelectronics Journal"},{"key":"3385_CR15","doi-asserted-by":"crossref","unstructured":"Canright, D. (2005). A very compact S-Box for AES. In Proceedings of CHES, Edinburgh, U.K., LNCS (Vol. 3659, pp. 441\u2013456).","DOI":"10.1007\/11545262_32"},{"key":"3385_CR16","unstructured":"Paar, C. (1994). Efficient VLSI architectures for bit-parallel computation in Galois fields. Ph.D. dissertation, Institute for Experimental Mathematics, Essen University, Essen, June 1994."},{"issue":"9","key":"3385_CR17","doi-asserted-by":"crossref","first-page":"957","DOI":"10.1109\/TVLSI.2004.832943","volume":"12","author":"X Zhang","year":"2004","unstructured":"Zhang, X., & Parhi, K. K. (2004). High-speed VLSI architectures for the AES Algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(9), 957\u2013967.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"issue":"12","key":"3385_CR18","doi-asserted-by":"crossref","first-page":"1753","DOI":"10.1109\/TVLSI.2009.2025952","volume":"18","author":"T Good","year":"2010","unstructured":"Good, T., & Benaissa, M. (2010). 692-nW Advanced Encryption Standard (AES) on a 0.13- m CMOS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(12), 1753\u20131757.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"3385_CR19","unstructured":"Zhang, X., Yan, G., & Dong, L. (2015). Hardware implementation of compact AES S-box. IAENG International Journal of Computer Science, 125\u2013131."},{"issue":"3","key":"3385_CR20","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1109\/LES.2010.2052401","volume":"2","author":"I Hammad","year":"2010","unstructured":"Hammad, I., El-Sankary, K., & El-Masry, E. (2010). High-speed AES encryptor with efficient merging techniques. IEEE Embedded Systems Letters, 2(3), 67\u201371.","journal-title":"IEEE Embedded Systems Letters"},{"key":"3385_CR21","doi-asserted-by":"crossref","unstructured":"Wadi, S. M., & Zainal, N. (2013). Rapid encryption method based on AES algorithm for grey scale HD image encryption. In Elsevier proceedings of the 4th international conference on electrical engineering and informatics (ICEEI 2013).","DOI":"10.1016\/j.protcy.2013.12.161"},{"key":"3385_CR22","volume-title":"An AES crypto chip using a high-speed parallel pipelined architecture","author":"SM Yoo","year":"2005","unstructured":"Yoo, S. M., Kotturi, D., Pan, D. W., & Blizzard, J. (2005). An AES crypto chip using a high-speed parallel pipelined architecture. Amsterdam: Elsevier."},{"issue":"4","key":"3385_CR23","doi-asserted-by":"crossref","first-page":"366","DOI":"10.1109\/TC.2006.49","volume":"55","author":"A Hodjat","year":"2006","unstructured":"Hodjat, A., & Verbauwhede, I. (2006). Area-throughput trade-offs for fully pipelined 30 to 70 Gbits\/s AES processors. IEEE Transactions on Computers, 55(4), 366\u2013372.","journal-title":"IEEE Transactions on Computers"},{"key":"3385_CR24","doi-asserted-by":"crossref","unstructured":"Wang, S.-S., & Ni, W.-S. (2004). An efficient FPGA implementation of advanced encryption standard algorithm. In Proceedings of IEEE international symposium on circuits and systems, May, 2004.","DOI":"10.1109\/ISCAS.2004.1329342"},{"issue":"10","key":"3385_CR25","doi-asserted-by":"crossref","first-page":"1153","DOI":"10.1109\/TCSII.2006.882217","volume":"53","author":"X Zhang","year":"2006","unstructured":"Zhang, X., & Parhi, K. K. (2006). On the optimum constructions of composite field for the AES algorithm. IEEE Transactions on Circuits and Systems, 53(10), 1153\u20131157.","journal-title":"IEEE Transactions on Circuits and Systems"},{"key":"3385_CR26","doi-asserted-by":"crossref","unstructured":"Chang, C., Husang, C.-W., Tai, H.-Y., Lin, M.-Y., & Hu, T.-K. (2007). 8-Bit AES FPGA implementation using Block RAM. In Proceedings of the 33 annual conference of the IEEE Industrial Electronics Society (IECON) (pp. 2654\u20132659), Taipei, Taiwan, November 5\u20138, 2007.","DOI":"10.1109\/IECON.2007.4460363"},{"issue":"2","key":"3385_CR27","first-page":"53","volume":"1","author":"G Singh","year":"2011","unstructured":"Singh, G., & Mehra, R. (2011). FPGA based high speed and area efficient AES encryption for data security. International Journal of Research and Innovation in Computer Engineering, 1(2), 53\u201356.","journal-title":"International Journal of Research and Innovation in Computer Engineering"},{"key":"3385_CR28","doi-asserted-by":"crossref","unstructured":"Kumar, S., Sharma, V. K., & Mahapatra, K. K. (2013). Low latency VLSI architecture of S-box for AES encryption. In International conference on circuits, power and computing technologies (ICCPCT) (pp. 694\u2013698), 20\u201321 March 2013.","DOI":"10.1109\/ICCPCT.2013.6528906"},{"key":"3385_CR29","unstructured":"Huang, C.-W., Chang, C.-J., Lin, M.-Y., & Tai, H.-Y. (2007). Compact FPGA implementation of 32-bits AES algorithm using block RAM. In Proceedings of the IEEE region 10 conference TENCON (pp. 1\u20134)."},{"issue":"11","key":"3385_CR30","doi-asserted-by":"crossref","first-page":"2225","DOI":"10.1002\/sec.651","volume":"7","author":"K Rahimunnisa","year":"2012","unstructured":"Rahimunnisa, K., Karthigaikumar, P., Rasheed, S., & Jayakumar, J. (2012). FPGA implementation of AES algorithm for high throughput using folded parallel architecture. Security and Communication Networks, 7(11), 2225\u20132236.","journal-title":"Security and Communication Networks"},{"key":"3385_CR31","doi-asserted-by":"crossref","first-page":"1160","DOI":"10.1016\/j.compeleceng.2011.06.003","volume":"37","author":"L Ali","year":"2011","unstructured":"Ali, L., Aris, I., Hossain, F. S., & Roy, N. (2011). Design of an ultra high speed AES processor for next generation IT security. International Journal of Computers and Electrical Engineering, 37, 1160\u20131170.","journal-title":"International Journal of Computers and Electrical Engineering"},{"key":"3385_CR32","doi-asserted-by":"crossref","unstructured":"Wong, M.M., & Wong, M. L. D. (2010). A high throughput, low power compact AES S-box implementation using composite field arithmetic and algebraic normal form representation. In 2nd Asia IEEE symposium on quality electronic design.","DOI":"10.1109\/ASQED.2010.5548317"},{"issue":"3","key":"3385_CR33","doi-asserted-by":"crossref","first-page":"117","DOI":"10.5121\/ijcis.2012.2311","volume":"2","author":"K Rahimunnisa","year":"2012","unstructured":"Rahimunnisa, K., Priya Zach, M., Suresh Kumar, S., & Jayakumar, J. (2012). Architectural optimization of AES transformations and key expansion. International Journal on Cryptography and Information Security (IJCIS), 2(3), 117\u2013130.","journal-title":"International Journal on Cryptography and Information Security (IJCIS)"}],"container-title":["Wireless Personal Communications"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11277-016-3385-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-016-3385-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-016-3385-7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-016-3385-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,9]],"date-time":"2019-09-09T03:05:46Z","timestamp":1567998346000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11277-016-3385-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,6,3]]},"references-count":33,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017,6]]}},"alternative-id":["3385"],"URL":"https:\/\/doi.org\/10.1007\/s11277-016-3385-7","relation":{},"ISSN":["0929-6212","1572-834X"],"issn-type":[{"value":"0929-6212","type":"print"},{"value":"1572-834X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,6,3]]}}}