{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,13]],"date-time":"2026-05-13T17:20:46Z","timestamp":1778692846837,"version":"3.51.4"},"reference-count":25,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T00:00:00Z","timestamp":1638144000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T00:00:00Z","timestamp":1638144000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Wireless Pers Commun"],"published-print":{"date-parts":[[2022,5]]},"DOI":"10.1007\/s11277-021-09407-x","type":"journal-article","created":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T04:02:31Z","timestamp":1638158551000},"page":"1297-1315","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors"],"prefix":"10.1007","volume":"124","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4432-339X","authenticated-orcid":false,"given":"K.","family":"Gavaskar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Malathi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Ravivarma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V. Krithika","family":"Devi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Megala","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S. Megaraj","family":"Begam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2021,11,29]]},"reference":[{"issue":"13","key":"9407_CR1","doi-asserted-by":"publisher","first-page":"2050214","DOI":"10.1142\/S021812662050214X","volume":"29","author":"S Elango","year":"2020","unstructured":"Elango, S., & Sampath, P. (2020). Implementation of high performance hierarchy-based parallel signed multiplier for cryptosystems. Journal of Circuits, Systems and Computers, 29(13), 2050214.","journal-title":"Journal of Circuits, Systems and Computers"},{"issue":"11","key":"9407_CR2","doi-asserted-by":"publisher","first-page":"7795","DOI":"10.1007\/s13369-014-1329-7","volume":"39","author":"KN Vijeyakumar","year":"2014","unstructured":"Vijeyakumar, K. N., Sumathy, V., & Elango, S. (2014). VLSI implementation of area-efficient truncated modified booth multiplier for signal processing applications. Arabian Journal for Science and Engineering, 39(11), 7795\u20137806.","journal-title":"Arabian Journal for Science and Engineering"},{"key":"9407_CR3","doi-asserted-by":"crossref","unstructured":"Gavaskar, K., & Ragupathy U. S. (2014). An efficient design and comparative analysis of low power memory cell structures. In 2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE). IEEE.","DOI":"10.1109\/ICGCCEE.2014.6922280"},{"issue":"10","key":"9407_CR4","doi-asserted-by":"publisher","first-page":"2973","DOI":"10.1109\/TC.2016.2516016","volume":"65","author":"P Sakellariou","year":"2016","unstructured":"Sakellariou, P., & Paliouras, V. (2016). Application-specific low-power multipliers. IEEE Transactions on Computers, 65(10), 2973\u20132985.","journal-title":"IEEE Transactions on Computers"},{"issue":"4","key":"9407_CR5","doi-asserted-by":"publisher","first-page":"2311","DOI":"10.1007\/s11277-019-06523-7","volume":"108","author":"K Gavaskar","year":"2019","unstructured":"Gavaskar, K., Ragupathy, U. S., & Malini, V. (2019). Design of novel SRAM cell using hybrid VLSI techniques for low leakage and high speed in embedded memories. Wireless Personal Communications, 108(4), 2311\u20132339.","journal-title":"Wireless Personal Communications"},{"key":"9407_CR6","doi-asserted-by":"crossref","unstructured":"Gavaskar, K., et al. (2020). Design and analysis of 8-bit stable SRAM for ultra low power applications. In 2020 5th International Conference on Devices, Circuits and Systems (ICDCS). IEEE.","DOI":"10.1109\/ICDCS48716.2020.243585"},{"issue":"05","key":"9407_CR7","doi-asserted-by":"publisher","first-page":"1850077","DOI":"10.1142\/S0218126618500779","volume":"27","author":"KN Vijeyakumar","year":"2018","unstructured":"Vijeyakumar, K. N., Elango, S., & Kalaiselvi, S. (2018). VLSI implementation of high speed energy-efficient truncated multiplier. Journal of Circuits, Systems and Computers, 27(05), 1850077.","journal-title":"Journal of Circuits, Systems and Computers"},{"issue":"1","key":"9407_CR8","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/s12046-018-1017-5","volume":"44","author":"D Malathi","year":"2019","unstructured":"Malathi, D., & Gomathi, M. (2019). Design of inductively degenerated common source RF CMOS low noise amplifier. S\u0101dhan\u0101, 44(1), 1\u20139.","journal-title":"S\u0101dhan\u0101"},{"key":"9407_CR9","doi-asserted-by":"crossref","unstructured":"Hanuman, C. R. S., & Kamala J. (2018) Hardware implementation of 24-bit vedic multiplier in 32-bit floating-point divider. In 2018 4th International Conference on Electrical, Electronics and System Engineering (ICEESE). IEEE.","DOI":"10.1109\/ICEESE.2018.8703551"},{"key":"9407_CR10","doi-asserted-by":"crossref","unstructured":"Dalmia, P., et al. (2018) Novel high speed vedic multiplier proposal incorporating adder based on quaternary signed digit number system. In 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). IEEE.","DOI":"10.1109\/VLSID.2018.78"},{"key":"9407_CR11","doi-asserted-by":"crossref","unstructured":"Gavaskar, K., et al. (2020) Low power design of 4-bit simultaneous counter using digital switching circuits for low range counting applications. In 2020 5th International Conference on Devices, Circuits and Systems (ICDCS). IEEE, .","DOI":"10.1109\/ICDCS48716.2020.243607"},{"key":"9407_CR12","doi-asserted-by":"crossref","unstructured":"Ram, G. C., et al. (2016) VLSI architecture for delay efficient 32-bit multiplier using vedic mathematic sutras. In 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE.","DOI":"10.1109\/RTEICT.2016.7808160"},{"issue":"6","key":"9407_CR13","doi-asserted-by":"publisher","first-page":"804","DOI":"10.1109\/TC.2018.2890222","volume":"68","author":"W Liu","year":"2018","unstructured":"Liu, W., et al. (2018). Design and analysis of approximate redundant binary multipliers. IEEE Transactions on Computers, 68(6), 804\u2013819.","journal-title":"IEEE Transactions on Computers"},{"issue":"11","key":"9407_CR14","doi-asserted-by":"publisher","first-page":"5627","DOI":"10.1166\/jctn.2017.6995","volume":"14","author":"D Malathi","year":"2017","unstructured":"Malathi, D., & MuthamilSelvi, P. (2017). Low power delay insensitive FIR filter architecture. Journal of Computational and Theoretical Nanoscience, 14(11), 5627\u20135631.","journal-title":"Journal of Computational and Theoretical Nanoscience"},{"issue":"3","key":"9407_CR15","doi-asserted-by":"publisher","first-page":"381","DOI":"10.1049\/iet-cds.2019.0246","volume":"14","author":"S Perri","year":"2020","unstructured":"Perri, S., et al. (2020). Parallel architecture of power-of-two multipliers for FPGAs. IET Circuits, Devices & Systems, 14(3), 381\u2013389.","journal-title":"IET Circuits, Devices & Systems"},{"key":"9407_CR16","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-020-01550-3","author":"I Hussain","year":"2020","unstructured":"Hussain, I., & Saurabh, C. (2020). Fast and high-performing 1-bit full adder circuit based on input switching activity patterns and gate diffusion input technique. Circuits, Systems, and Signal Processing. https:\/\/doi.org\/10.1007\/s00034-020-01550-3","journal-title":"Circuits, Systems, and Signal Processing"},{"key":"9407_CR17","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2019.0373","author":"PB Petrovi\u0107","year":"2020","unstructured":"Petrovi\u0107, P. B. (2020). New current-mode RMS-to-DC converters and four-quadrant multiplier\/divider based on VDTA. IET Circuits, Devices & Systems. https:\/\/doi.org\/10.1049\/iet-cds.2019.0373","journal-title":"IET Circuits, Devices & Systems"},{"key":"9407_CR18","unstructured":"Bandi, V. L., Gamini, P., & Harshith, B. S (2018). Performance analysis of dadda multiplier using modified full adder. International Journal of Innovative Research in Computer and Communication Engineering, 6(2), 126\u2013130."},{"issue":"6","key":"9407_CR19","first-page":"38","volume":"19","author":"RK Kadu","year":"2018","unstructured":"Kadu, R. K., & Adane, D. S. (2018). A novel efficient hardware implementation of elliptic curve cryptography scalar multiplication using vedic multiplier. International Journal of Simulation-Systems, Science & Technology, 19(6), 38-1.","journal-title":"International Journal of Simulation-Systems, Science &amp; Technology"},{"issue":"9","key":"9407_CR20","doi-asserted-by":"publisher","first-page":"45","DOI":"10.31026\/j.eng.2020.09.04","volume":"2","author":"AM Abdul-Hadi","year":"2020","unstructured":"Abdul-Hadi, A. M., & Tawfeeq, F. G. (2020). Performance evaluation of scalar multiplication in elliptic curve cryptography implementation using different multipliers over binary field GF (2233). Journal of Engineering, 2(9), 45\u201364.","journal-title":"Journal of Engineering"},{"issue":"2","key":"9407_CR21","first-page":"270","volume":"11","author":"RK Kadu","year":"2019","unstructured":"Kadu, R. K., & Adane, D. S. (2019). Hardware implementation of efficient elliptic curve scalar multiplication using vedic multiplier. International Journal of Communication Networks and Information Security, 11(2), 270\u2013277.","journal-title":"International Journal of Communication Networks and Information Security"},{"key":"9407_CR22","doi-asserted-by":"crossref","unstructured":"Devi, T. K., Priyanka, E. B., Sakthivel, P., & Sagayaraj, A. S. (2021). Sleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability. Analog Integrated Circuits and Signal Processing, 109, 487\u2013499.","DOI":"10.1007\/s10470-021-01875-2"},{"key":"9407_CR23","unstructured":"Vamsi, A. S. K., & and Ramesh, S. R. (2019) An efficient design of 16 bit mac unit using vedic mathematics. In 2019 International Conference on Communication and Signal Processing (ICCSP). IEEE."},{"key":"9407_CR24","doi-asserted-by":"crossref","unstructured":"Eshack, A., & Krishnakumar, S. (2020) Design of low-power vedic multipliers using pipelining technology. In Proceedings of the Third International Conference on Computational Intelligence and Informatics. Springer, Singapore.","DOI":"10.1007\/978-981-15-1480-7_24"},{"key":"9407_CR25","doi-asserted-by":"crossref","unstructured":"Krishna, A. V., Deepthi, S., Devi, M. N. (2021) Design of 32\u2014Bit MAC unit using vedic multiplier and XOR logic. In Proceedings of International Conference on Recent Trends in Machine Learning, IoT, Smart Cities and Applications. Springer, Singapore.","DOI":"10.1007\/978-981-15-7234-0_68"}],"container-title":["Wireless Personal Communications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-021-09407-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11277-021-09407-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-021-09407-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,6]],"date-time":"2022-05-06T18:12:08Z","timestamp":1651860728000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11277-021-09407-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,29]]},"references-count":25,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2022,5]]}},"alternative-id":["9407"],"URL":"https:\/\/doi.org\/10.1007\/s11277-021-09407-x","relation":{"has-preprint":[{"id-type":"doi","id":"10.21203\/rs.3.rs-194480\/v1","asserted-by":"object"}]},"ISSN":["0929-6212","1572-834X"],"issn-type":[{"value":"0929-6212","type":"print"},{"value":"1572-834X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,11,29]]},"assertion":[{"value":"14 November 2021","order":1,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 November 2021","order":2,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors whose names are listed immediately certify that they have NO affiliations with or involvement in any organization or entity with any financial interest or non-financial interest in the subject matter or materials discussed in this manuscript.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}},{"value":"Agreed.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethics approval"}}]}}