{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T01:50:30Z","timestamp":1781833830465,"version":"3.54.5"},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Wireless Pers Commun"],"published-print":{"date-parts":[[2022,6]]},"DOI":"10.1007\/s11277-022-09510-7","type":"journal-article","created":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T11:02:41Z","timestamp":1642417361000},"page":"3235-3251","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["A Variation Tolerant Nanoscale SRAM for Low Power Wireless Sensor Nodes"],"prefix":"10.1007","volume":"124","author":[{"given":"Vipul","family":"Bhatnagar","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Manoj Kumar","family":"Pandey","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2669-8323","authenticated-orcid":false,"given":"Sujata","family":"Pandey","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2022,1,17]]},"reference":[{"key":"9510_CR1","doi-asserted-by":"publisher","first-page":"2201","DOI":"10.1007\/s11277-021-08462-8","volume":"120","author":"A Sachdeva","year":"2021","unstructured":"Sachdeva, A., & Tomar, V. K. (2021). A Multi-bit error upset immune 12T SRAM cell for 5G satellite communications. Wireless Personal Communications, 120, 2201\u20132225.","journal-title":"Wireless Personal Communications"},{"key":"9510_CR2","doi-asserted-by":"crossref","unstructured":"K.-S. Yeo, W.-L. Goh, Z.-H. Kong, Q-X. Zhang and W.-G. Yeo, (2002) High-performance low-power current sense amplifier using a cross-coupled current-mirror Configuration, IEEE Proceedings - Circuits, Devices and System 149(516): 308\u2013314.","DOI":"10.1049\/ip-cds:20020502"},{"issue":"2","key":"9510_CR3","doi-asserted-by":"publisher","first-page":"85","DOI":"10.1049\/ip-cds:19981601","volume":"145","author":"YK Seng","year":"1998","unstructured":"Seng, Y. K. (1998). New current conveyor for high-speed low-power current sensing. IEEE Proceedings of Devices and Systems, 145(2), 85.","journal-title":"IEEE Proceedings of Devices and Systems"},{"issue":"7","key":"9510_CR4","first-page":"1148","volume":"39","author":"B Witch","year":"2000","unstructured":"Witch, B., Nirschil, T., & Landsiedel, D. S. (2000). (2000) Yield and speed optimization of a latch-type voltage sense amplifier. IEEE Journal of Solid-State Circuit, 39(7), 1148\u20131158.","journal-title":"IEEE Journal of Solid-State Circuit"},{"issue":"6","key":"9510_CR5","doi-asserted-by":"publisher","first-page":"652","DOI":"10.1109\/TVLSI.2004.827566","volume":"12","author":"R Singh","year":"2004","unstructured":"Singh, R., & Baht, N. (2004). An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(6), 652\u2013657.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"issue":"2","key":"9510_CR6","doi-asserted-by":"publisher","first-page":"196","DOI":"10.1109\/TVLSI.2009.2033110","volume":"19","author":"A-T Do","year":"2011","unstructured":"Do, A.-T., Kong, Z. H., Yeo, K. S., & Low, J. Y. S. (2011). Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM. IEEE Transactions on Very Large Scale Integration Systems, 19(2), 196\u2013204.","journal-title":"IEEE Transactions on Very Large Scale Integration Systems"},{"issue":"6","key":"9510_CR7","doi-asserted-by":"publisher","first-page":"781","DOI":"10.1016\/j.mejo.2014.02.015","volume":"45","author":"H Attarzadeh","year":"2014","unstructured":"Attarzadeh, H., & Sharifkhani, M. (2014). An auto calibrated, dual mode SRAM macro using a hybrid offset cancelled sense amplifier. Microelectronics Journal, 45(6), 781\u2013792.","journal-title":"Microelectronics Journal"},{"issue":"4","key":"9510_CR8","doi-asserted-by":"publisher","first-page":"3513","DOI":"10.1007\/s11277-016-3788-5","volume":"94","author":"R Lorenzo","year":"2017","unstructured":"Lorenzo, R., & Chaudhury, S. (2017). A novel SRAM design with a body-bias controller circuit for low leakage, high-speed and improved stability. Wireless Personal Communications, 94(4), 3513\u20133529.","journal-title":"Wireless Personal Communications"},{"issue":"1","key":"9510_CR9","doi-asserted-by":"publisher","first-page":"34","DOI":"10.12720\/ijeee.1.1.34-38","volume":"1","author":"B Reniwal","year":"2013","unstructured":"Reniwal, B., & Vishvakarma, S. K. (2013). A reliable, process-sensitive-tolerant hybrid sense amplifier for ultra low power SRAM. International Journal of Electronics and Electrical Engineering, 1(1), 34\u201338.","journal-title":"International Journal of Electronics and Electrical Engineering"},{"key":"9510_CR10","unstructured":"AK Singh, MM Seong, CMR Prabhu (2013) A proposed eleven-transistor (11-T) CMOS SRAM cell for improved read stability and reduced read power consumption, Journal of Circuits, Systems, and Computers 12(7) 1350062\u20131\u20131350062\u201312."},{"issue":"2","key":"9510_CR11","doi-asserted-by":"publisher","first-page":"823","DOI":"10.1007\/s11277-019-06593-7","volume":"109","author":"K Gavaskar","year":"2019","unstructured":"Gavaskar, K., Ragupathy, U. S., & Malini, V. (2019). Proposed design of 1 KB memory array structure for cache memories. Wireless Personal Communications, 109(2), 823\u2013847.","journal-title":"Wireless Personal Communications"},{"key":"9510_CR12","doi-asserted-by":"publisher","first-page":"2105","DOI":"10.1007\/s11277-018-5807-1","volume":"101","author":"MK Singh","year":"2018","unstructured":"Singh, M. K., & Akashe, S. (2018). Design and enactment of diverse low power techniques based schmitt trigger. Wireless Personal Communications, 101, 2105\u20132125.","journal-title":"Wireless Personal Communications"},{"key":"9510_CR13","doi-asserted-by":"crossref","unstructured":"MA Turi, JG Delgado-Frias (2020) Effective low leakage 6T and 8T FinFET SRAMs: Using cells with reverse-biased FinFETs, near-threshold operation, and power gating. IEEE Transactions on Circuits and Systems II: Express Briefs 67(4): 8736268, pp. 765\u2013769.","DOI":"10.1109\/TCSII.2019.2922921"},{"issue":"3","key":"9510_CR14","doi-asserted-by":"publisher","first-page":"114","DOI":"10.1049\/iet-cdt.2019.0234","volume":"14","author":"R Lorenzo","year":"2020","unstructured":"Lorenzo, R., & Pailly, R. (2020). Single bit-line 11T SRAM cell for low power and improved stability. IET Computers and Digital Techniques, 14(3), 114\u2013121.","journal-title":"IET Computers and Digital Techniques"},{"issue":"2","key":"9510_CR15","doi-asserted-by":"publisher","first-page":"025001","DOI":"10.1088\/1674-4926\/39\/2\/025001","volume":"39","author":"V Bhatnagar","year":"2018","unstructured":"Bhatnagar, V., Kumar, P., & Pandey, S. (2018). A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation (wari) and write-back for half-selected cells. Journal of Semiconductors, 39(2), 025001.","journal-title":"Journal of Semiconductors"},{"issue":"10","key":"9510_CR16","doi-asserted-by":"publisher","first-page":"1031","DOI":"10.1109\/TCSII.2008.926797","volume":"55","author":"Y-C Lai","year":"2008","unstructured":"Lai, Y.-C., & Huang, S. Y. (2008). A resilient and power-efficient automatic-power-down sense amplifier for SRAM design. IEEE Transactions on Circuits and Systems\u2014II: Express briefs, 55(10), 1031.","journal-title":"IEEE Transactions on Circuits and Systems\u2014II: Express briefs"},{"issue":"12","key":"9510_CR17","doi-asserted-by":"publisher","first-page":"878","DOI":"10.1109\/TCSII.2012.2231016","volume":"59","author":"ML Fan","year":"2012","unstructured":"Fan, M. L., Hu, V.P.-H., Chen, Y. N., Su, P., & Chuang, C.-T. (2012). Variability analysis of sense amplifier for FinFET subthreshold SRAM applications\u201d. IEEE Transactions on Circuits and Systems\u2014II: Express Briefs, 59(12), 878\u2013882.","journal-title":"IEEE Transactions on Circuits and Systems\u2014II: Express Briefs"},{"issue":"7","key":"9510_CR18","doi-asserted-by":"publisher","first-page":"2325","DOI":"10.1007\/s00542-019-04708-5","volume":"26","author":"S Pal","year":"2020","unstructured":"Pal, S., Bose, S., & Islam, A. (2020). A low power SRAM cell design for wireless sensor network applications\u201d. Microsystem Technologies, 26(7), 2325\u20132335.","journal-title":"Microsystem Technologies"},{"key":"9510_CR19","doi-asserted-by":"crossref","unstructured":"K Monga, N Chaturved, S Gurunarayanan (2020) Design of a novel CMOS\/MTJ-based multibit SRAM cell with low store energy for IoT applications. International Journal of Electronics 107(6): 899\u201314.","DOI":"10.1080\/00207217.2019.1692245"},{"issue":"2","key":"9510_CR20","doi-asserted-by":"publisher","first-page":"025002","DOI":"10.1088\/1674-4926\/39\/2\/025002","volume":"39","author":"V Bhatnagar","year":"2018","unstructured":"Bhatnagar, V., Kumar, P., Pandey, N., & Pandey, S. (2018). A boosted negative bit-line SRAM with write assisted cell in 45nm CMOS technology. Journal of Semiconductors (IOP Science), 39(2), 025002.","journal-title":"Journal of Semiconductors (IOP Science)"},{"key":"9510_CR21","doi-asserted-by":"crossref","unstructured":"I Ullah, JS Yang, J Chung (2020) ER-TCAM: A soft-error-resilient SRAM-based ternary content-addressable memory for FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(4): 1084\u20131088.","DOI":"10.1109\/TVLSI.2020.2968365"},{"key":"9510_CR22","doi-asserted-by":"publisher","first-page":"1959","DOI":"10.1007\/s11277-020-07953-4","volume":"117","author":"H Kumar","year":"2021","unstructured":"Kumar, H., & Tomar, V. K. (2021). A review on performance evaluation of different low power SRAM cells in nano-scale era. Wireless Personal Communications, 117, 1959\u20131984.","journal-title":"Wireless Personal Communications"},{"key":"9510_CR23","doi-asserted-by":"crossref","unstructured":"F Tachibana, O Hirabayashi, Y Takeyama, M Shizuno, A Kawasumi, K Kushida, A Suzuki, Y Niki, S Sasaki, T Yabe, Y Unekawa (2014) A 27% active and 85% standby power reduction in dual power supply SRAM using BL power calculator and digitally controllably retention circuit. IEEE Journal of Solid-State Circuits 49(1): 118\u2013126.","DOI":"10.1109\/JSSC.2013.2280312"},{"key":"9510_CR24","doi-asserted-by":"crossref","unstructured":"MSM Siddiqui, ZC Lee, TTH Kim (2021). A 16-kb 9T ultralow-voltage SRAM with column-based split cell-VSS, data-aware write-assist, and enhanced read sensing margin in 28-nm FDSOI. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(10): 1707\u20131719.","DOI":"10.1109\/TVLSI.2021.3102675"},{"key":"9510_CR25","doi-asserted-by":"crossref","unstructured":"MH Sheu, CM Tsai, MY Tsai, SC Hsia, SM Morsalin, JF Lin (2021) A 0.3 V PNN based 10T SRAM with pulse control based read-assist and write data-aware schemes for low power applications. Sensors 21(19):6591.","DOI":"10.3390\/s21196591"},{"key":"9510_CR26","doi-asserted-by":"publisher","first-page":"4091","DOI":"10.1007\/s12633-020-00713-w","volume":"13","author":"H Kaur","year":"2021","unstructured":"Kaur, H., Sarin, R. K., Anand, S., et al. (2021). 6-T and 7-T SRAM cell design using doping-less charge plasma TFET. SILICON, 13, 4091\u20134100.","journal-title":"SILICON"}],"container-title":["Wireless Personal Communications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-022-09510-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11277-022-09510-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-022-09510-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,21]],"date-time":"2022-06-21T18:44:06Z","timestamp":1655837046000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11277-022-09510-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,1,17]]},"references-count":26,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2022,6]]}},"alternative-id":["9510"],"URL":"https:\/\/doi.org\/10.1007\/s11277-022-09510-7","relation":{},"ISSN":["0929-6212","1572-834X"],"issn-type":[{"value":"0929-6212","type":"print"},{"value":"1572-834X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,1,17]]},"assertion":[{"value":"6 January 2022","order":1,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"17 January 2022","order":2,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare no potential conflict of interest with respect to the research, authorship, and\/or publication of this article.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}