{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,24]],"date-time":"2026-02-24T19:21:49Z","timestamp":1771960909936,"version":"3.50.1"},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Wireless Pers Commun"],"published-print":{"date-parts":[[2023,3]]},"DOI":"10.1007\/s11277-023-10177-x","type":"journal-article","created":{"date-parts":[[2023,3,3]],"date-time":"2023-03-03T06:02:57Z","timestamp":1677823377000},"page":"1097-1111","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":9,"title":["Comprehensive Analysis of a Power-Efficient 1-Bit Hybrid Full Adder Cell"],"prefix":"10.1007","volume":"129","author":[{"given":"Ayush","family":"Kanojia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sachin","family":"Agrawal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rohit","family":"Lorenzo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2023,3,3]]},"reference":[{"key":"10177_CR1","doi-asserted-by":"crossref","unstructured":"Vijayakumar, V., Ilayarajaa, K. T., Ravi, T. et al. (2021), Analysis of High Speed Hybrid Full Adder. 2021 International Conference on Artificial Intelligence and Smart Systems (ICAIS), (pp. 1641\u20131645).","DOI":"10.1109\/ICAIS50930.2021.9395998"},{"issue":"4","key":"10177_CR2","doi-asserted-by":"publisher","first-page":"2363","DOI":"10.1016\/j.asej.2017.05.004","volume":"9","author":"V Dokania","year":"2018","unstructured":"Dokania, V., Verma, R., Guduri, M., et al. (2018). Design of 10T full adder cell for ultralow-power applications. Ain Shams Engineering Journal, 9(4), 2363\u20132372.","journal-title":"Ain Shams Engineering Journal"},{"issue":"1","key":"10177_CR3","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1142\/S0218126617500141","volume":"26","author":"MC Parameshwara","year":"2017","unstructured":"Parameshwara, M. C., & Srinivasaiah, H. C. (2017). Low-power hybrid 1-bit full adder circuit for energy efficient arithmetic applications. Journal of Circuits Systems and Computers, 26(1), 1\u201315.","journal-title":"Journal of Circuits Systems and Computers"},{"key":"10177_CR4","volume-title":"CMOS VLSI design: A circuits and systems perspective","author":"N Weste","year":"2010","unstructured":"Weste, N., & Harris, D. (2010). CMOS VLSI design: A circuits and systems perspective (4th ed.). Addison-Wesley.","edition":"4"},{"key":"10177_CR5","first-page":"348","volume":"2017","author":"P Agrawal","year":"2017","unstructured":"Agrawal, P., Raghuvanshi, D. K., & Gupta, M. K. (2017). A low-power high-speed 16T 1-bit hybrid full adder. International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), 2017, 348\u2013352.","journal-title":"International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)"},{"issue":"10","key":"10177_CR6","doi-asserted-by":"publisher","first-page":"2001","DOI":"10.1109\/TVLSI.2014.2357057","volume":"23","author":"P Bhattacharyya","year":"2015","unstructured":"Bhattacharyya, P., Kundu, B., Ghosh, S., et al. (2015). Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(10), 2001\u20132008.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"issue":"2","key":"10177_CR7","doi-asserted-by":"publisher","first-page":"165","DOI":"10.1080\/02564602.2016.1162116","volume":"34","author":"R Lorenzo","year":"2016","unstructured":"Lorenzo, R., & Chaudhury, S. (2016). Review of circuit level leakage minimization technique in VLSI circuits. IETE Technical Review Taylor and Francis, 34(2), 165\u2013187.","journal-title":"IETE Technical Review Taylor and Francis"},{"issue":"5","key":"10177_CR8","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1142\/S0218126617500840","volume":"26","author":"P Kumar","year":"2017","unstructured":"Kumar, P., & Sharma, R. K. (2017). An energy efficient logic approch to implement CMOS full adder. Journal of Circuits Systems and Computers, 26(5), 1\u201320.","journal-title":"Journal of Circuits Systems and Computers"},{"key":"10177_CR9","first-page":"1","volume":"2021","author":"D Vaithiyanathan","year":"2021","unstructured":"Vaithiyanathan, D., Sonar, S. M., Pari, J. B., et al. (2021). Performance Analysis of Full Adder Circuit using Conventional and Hybrid Techniques. IEEE Madras Section Conference (MASCON), 2021, 1\u20137.","journal-title":"IEEE Madras Section Conference (MASCON)"},{"key":"10177_CR10","doi-asserted-by":"publisher","first-page":"1762","DOI":"10.1007\/s00034-020-01550-3","volume":"40","author":"I Hussain","year":"2021","unstructured":"Hussain, I., & Chaudhury, S. (2021). Fast and high-performing 1-bit full adder circuit based on input switching activity pattern and gate diffusion input technique. Circuits System Signal Process., 40, 1762\u20131787.","journal-title":"Circuits System Signal Process."},{"key":"10177_CR11","doi-asserted-by":"crossref","unstructured":"Aguirre-Hernandez, M., & Linares-Aranda, M. (2011), CMOS Full-Adders for Energy-Efficient Arithmetic Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(4), 718\u2013721.","DOI":"10.1109\/TVLSI.2009.2038166"},{"key":"10177_CR12","doi-asserted-by":"crossref","unstructured":"Naseri, H.,& Timarchi, S. (2018), Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(8), 1481\u20131493.","DOI":"10.1109\/TVLSI.2018.2820999"},{"key":"10177_CR13","doi-asserted-by":"crossref","unstructured":"Kandpal, J., Tomar, A., Agarwal, M.et al. (2020), High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR\u2013XNOR Cell, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(6), 1413\u20131422.","DOI":"10.1109\/TVLSI.2020.2983850"},{"key":"10177_CR14","doi-asserted-by":"publisher","first-page":"644","DOI":"10.1007\/s42452-021-04640-2","volume":"3","author":"M Hassan","year":"2021","unstructured":"Hassan, M., Siddique, A. H., Mondol, A. H., et al. (2021). Comprehensive study of 1-Bit full adder cells: Review, performance comparison and scalability analysis. SN Applied Science, 3, 644.","journal-title":"SN Applied Science"},{"issue":"8","key":"10177_CR15","doi-asserted-by":"publisher","first-page":"1464","DOI":"10.1109\/TCSII.2019.2940558","volume":"67","author":"M Hasan","year":"2020","unstructured":"Hasan, M., Hossein, M. J., Hossain, M., et al. (2020). Design of a scalable low-power 1-bit hybrid full adder for fast computation. IEEE Transactions on Circuits and Systems II Express Briefs, 67(8), 1464\u20131468.","journal-title":"IEEE Transactions on Circuits and Systems II Express Briefs"},{"key":"10177_CR16","doi-asserted-by":"publisher","first-page":"49","DOI":"10.1016\/j.mejo.2018.01.018","volume":"74","author":"M Amini-Valashani","year":"2018","unstructured":"Amini-Valashani, M., Ayat, M., & Mirzakuchaki, S. (2018). Design and analysis of a novel low-power and energy-efficient 18T hybrid fulladder. Microelectronics Journal, 74, 49\u201359.","journal-title":"Microelectronics Journal"},{"key":"10177_CR17","doi-asserted-by":"publisher","first-page":"5718","DOI":"10.1007\/s00034-021-01725-6","volume":"40","author":"T Rajagopal","year":"2021","unstructured":"Rajagopal, T., & Chakrapani, A. (2021). A novel high-performance hybrid full adder for VLSI circuits. Circuits System Signal Process., 40, 5718\u20135732.","journal-title":"Circuits System Signal Process."},{"key":"10177_CR18","doi-asserted-by":"publisher","first-page":"165","DOI":"10.1007\/s10470-021-01852-9","volume":"109","author":"VJ Arulkarthick","year":"2021","unstructured":"Arulkarthick, V. J., Thiruvengadam, R., Arvind, C., et al. (2021). Area and power delay product efficient level restored hybrid full adder (LR-HFA). Analog Integrated Circuits and Signal Processing, 109, 165\u2013172.","journal-title":"Analog Integrated Circuits and Signal Processing"},{"key":"10177_CR19","doi-asserted-by":"publisher","first-page":"1364","DOI":"10.1016\/j.jestch.2020.05.008","volume":"23","author":"M Hasan","year":"2020","unstructured":"Hasan, M., Zaman, H. U., Hossain, M., et al. (2020). Gate Diffusion Input technique based full swing and scalable 1-bit hybrid Full Adder for high performance applications. Engineering Science and Technology, an International Journal, 23, 1364\u20131373.","journal-title":"Engineering Science and Technology, an International Journal"},{"key":"10177_CR20","doi-asserted-by":"publisher","first-page":"135","DOI":"10.1007\/s10470-021-01831-0","volume":"109","author":"M Taheri","year":"2021","unstructured":"Taheri, M., Shafiee, N., Sharifi, F., et al. (2021). Energy efficient hybrid full adder design for digital signal processing in nanoelectronics. Analog Integrated Circuits and Signal Processing, 109, 135\u2013151.","journal-title":"Analog Integrated Circuits and Signal Processing"},{"issue":"5","key":"10177_CR21","doi-asserted-by":"publisher","first-page":"1138","DOI":"10.1109\/TVLSI.2018.2889833","volume":"27","author":"H Basireddy","year":"2019","unstructured":"Basireddy, H., Challa, K., & Nikoubin, T. (2019). Hybrid logical effort for hybrid logic style full adders in multistage structures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(5), 1138\u20131147.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"}],"container-title":["Wireless Personal Communications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-023-10177-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11277-023-10177-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-023-10177-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,3,26]],"date-time":"2023-03-26T22:37:13Z","timestamp":1679870233000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11277-023-10177-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3]]},"references-count":21,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2023,3]]}},"alternative-id":["10177"],"URL":"https:\/\/doi.org\/10.1007\/s11277-023-10177-x","relation":{},"ISSN":["0929-6212","1572-834X"],"issn-type":[{"value":"0929-6212","type":"print"},{"value":"1572-834X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,3]]},"assertion":[{"value":"4 February 2023","order":1,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"3 March 2023","order":2,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"There is no known competing interests or personal relationships that could have appeared to influence the work reported.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Competing interest"}}]}}