{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T05:27:39Z","timestamp":1735709259999,"version":"3.32.0"},"reference-count":175,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2005,3,1]],"date-time":"2005-03-01T00:00:00Z","timestamp":1109635200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Comput Sci Technol"],"published-print":{"date-parts":[[2005,3]]},"DOI":"10.1007\/s11390-005-0147-5","type":"journal-article","created":{"date-parts":[[2005,4,19]],"date-time":"2005-04-19T08:09:59Z","timestamp":1113898199000},"page":"147-165","source":"Crossref","is-referenced-by-count":0,"title":["Design and Verification of High-Speed VLSI Physical Design"],"prefix":"10.1007","volume":"20","author":[{"given":"Dian","family":"Zhou","sequence":"first","affiliation":[]},{"given":"Rui-Ming","family":"Li","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"CR1","unstructured":"International Technology Roadmap for Semiconductors (ITRS). 2003."},{"key":"CR2","volume-title":"Circuits, Interconnections and Packaging for VLSI","author":"B H Bakoglu","year":"1990","unstructured":"Bakoglu H B. Circuits, Interconnections and Packaging for VLSI. MA: Addision-Wesley, 1990."},{"issue":"2","key":"CR3","doi-asserted-by":"crossref","first-page":"143","DOI":"10.1145\/103724.103725","volume":"23","author":"K Sahookar","year":"June 1991","unstructured":"Sahookar K, Mazumder P. VLSI cell placement techniques. ACM Computing Surveys, June 1991, 23(2): 143?220.","journal-title":"ACM Computing Surveys"},{"key":"CR4","doi-asserted-by":"crossref","unstructured":"Sherwani N. Algorithms for VLSI Physical Design Automation. second edition, Kluwer Academic Publishers, 1995.","DOI":"10.1007\/978-1-4615-2351-2"},{"key":"CR5","doi-asserted-by":"crossref","unstructured":"Kirkpatrick S, Gelatt C D, Vecchi M P. Optimization by simulated annealing. Science, May, 1983, pp.671?680.","DOI":"10.1126\/science.220.4598.671"},{"key":"CR6","unstructured":"Lam J, Delosme J. Logic minimization using simulated annealing. In Proc. the IEEE Int. Conf. Computer-Aided Design, 1986, pp.378."},{"key":"CR7","unstructured":"Otten R, Vanginnekin L. Floorplan design using simulated annealing. In Proc. the IEEE Int. Conf. Computer-Aided Design, 1984, pp.96?98."},{"key":"CR8","doi-asserted-by":"crossref","first-page":"510","DOI":"10.1109\/JSSC.1985.1052337","volume":"20","author":"C Sechen","year":"May 2003","unstructured":"Sechen C, Sangiovanni-Vincentelli A. The TimberWolf placement and routing package. IEEE Journal of Solid-State Circuits, Apr. 1985, 20: 510?522.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"CR9","doi-asserted-by":"crossref","unstructured":"Sechen C, Sangiovanni-Vincentelli A. TimberWolf3.2: A new standard cell placement and global routing package. In Proc. the 23rd Design Automation Conference, 1986, pp.432?439.","DOI":"10.1145\/318013.318083"},{"key":"CR10","doi-asserted-by":"crossref","first-page":"470","DOI":"10.1109\/TCAD.2003.809649","volume":"22","author":"C-W Sham","year":"April 2003","unstructured":"Sham C-W, Young E F Y. Routability-driven floorplanner with buffer block planning. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, April 2003, 22: 470?480.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR11","first-page":"1550","volume":"22","author":"J-G Kim","year":"Apr. 1985","unstructured":"Kim J-G, Kim Y-D. A linear programming-based algorithm for floorplanning in VLSI design. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, May 2003, 22: 1550?1556.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR12","doi-asserted-by":"crossref","first-page":"1518","DOI":"10.1109\/43.552084","volume":"15","author":"H Murata","year":"Dec. 1996","unstructured":"Murata H, Fujiyoshi K, Kajitani Y. VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. Computer-Aided Design, Dec. 1996, 15: 1518?1524.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"CR13","doi-asserted-by":"crossref","first-page":"824","DOI":"10.1109\/TVLSI.2002.808453","volume":"10","author":"S Alupoaei","year":"Dec. 2002","unstructured":"Alupoaei S, Katkoori S. Net-based force-directed macrocell placement for wirelength optimization. IEEE Trans. Very Large Scale Integration (VLSI) Systems, Dec. 2002, 10: 824?835.","journal-title":"IEEE Trans. Very Large Scale Integration (VLSI) Systems"},{"key":"CR14","unstructured":"Choi W, Bazargan K. Hierarchical global floorplacement using simulated annealing and network flow area migration. Design, Automation and Test in Europe Conference and Exhibition, 2003, pp.1104?1105."},{"key":"CR15","first-page":"356","volume":"10","author":"J M Kleinhans","year":"March 1991","unstructured":"Kleinhans J M, Sigl G, Johannes F M, Antreich K J. GORDIAN: VLSI placement by quadratic programming and slicing optimization. IEEE\/ACM Int. Conf. Computer Aided Design, March 1991, 10: 356?365.","journal-title":"IEEE\/ACM Int. Conf. Computer Aided Design"},{"key":"CR16","unstructured":"Quinn N R. The placement problem as viewed from the physics of classical mechanics. In Proc. 12th Design Automa-tion Conf., June 1975, pp.173?178."},{"key":"CR17","doi-asserted-by":"crossref","unstructured":"Eisenmann H, Johannes F M. Generic global placement and floorplanning. In Proc. Design Automation Conf., June 1998, pp.269?274.","DOI":"10.1145\/277044.277119"},{"key":"CR18","doi-asserted-by":"crossref","unstructured":"Goplen B, Sapatnekar S. Efficient thermal placement of standard cells in 3D ICs using a force directed approach Goplen. In Proc. Int. Conf. Computer Aided Design, Nov. 9?13, 2003, pp.86?89.","DOI":"10.1109\/ICCAD.2003.1257591"},{"issue":"2","key":"CR19","doi-asserted-by":"crossref","first-page":"473","DOI":"10.1109\/TCAPT.2003.815091","volume":"26","author":"J. Lee","year":"June 2003","unstructured":"Lee J. Thermal placement algorithm based on heat conduction analogy. IEEE Trans. Components and Packaging Technologies, June 2003, 26(2): 473?482.","journal-title":"IEEE Trans. Components and Packaging Technologies"},{"key":"CR20","doi-asserted-by":"crossref","unstructured":"Viswanathan N, Chu C. FastPlace: Efficient analytical placement using cell spreading, iterative local refinement and a hybrid net model. In Proc. Int. Symp. Physical Design, 2004, pp.26?33.","DOI":"10.1145\/981066.981072"},{"key":"CR21","unstructured":"Breuer M A. A class of min-cut placement algorithms. In Proc. Design Automation Conf, 1977, pp.284?290."},{"issue":"1","key":"CR22","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1109\/TCAD.1985.1270101","volume":"CAD-4","author":"A E Dunlop","year":"January 1985","unstructured":"Dunlop A E, Kernighan B W. A procedure for placement of standard-cell VLSI circuits. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, January 1985, CAD-4(1): 92?98.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"2","key":"CR23","doi-asserted-by":"crossref","first-page":"291","DOI":"10.1002\/j.1538-7305.1970.tb01770.x","volume":"49","author":"B W Kernighan","year":"1970","unstructured":"Kernighan B W, Lin S. An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J. 1970, 49(2): 291?308.","journal-title":"Bell Syst. Tech. J."},{"key":"CR24","doi-asserted-by":"crossref","unstructured":"Fiduccia C M, Mattheyses R M. A linear-time heuristic for improving network partitions. In Proc. the 19th Design Automation Conf., 1982, pp.175?181.","DOI":"10.1109\/DAC.1982.1585498"},{"key":"CR25","doi-asserted-by":"crossref","unstructured":"Alpert C J, Huang J-H, Kahng A B. Multilevel circuit partitioning. In Proc. Design Automation Conf., 1997, pp.530?533.","DOI":"10.1109\/DAC.1997.597204"},{"key":"CR26","doi-asserted-by":"crossref","unstructured":"Karypis G, Aggarwal R, Kumar V, Shekhar S. A Multilevel hypergraph partitioning: Applications in VLSI design. In Proc. Design Automation Conf., 1997, pp.526?529.","DOI":"10.1109\/DAC.1997.597203"},{"key":"CR27","doi-asserted-by":"crossref","unstructured":"Caldwell A E, Kahng A B, Markov I L. Can mrecursive bisection alone produce routable placements? In Proc. Design Automation Conf., 2000, pp.526?529.","DOI":"10.1145\/337292.337549"},{"key":"CR28","doi-asserted-by":"crossref","unstructured":"Yildiz M C, Madden P H. Improved cut sequences for partitioning based placement. In Proc. Design Automation Conf., 2001, pp.776?779.","DOI":"10.1145\/378239.379064"},{"key":"CR29","doi-asserted-by":"crossref","unstructured":"Agnihotri A et al. Fractional cut: Improved recursive bisection placement. In Proc. Int. Conf. Computer Aided Design, 2003, pp.307?310.","DOI":"10.1109\/ICCAD.2003.1257685"},{"key":"CR30","doi-asserted-by":"crossref","unstructured":"Caldwell A E, Kahng A B, Markov I L. Improved algorithms for hypergraph bipartitioning. In Proc. Asia South Pacific Design Automation Conf., 2000, pp.661?666.","DOI":"10.1145\/368434.368864"},{"key":"CR31","unstructured":"Wang M, Yang X, Sarrafzadeh M. Dragon2000: Standard-cell placement tool for large industry circuits. In Proc. Int. Conf. Computer Aided Design, November 2000, pp.260?263."},{"key":"CR32","doi-asserted-by":"crossref","unstructured":"Brandt A. Multi-level adaptive technique (MLAT) for fast numerical solution to boundary value problems. In Proc. 3rd Int. Conf. Numerical Methods in Fluid Mechanics, Vol. 1, Cabannes, Temam R (eds.), Lecture Notes in Physics 18, Springer, Berlin, pp.82?89.","DOI":"10.1007\/BFb0118663"},{"key":"CR33","doi-asserted-by":"crossref","unstructured":"Brandt A. Multi-level adaptive solutions to boundary value problems. Math. Comput., 31: 333?390.","DOI":"10.1090\/S0025-5718-1977-0431719-X"},{"key":"CR34","volume-title":"A Multigrid Tutorial","author":"L W Briggs","year":"1987","unstructured":"Briggs W L. A Multigrid Tutorial. SIAM Books, Philadelphia, 1987."},{"key":"CR35","unstructured":"Trottenberg U, Osterlee C W, Schler A. Multigrid."},{"key":"CR36","unstructured":"Hong X, Yu H, Qiao C, Cai Y. CASH: A novel quadratic placement algorithm for very large standard cell layout design based on clustering. In Proc. 5th Int. Conf. Solid-State and Integrated Circuit Technology, 1998, pp.496?501."},{"key":"CR37","doi-asserted-by":"crossref","unstructured":"Chan T F, Cong J, Kong T, Shinnerl J R. Multilevel optimization for large-scale circuit placement. In Proc. Int. Conf. Computer Aided Design, Nov., 2000, pp.171?176.","DOI":"10.1109\/ICCAD.2000.896469"},{"key":"CR38","doi-asserted-by":"crossref","unstructured":"Chang T F, Cong J, Kong T, Shinnel J R, Sze K. An enhanced multilevel algorithm for circuit placement. In Proc. Int. Conf. Computer Aided Design, Nov., 2003, pp.299?306.","DOI":"10.1109\/ICCAD.2003.159704"},{"key":"CR39","doi-asserted-by":"crossref","unstructured":"Chen H, Cheng C-K, Chou N-C, Kahng A B. An algebraic multigrid solver for analytical placement with layout based clustering. In Proc. Design Automation Conf., June 2003, pp.794?799.","DOI":"10.1145\/775832.776034"},{"key":"CR40","doi-asserted-by":"crossref","unstructured":"Cong J, Yuan X. Multilevel global placement with retiming. In Proc. Design Automation Conf., pp.208?213.","DOI":"10.1145\/775832.775887"},{"key":"CR41","doi-asserted-by":"crossref","first-page":"395","DOI":"10.1109\/TCAD.2003.809661","volume":"22","author":"C C Chang","year":"April 2003","unstructured":"Chang C C, Cong J, Pan Z, Yuan X. Multilevel global placement with congestion control. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, April 2003, 22: 395?409.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR42","doi-asserted-by":"crossref","unstructured":"Lee H-C, Chang Y-W, Hsu J-M, Yang H H. Multilevel floorplanning\/placement for large-scale modules using b*-trees. In Proc. Design Automation Conference, June 2003, pp.812?817.","DOI":"10.1145\/775832.776037"},{"key":"CR43","doi-asserted-by":"crossref","unstructured":"Yang X, Choi B-K, Sarrafzadeh M. Routability driven white space allocation for fixed-die standard-cell placement. ACM Int. Symp. Physical Design, April 2002, pp.42?47.","DOI":"10.1145\/505388.505400"},{"key":"CR44","doi-asserted-by":"crossref","unstructured":"Cong J, Kong T, Pan D Z. Buffer block planning for interconnectdriven floorplanning. In Proc. Int. Conf. Computer-Aided Design, 1999, pp.358?363.","DOI":"10.1109\/ICCAD.1999.810675"},{"key":"CR45","doi-asserted-by":"crossref","unstructured":"Alpert C J, Hu J, Sapatnekar S, Villarubia P G. A practical methodology for early buffer and wire resource allocation. In Proc. Design Automation Conf., 2001, pp.189?194.","DOI":"10.1145\/378239.378461"},{"key":"CR46","doi-asserted-by":"crossref","unstructured":"Nakatake S, Sakanushi K, Kajitani Y, Kawatika M. The channeled BSG: A universal floorplanner for simultaneous place\/route with IC applications. In Proc. IEEE Int. Conf. Computer-Aided Design, 1998, pp.418?425.","DOI":"10.1145\/288548.289064"},{"key":"CR47","unstructured":"Chen H, Zhou H, Young F Y, Wong D F, Yang Y, Sherwani N. Integrated floorplanning and interconnect planning. In Proc. IEEE Int. Conf. Computer-Aided Design, 1999, pp.354?357."},{"issue":"4","key":"CR48","doi-asserted-by":"crossref","first-page":"467","DOI":"10.1109\/5.920579","volume":"89","author":"D Sylvester","year":"2001","unstructured":"Sylvester D, Keutzer K. Impact of small process geometries on microarchitectures in systems on a chip. In Proc. IEEE, 2001, 89(4): 467?489.","journal-title":"Proc. IEEE"},{"key":"CR49","doi-asserted-by":"crossref","first-page":"607","DOI":"10.1109\/82.673643","volume":"45","author":"V Adler","year":"May 1998","unstructured":"Adler V, Friedman E G. Repeater design to reduce delay and power in resistive interconnect. IEEE Trans. Circuits Syst. I, May 1998, 45: 607?616.","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"CR50","doi-asserted-by":"crossref","first-page":"903","DOI":"10.1109\/T-ED.1985.22046","volume":"ED-32","author":"H B Bakoglu","year":"May 1985","unstructured":"Bakoglu H B, Meindl J D. Optimal interconnection circuits for VLSI. IEEE Trans. Electron Devices, May 1985, ED-32: 903?909.","journal-title":"IEEE Trans. Electron Devices"},{"key":"CR51","doi-asserted-by":"crossref","unstructured":"Alpert C, Devgan A. Wire segmenting for improved buffer insertion. In Proc. ACM\/IEEE DAC, 1997, pp.588?593.","DOI":"10.1145\/266021.266291"},{"issue":"3","key":"CR52","doi-asserted-by":"crossref","first-page":"343","DOI":"10.1145\/383251.383256","volume":"6","author":"C Chu","year":"July 2001","unstructured":"Chu C, Wong D F. Closed form solution to simultaneous buffer insertion\/sizing and wire sizing. ACM Trans. Design Automation of Electronic Systems, July 2001, 6(3): 343?371.","journal-title":"ACM Trans. Design Automation of Electronic Systems"},{"key":"CR53","doi-asserted-by":"crossref","unstructured":"Cong J, Leung K. Optimal wire sizing under the distributed Elmore delay model. In Proc. IEEE ICCAD, 1993, pp.634?639.","DOI":"10.1109\/ICCAD.1993.580152"},{"key":"CR54","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1109\/4.65707","volume":"26","author":"S Dhar","year":"Jan. 1991","unstructured":"Dhar S, Franklin M A. Optimum buffer circuits for driving long uniform lines. IEEE J. Solid-State Circuits, Jan. 1991, 26: 32?40.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"CR55","unstructured":"Nekili M, Savaria Y. Parallel regeneration of interconnections in VLSI & ULSI circuits. In Proc. IEEE Int. Symp. Circuits and Systems, May 1993."},{"key":"CR56","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1016\/S0167-9260(96)00008-9","volume":"21","author":"J Cong","year":"1996","unstructured":"Cong J, He L, Koh C-K, Madden P H. Performance optimization of VLSI interconnect layout. Integration VLSI J., 1996, 21: 1?94.","journal-title":"Integration VLSI J."},{"key":"CR57","doi-asserted-by":"crossref","unstructured":"Cong J, He L, Khoo K-Y, Koh C-K, Pan D Z. Interconnect design for deep submicron ICs. In Proc. Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 1997, pp.478?485.","DOI":"10.1109\/ICCAD.1997.643579"},{"key":"CR58","doi-asserted-by":"crossref","unstructured":"Zhou D, Preparata F P, Kang S M. Interconnection delay in very high-speed VLSI. IEEE Trans. Circuits and Systems, July 1991, 38(7).","DOI":"10.1109\/31.135749"},{"key":"CR59","doi-asserted-by":"crossref","unstructured":"Davis J A, Meindl J D. Compact distributed RLC interconnect models?Part I: Single line transient, time delay, and overshoot expressions. IEEE Trans. Electron. Devices, 47(11): 2068?2077.","DOI":"10.1109\/16.877168"},{"key":"CR60","doi-asserted-by":"crossref","unstructured":"Davis J A, Meindl J D. Compact distributed RLC interconnect models?Part II: Coupled line expressions, and peak crosstalk in multilevel networks. IEEE Trans. Electron. Devices, 47(11): 2078?2087.","DOI":"10.1109\/16.877169"},{"key":"CR61","doi-asserted-by":"crossref","unstructured":"Venkatesan R, Davis J A, Meindl J D. Compact distributed RLC interconnect models?Part III: Transients in single and coupled lines with capacitive load termination. IEEE Trans. Electron. Devices, 50(4): 1081?1093.","DOI":"10.1109\/TED.2003.812507"},{"key":"CR62","doi-asserted-by":"crossref","unstructured":"Venkatesan R, Davis J A, Meindl J D. Compact distributed RLC interconnect models?Part IV: Unified models for time delay, crosstalk, and repeater insertion. IEEE Trans. Electron. Devices, 50(4): 1094?1102.","DOI":"10.1109\/TED.2003.812509"},{"key":"CR63","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1063\/1.1697872","volume":"19","author":"C W Elmore","year":"1948","unstructured":"Elmore W C. The transient response of damped linear network with particular regard to wideband amplifiers. J. Appl. Phys., 1948, 19: 55?63.","journal-title":"J. Appl. Phys."},{"key":"CR64","doi-asserted-by":"crossref","first-page":"19","DOI":"10.1007\/BF01673903","volume":"5","author":"D Zhou","year":"Jan. 1994","unstructured":"Zhou D, Su S, Tsui F, Gao D S, Cong J S. A simplified synthesis of transmission lines with a tree structure. Int. J. Analog Integrated Circuits Signal Process, Jan. 1994, 5: 19?30.","journal-title":"Int. J. Analog Integrated Circuits Signal Process"},{"key":"CR65","doi-asserted-by":"crossref","first-page":"1507","DOI":"10.1109\/43.664231","volume":"16","author":"A B Kahng","year":"Dec. 1997","unstructured":"Kahng A B, Muddu S. An analytical delay model for RLC interconnects. IEEE Trans. Computer-Aided Design, Dec. 1997, 16: 1507?1514.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"CR66","doi-asserted-by":"crossref","unstructured":"Tutuianu B, Dartu F, Pileggi L. Explicit RC-circuit delay approximation based on the first three moments of the impulse response. IEEE\/ACM Design Automation Conf., June 1996, pp.611?616.","DOI":"10.1145\/240518.240634"},{"key":"CR67","doi-asserted-by":"crossref","first-page":"352","DOI":"10.1109\/43.45867","volume":"9","author":"L T Pillage","year":"Apr. 1990","unstructured":"Pillage L T, Rohrer R A. Asymptotic waveform evaluation fortiming analysis. IEEE Trans. Computer-Aided Design, Apr. 1990, 9: 352?366.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"CR68","doi-asserted-by":"crossref","first-page":"639","DOI":"10.1109\/43.384428","volume":"14","author":"P Feldmann","year":"May 1995","unstructured":"Feldmann P, Freund R W. Efficient linear circuit analysis by Pad approximation via the Lanczos process. IEEE Trans. Computer-Aided Design, May 1995, 14: 639?649.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"CR69","doi-asserted-by":"crossref","unstructured":"Feldmann P, Freund R W. Reduced-order modeling of large linear subcircuits via block Lanczos algorithm. In Proc. IEEE\/ACM Design Automation Conf., June 1995, pp.474-479.","DOI":"10.1145\/217474.217573"},{"key":"CR70","doi-asserted-by":"crossref","unstructured":"Silveira M, Kamon M, White J. Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures. In Proc. IEEE\/ACM Design Automation Conf., June 1995, pp.376?380.","DOI":"10.1145\/217474.217558"},{"issue":"6","key":"CR71","doi-asserted-by":"crossref","first-page":"733","DOI":"10.1007\/BF02523124","volume":"13","author":"L D Boley","year":"May 1994","unstructured":"Boley D L. Krylov space methods on state-space control models. J. Circuits, Syst., Signal Processing, May 1994, 13(6): 733?758.","journal-title":"J. Circuits, Syst., Signal Processing"},{"key":"CR72","doi-asserted-by":"crossref","first-page":"645","DOI":"10.1109\/43.712097","volume":"17","author":"A Odabasioglu","year":"Aug. 1998","unstructured":"Odabasioglu A, Celik M, Pillage L T. PRIMA: Passive reduced-order interconnect macromodeling algorithm. IEEE Trans. Computer-Aided Design, Aug. 1998, 17: 645?654.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"CR73","doi-asserted-by":"crossref","unstructured":"Feldmann P, Freund R W. Reduced-order modeling of large passive linear circuits by means of the SyPVL algorithm. In Proc. IEEE\/ACM Int. Conf. Computer-Aided Design, Nov. 1996, pp.280?287.","DOI":"10.1109\/ICCAD.1996.569707"},{"issue":"1","key":"CR74","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1109\/43.822622","volume":"19","author":"Y I Ismail","year":"Jan. 2000","unstructured":"Ismail Y I, Friedman E G, Neves J L. Equivalent Elmore delay for RLC trees. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Jan. 2000, 19(1): 83?97.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR75","doi-asserted-by":"crossref","unstructured":"Cong J, Leung K S, Zhou D. Performance-driven interconnect design based on distributed RC delay model. In Proc. Design Automation Conf., June 1993, pp.606?611.","DOI":"10.1145\/157485.165065"},{"issue":"12","key":"CR76","doi-asserted-by":"crossref","first-page":"1020","DOI":"10.1109\/81.481198","volume":"42","author":"J P Fishburn","year":"Dec. 1995","unstructured":"Fishburn J P, Schevon C A. Shaping a distributed-RC line to minimize Elmore delay. IEEE Trans. Circuits Syst. I: Fund. Theory Applicat., Dec. 1995, 42(12): 1020?1022.","journal-title":"IEEE Trans. Circuits Syst. I: Fund. Theory Applicat."},{"key":"CR77","doi-asserted-by":"crossref","unstructured":"Chen C P, Chen Y P, Wong D F. Optimal wire-sizing formula under the Elmore delay model. In Proc. Design Automation Conf., June, 1996, pp.487?490.","DOI":"10.1145\/240518.240611"},{"key":"CR78","doi-asserted-by":"crossref","unstructured":"Chen C-P, Wong D F. Optimal wire sizing function with fringing capacitance consideration. In Proc. Design Automation Conf., June, 1997, pp.604?607.","DOI":"10.1109\/DAC.1997.597217"},{"key":"CR79","doi-asserted-by":"crossref","unstructured":"Fishburn J P. Shaping a VLSI wire to minimize Elmore delay. In Proc. European Design and Test Conf., Mar. 1997.","DOI":"10.1109\/EDTC.1997.582366"},{"key":"CR80","doi-asserted-by":"crossref","unstructured":"Gao Y, Wong D F. Optimal shape function for a bi-directional wire under Elmore delay model. In Proc. Int. Conf. Computer Aided Design, Nov. 1997, pp.622?627.","DOI":"10.1109\/ICCAD.1997.643603"},{"key":"CR81","first-page":"412","volume":"4","author":"C-P Chen","year":"1996","unstructured":"Chen C-P, Wong D F. A fast algorithm for optimal wire-sizing under Elmore delay model. In Proc. IEEE ISCAS, 1996, 4: 412?415.","journal-title":"Proc. IEEE ISCAS"},{"key":"CR82","doi-asserted-by":"crossref","first-page":"398","DOI":"10.1109\/43.752924","volume":"18","author":"C Chu","year":"Apr. 1999","unstructured":"Chu C, Wong D F. Greedy wire-sizing is linear time. IEEE Trans. Computer-Aided Design, Apr. 1999, 18: 398?405.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"CR83","doi-asserted-by":"crossref","unstructured":"Fishburn J P. Shaping a VLSI wire to minimize Elmore delay. European Design and Design and Test Conf., 1997.","DOI":"10.1109\/EDTC.1997.582366"},{"key":"CR84","doi-asserted-by":"crossref","unstructured":"Chen C-P, Zhou H, Wong D F. Optimal nonuniform wire-sizing under the Elmore delay model. IEEE Int. Conf. Computer-Aided Design, 1996, pp.192?197.","DOI":"10.1145\/240518.240611"},{"issue":"4","key":"CR85","doi-asserted-by":"crossref","first-page":"478","DOI":"10.1145\/238997.239018","volume":"1","author":"J Cong","year":"Oct. 1996","unstructured":"Cong J, He L. Optimal wiresizing for interconnects with multiple sources. ACM Trans. Design Automation Electron. Syst., Oct. 1996, 1(4): 478?511.","journal-title":"ACM Trans. Design Automation Electron. Syst."},{"key":"CR86","doi-asserted-by":"crossref","unstructured":"Menezes N, Pullela S, Dartu F, Pillage L T. RC interconnect synthesis?A moment fitting approach. In Proc. Int. Conf. Computer-Aided Design, Nov. 1994, pp.418?425.","DOI":"10.1109\/ICCAD.1994.629837"},{"key":"CR87","doi-asserted-by":"crossref","unstructured":"Pileggi L. Coping with RC(L) interconnect design headaches. In Proc. Int. Conf. Computer-Aided Design, Nov. 1995, pp.246?253.","DOI":"10.1109\/ICCAD.1995.480019"},{"key":"CR88","doi-asserted-by":"crossref","unstructured":"Cong J, He L, Koh C-K, Pan Z. Global interconnect sizing and spacing with consideration of coupling capacitance. In Proc. Int. Conf. Computer-Aided Design, Nov. 1997, pp.628?633.","DOI":"10.1109\/ICCAD.1997.643604"},{"key":"CR89","doi-asserted-by":"crossref","first-page":"319","DOI":"10.1109\/43.986425","volume":"21","author":"J Cong","year":"March 2002","unstructured":"Cong J, Pan Z. Wire width planning for interconnect performance optimization. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, March 2002, 21: 319?329.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR90","doi-asserted-by":"crossref","first-page":"28","DOI":"10.1109\/TVLSI.2003.820529","volume":"12","author":"T-C Chen","year":"Jan. 2004","unstructured":"Chen T-C, Pan S-R, Chang Y-W. Timing modeling and optimization under the transmission line model. IEEE Trans. Very Large Scale Integration (VLSI) Systems, Jan. 2004, 12: 28?41.","journal-title":"IEEE Trans. Very Large Scale Integration (VLSI) Systems"},{"key":"CR91","doi-asserted-by":"crossref","first-page":"270","DOI":"10.1109\/TCAD.1987.1270271","volume":"CAD-6","author":"N Hedenstierna","year":"Mar. 1987","unstructured":"Hedenstierna N, Jeppson K O. CMOS circuit speed and buffer optimization. IEEE Trans. Computer-Aided Design, Mar., 1987, CAD-6: 270?281.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"CR92","doi-asserted-by":"crossref","first-page":"185","DOI":"10.1109\/JSSC.1975.1050587","volume":"SC-10","author":"C R Jaeger","year":"June 1975","unstructured":"Jaeger R C. Comments on ?An optimized output stage for MOS integrated circuits?. IEEE J. Solid-State Circuits, June, 1975, SC-10: 185?186.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"CR93","first-page":"106","volume":"SC-10","author":"H C Lin","year":"April 1975","unstructured":"Lin H C, Linholm L W. An optimized output stage for MOS integrated circuits. IEEE J. Solid-State Circuits, April, 1975, SC-10: 106?109.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"CR94","doi-asserted-by":"crossref","unstructured":"van Ginneken L P P P. Buffer placement in distributed RC-tree network for minimal Elmore delay. ISCAS 1990, pp.865?868.","DOI":"10.1109\/ISCAS.1990.112223"},{"key":"CR95","doi-asserted-by":"crossref","unstructured":"Shi W, Li Z. An O(nlog n) time algorithm for optimal buffer insertion. DAC 2003, pp.580?585.","DOI":"10.1145\/775832.775980"},{"key":"CR96","doi-asserted-by":"crossref","unstructured":"Lillis J, Cheng C-K, Lin T. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE\/ACM ICCAD, 1995, pp.138?143.","DOI":"10.1109\/ICCAD.1995.480004"},{"key":"CR97","doi-asserted-by":"crossref","unstructured":"Lillis J, Cheng C-K, Lin T Y, Ho C. New performance driven routing techniques with explicit area\/delay tradeoff and simultaneous wire sizing. Design Automation Conference Proceedings, 1996, pp.395?400.","DOI":"10.1145\/240518.240594"},{"key":"CR98","doi-asserted-by":"crossref","unstructured":"Kamoto T, Cong J. Buffered Steiner tree construction with wire sizing for interconnect layout optimization. IEEE\/ACM Int. Conf. Computer-Aided Design, 1996, pp.44?49.","DOI":"10.1109\/ICCAD.1996.568938"},{"key":"CR99","doi-asserted-by":"crossref","unstructured":"Kang M, Dai W W-M, Dillinger T, LaPotin D. Delay bounded buffered tree construction for timing driven floorplanning. ICCAD 1997, pp.707?712.","DOI":"10.1109\/ICCAD.1997.643616"},{"issue":"7","key":"CR100","doi-asserted-by":"crossref","first-page":"819","DOI":"10.1109\/43.851998","volume":"19","author":"H Zhou","year":"2000","unstructured":"Zhou H, Wong D F, Liu I M, Aziz A. Simultaneous routing and buffer insertion with restrictions on buffer locations. IEEE Trans. CAD, 2000, 19(7): 819?824.","journal-title":"IEEE Trans. CAD"},{"key":"CR101","doi-asserted-by":"crossref","unstructured":"Chu C C N, Wong D F. A polynomial time optimal algorithm for simultaneous buffer and wire sizing. In Proc. Conf. Design Automation and Test in Europe, 1998, pp.479?485.","DOI":"10.1109\/DATE.1998.655901"},{"key":"CR102","doi-asserted-by":"crossref","unstructured":"Cong J, Koh C-K, Leung K-S. Simultaneous buffer and wire sizing for performance and power optimization. In Proc. Int. Symp. Low-Power Electronics and Design, Aug. 1996, pp.271?276.","DOI":"10.1109\/LPE.1996.547521"},{"issue":"5","key":"CR103","doi-asserted-by":"crossref","first-page":"680","DOI":"10.1109\/43.920705","volume":"20","author":"Y Mo","year":"May 2001","unstructured":"Mo Y, Chu C. Hybrid dynamic\/quadratic programming algorithm for interconnect tree optimization. IEEE Trans. Computer-Aided Design, May 2001, 20(5): 680?686.","journal-title":"IEEE Trans. Computer-Aided Design"},{"issue":"6","key":"CR104","doi-asserted-by":"crossref","first-page":"787","DOI":"10.1109\/43.766728","volume":"18","author":"C Chu","year":"1999","unstructured":"Chu C, Wong D F. A quadratic programming approach to simultaneous buffer insertion\/sizing and wire sizing. IEEE Trans. Computer-Aided Design, 1999, 18(6): 787?798.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"CR105","doi-asserted-by":"crossref","unstructured":"Menezes N, Baldick R, Pileggi L T. A sequential quadratic programming approach to concurrent gate and wire sizing. In Proc. IEEE Int. Conf. Computer-Aided Design, 1995, pp.144?151.","DOI":"10.1109\/ICCAD.1995.480005"},{"key":"CR106","doi-asserted-by":"crossref","first-page":"437","DOI":"10.1109\/4.494206","volume":"31","author":"J Lillis","year":"Mar. 1996","unstructured":"Lillis J, Cheng C-K, Lin T-T. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid State Circuits, Mar., 1996, 31: 437?447.","journal-title":"IEEE J. Solid State Circuits"},{"key":"CR107","doi-asserted-by":"crossref","unstructured":"Banerjee K, Mehrotra A. A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Transaction on Electron Devices, Nov., 2002, 49(11).","DOI":"10.1109\/TED.2002.804706"},{"key":"CR108","doi-asserted-by":"crossref","unstructured":"Turgis S, Azemard N, Auvergne D. Design and selection of buffers for minimum power-delay product. In Proc. European Design and Test Conference, 1996, pp.224?228.","DOI":"10.1109\/EDTC.1996.494153"},{"key":"CR109","doi-asserted-by":"crossref","unstructured":"Zhou D, Liu X. Minimization of chip size and power consumption of high-speed VLSI buffers. In Proc. Int. Symp. Physical Design, 1997, pp.186?191.","DOI":"10.1145\/267665.267711"},{"key":"CR110","doi-asserted-by":"crossref","unstructured":"Nalamalpu A, Burleson W. A practical approach to DSM repeater insertion: Satisfying delay constraints while minimizing area and power. In Proc. 14th Annu. IEEE Int. ASIC\/SOC Conf., 2001, pp.152?156.","DOI":"10.1109\/ASIC.2001.954689"},{"key":"CR111","unstructured":"Li R, Zhou D, Liu J, Zeng X. Power-Optimal Simultaneous Buffer Insertion\/Sizing and Wire Sizing. In Proc. International Conference on CAD, Nov. 2003."},{"issue":"4","key":"CR112","doi-asserted-by":"crossref","first-page":"352","DOI":"10.1109\/43.45867","volume":"9","author":"L T Pillage","year":"Appil 1990","unstructured":"Pillage L T, Rohrer R A. ?Asymptotic waveform evaluation for timing analysis. IEEE Trans. CAD, Appil, 1990, 9(4): 352?366.","journal-title":"IEEE Trans. CAD"},{"key":"CR113","doi-asserted-by":"crossref","unstructured":"Zhou D, Chen N, Cai W. A fast wavelet collocation method for high-speed circuit simulation. In Proc. IEEE\/ACM ICCAD, 1995, pp.115?122.","DOI":"10.1109\/ICCAD.1995.480001"},{"key":"CR114","doi-asserted-by":"crossref","unstructured":"Zhou D, Cai W. A fast wavelet collocation method for high-speed circuit simulation. IEEE Trans. CAS-I, 1999, pp.920?930.","DOI":"10.1109\/81.780373"},{"key":"CR115","doi-asserted-by":"crossref","unstructured":"Zhou D, Cai W, Zhang W. An adaptive wavelet method for nonlinear circuit simulation. IEEE Trans. CAS-I, 1999, pp.931?938.","DOI":"10.1109\/81.780374"},{"key":"CR116","doi-asserted-by":"crossref","unstructured":"Rabiei P, Pedram M. Model order reduction of large circuits using balanced truncation. In Proc. ASP-DAC, 1999, pp.237?240.","DOI":"10.1109\/ASPDAC.1999.760004"},{"issue":"6","key":"CR117","doi-asserted-by":"crossref","first-page":"1115","DOI":"10.1080\/00207178408933239","volume":"39","author":"K Glover","year":"1984","unstructured":"Glover K. All optimal Hankel-norm approximations of linear multivariable systems and their L error bounds. Int. J. Control, 1984, 39(6): 1115?1193.","journal-title":"Int. J. Control"},{"key":"CR118","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-3116-6","volume-title":"Asymptotic waveform evaluation and moment matching for interconnect analysis","author":"E Chiprout","year":"1994","unstructured":"Chiprout E, Nakhla M S. Asymptotic waveform evaluation and moment matching for interconnect analysis. Kluwer Academic, Norwell, MA, 1994."},{"issue":"2","key":"CR119","doi-asserted-by":"crossref","first-page":"186","DOI":"10.1109\/43.370425","volume":"14","author":"E Chiprout","year":"1995","unstructured":"Chiprout E, Nakhla M S. Analysis of interconnect networks using complex frequency hopping (CFH). IEEE Trans. CAD Integrated Circuits and Systems, 1995, 14(2): 186?200.","journal-title":"IEEE Trans. CAD Integrated Circuits and Systems"},{"key":"CR120","doi-asserted-by":"crossref","unstructured":"Ismail Y I. Efficient model order reduction via multi-node moment matching. IEEE\/ACM International Conference on Computer-Aided Design, Nov. 2002, pp.767?774.","DOI":"10.1145\/774572.774685"},{"key":"CR121","doi-asserted-by":"crossref","first-page":"900","DOI":"10.1109\/TVLSI.2003.817138","volume":"11","author":"I Y Ismail","year":"Oct. 2003","unstructured":"Ismail Y I. Improved model-order reduction by using spacial information in moments. IEEE Trans. Very Large Scale Integration (VLSI) Systems, Oct. 2003, 11: 900?908.","journal-title":"IEEE Trans. Very Large Scale Integration (VLSI) Systems"},{"key":"CR122","doi-asserted-by":"crossref","first-page":"133","DOI":"10.1109\/43.743719","volume":"18","author":"Z Bai","year":"Feb. 1999","unstructured":"Bai Z, Slone R D, Smith W T, Qiang Y. Error bound for reduced system model by Pade approximation via the Lanczos process. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Feb. 1999, 18: 133?141.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR123","doi-asserted-by":"crossref","first-page":"673","DOI":"10.1109\/20.996175","volume":"38","author":"T Wittig","year":"March 2002","unstructured":"Wittig T, Munteanu I, Schuhmann R, Weiland T. Two-step Lanczos algorithm for model order reduction. IEEE Trans. Magnetics, March 2002, 38: 673?676.","journal-title":"IEEE Trans. Magnetics"},{"key":"CR124","unstructured":"Silveira M, Kamon M, Elfadel I, White J. A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits. IEEE\/ACM Int. Conf. Computer-Aided Design, Nov. 1996, pp.288?294."},{"issue":"1-2","key":"CR125","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1007\/BF02141739","volume":"12","author":"E J Grimme","year":"1996","unstructured":"Grimme E J, Sorensen D C, Van Dooren P. Model reduction of state space systems via an implicitly restarted Lanczos method. Numer. Algorithms, 1996, 12(1-2): 1?31.","journal-title":"Numer. Algorithms"},{"key":"CR126","doi-asserted-by":"crossref","unstructured":"Odabasioglu A, Celik M, Pileggi L. PRIMA: Passive reduced-order interconnect macromodeling algorithm, ?i. In Proc. IEEE\/ACM Int. Conf. Computer-Aided Design, 1997, pp.58?65.","DOI":"10.1109\/ICCAD.1997.643366"},{"key":"CR127","doi-asserted-by":"crossref","unstructured":"Liu Y, Pileggi L T, Strojwas A J. Model order-reduction of RC(L) interconnect including variational analysis. Design Automation Conference, June 1999, pp.201?206.","DOI":"10.1145\/309847.309914"},{"key":"CR128","doi-asserted-by":"crossref","first-page":"1563","DOI":"10.1109\/TCSI.2002.804542","volume":"49","author":"J M Wang","year":"Nov. 2002","unstructured":"Wang J M, Chia-Chi Chu, Qingjian Yu, Kuh E S. On projection-based algorithms for model-order reduction of interconnects. IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications, Nov. 2002, 49: 1563?1585.","journal-title":"IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications"},{"key":"CR129","doi-asserted-by":"crossref","unstructured":"Zhou D, Li W, Cai W, Guo N. An efficient balanced truncation realization algorithm for interconnect model order reduction. IEEE International Symposium on Circuits and Systems, May 2001, pp.383?386.","DOI":"10.1109\/ISCAS.2001.922065"},{"key":"CR130","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1016\/S0167-9317(01)00576-7","volume":"60","author":"X Zeng","year":"January 2002","unstructured":"Zeng X, Zhou D, Cai W. An efficient DC-gain matched balanced truncation realization for VLSI interconnect circuit order reduction. Microelectronic Engineering, January 2002, 60: 3?15.","journal-title":"Microelectronic Engineering"},{"key":"CR131","doi-asserted-by":"crossref","first-page":"1027","DOI":"10.1109\/TCAD.2003.814949","volume":"22","author":"J R Philips","year":"Aug. 2003","unstructured":"Philips J R, Daniel L, Silveira L M. Guaranteed passive balancing transformations for model order reduction. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Aug. 2003, 22: 1027?1041.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR132","doi-asserted-by":"crossref","unstructured":"Mei S, Amin C, Ismail Y I. Efficient model order reduction including skin effect. Design Automation Conference, June, 2003, pp.232?237.","DOI":"10.1145\/775832.775892"},{"key":"CR133","doi-asserted-by":"crossref","first-page":"739","DOI":"10.1109\/TCAD.2002.1004318","volume":"21","author":"Y Shin","year":"June 2002","unstructured":"Shin Y, Sakurai T. Power distribution analysis of VLSI interconnects using model order reduction. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, June 2002, 21: 739?745.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR134","doi-asserted-by":"crossref","first-page":"155","DOI":"10.1109\/TCAD.2002.806601","volume":"22","author":"M Rewienski","year":"Feb. 2003","unstructured":"Rewienski M, White J. A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Feb. 2003, 22: 155?170.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR135","doi-asserted-by":"crossref","unstructured":"Dong N, Roychowdhury J. Piecewise polynomial nonlinear model reduction. In 40th ACM\/IEEE Design Automation Conference, Anaheim, CA, June 2003, pp.484?489.","DOI":"10.1145\/775832.775957"},{"key":"CR136","unstructured":"Chen Y. Model order reduction for nonlinear systems [Thesis]. Massachusetts Institute of Technology, September 1999."},{"key":"CR137","doi-asserted-by":"crossref","unstructured":"Phillips J R. Projection frameworks for model reduction of weakly nonlinear systems. Design Automation Conference, June, 2000.","DOI":"10.1145\/337292.337380"},{"key":"CR138","doi-asserted-by":"crossref","unstructured":"Phillips J R. Automated extraction of nonlinear circuit macromodels. IEEE Custom Integrated Circuits Conference, 2000.","DOI":"10.1109\/CICC.2000.852706"},{"key":"CR139","doi-asserted-by":"crossref","unstructured":"Roychowdhury J. Reduced-order modeling of time-varying system. IEEE Trans. CAS Part II, Oct., 1999, 46(10).","DOI":"10.1109\/82.799678"},{"key":"CR140","doi-asserted-by":"crossref","first-page":"1316","DOI":"10.1109\/DATE.2004.1269077","volume":"2","author":"L Feng","year":"2004","unstructured":"Feng L, Zeng X, Chiang C, Zhou D, Fang Q. Direct nonlinear order reduction with variational analysis. Design, Automation and Test in Europe Conference and Exhibition, 2004, 2: 1316?1321.","journal-title":"Design, Automation and Test in Europe Conference and Exhibition"},{"key":"CR141","doi-asserted-by":"crossref","unstructured":"Li P, Pileggi L T. NORM: Compact model order reduction of weakly nonlinear systems. Design Automation Conference, June, 2003, pp.472?477.","DOI":"10.1145\/775832.775955"},{"key":"CR142","doi-asserted-by":"crossref","unstructured":"Phillips J, Afonso J, Oliveira A, Silveira L M. Analog macromodeling using kernel methods. IEEE\/ACM Int. Conf. Computer-Aided Design, Nov. 2003, pp.446?453.","DOI":"10.1109\/ICCAD.2003.159722"},{"key":"CR143","doi-asserted-by":"crossref","unstructured":"Chen T-H, Chen C C-P. Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods. Design Automation Conf., June 2003, pp.559?562.","DOI":"10.1145\/378239.379023"},{"key":"CR144","doi-asserted-by":"crossref","first-page":"1343","DOI":"10.1109\/TCAD.2002.804082","volume":"21","author":"Y-M Lee","year":"Nov. 2002","unstructured":"Lee Y-M, Chen C C-P. Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Nov. 2002, 21: 1343?1352.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR145","doi-asserted-by":"crossref","first-page":"1545","DOI":"10.1109\/TCAD.2003.818373","volume":"22","author":"Y-M Lee","year":"Nov. 2003","unstructured":"Lee Y-M, Chen C C-P. The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Nov. 2003, 22: 1545?1550.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR146","doi-asserted-by":"crossref","first-page":"1148","DOI":"10.1109\/TCAD.2002.802271","volume":"21","author":"J N Kozhaya","year":"Oct. 2002","unstructured":"Kozhaya J N, Nassif S R, Najm F N. A multigrid-like technique for power grid analysis. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Oct. 2002, 21: 1148?1160.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR147","doi-asserted-by":"crossref","unstructured":"Su H, Acar E, Nassif S R. Power grid reduction based on algebraic multigrid principles. Design Automation Conference, June 2003, pp.109?112.","DOI":"10.1145\/775832.775863"},{"key":"CR148","doi-asserted-by":"crossref","unstructured":"Zhu Z, Yao B, Cheng C-K. Power network analysis using an adaptive algebraic multigrid approach. Design Automation Conference, June 2003, pp.105?108.","DOI":"10.1145\/775832.775862"},{"key":"CR149","doi-asserted-by":"crossref","unstructured":"Wang K, Marek-Sadowska M. On-chip power supply network optimization using multigrid-based technique. Design Automation Conference, June 2003, pp.113?118.","DOI":"10.1145\/775832.775864"},{"key":"CR150","doi-asserted-by":"crossref","unstructured":"Qian H, Nassif S R, Sapatnekar S S. Random walks in a supply network. Design Automation Conf., June 2003, pp.93?98.","DOI":"10.1145\/775832.775860"},{"key":"CR151","doi-asserted-by":"crossref","unstructured":"Kouroussis D, Najm F N. A static pattern-independent technique for power grid voltage integrity verification. Design Automation Conf., June 2003, pp.99?104.","DOI":"10.1145\/775832.775861"},{"key":"CR152","doi-asserted-by":"crossref","first-page":"159","DOI":"10.1109\/43.980256","volume":"21","author":"M Zhao","year":"Feb. 2002","unstructured":"Zhao M, Panda R V, Sapatnekar S S, Blaauw D. Hierarchical analysis of power distribution networks. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Feb. 2002, 21: 159?168.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"3","key":"CR153","doi-asserted-by":"crossref","first-page":"209","DOI":"10.1109\/96.704931","volume":"21","author":"H Chen","year":"August1998","unstructured":"Chen H, Neely J. Interconnect and circuit modeling techniques for full-chip power supply noise analysis. IEEE Trans. Components, Packaging and Manufacturing Technology, Part B, August 1998, 21(3): 209?215.","journal-title":"IEEE Trans. Components, Packaging and Manufacturing Technology, Part B"},{"key":"CR154","doi-asserted-by":"crossref","first-page":"729","DOI":"10.1109\/5.929651","volume":"89","author":"W H Kao","year":"May 2001","unstructured":"Kao W H, Lo C-Y, Basel M, Singh R. Parasitic extraction: Current state of the art and future trends. In Proc. the IEEE, May 2001, 89: 729?739.","journal-title":"Proc. the IEEE"},{"key":"CR155","volume-title":"The Rapid Evaluation of Potential Fields in Particle Systems","author":"L Greengard","year":"1987","unstructured":"Greengard L. The Rapid Evaluation of Potential Fields in Particle Systems. Cambridge, MA: MIT Press, 1987."},{"key":"CR156","doi-asserted-by":"crossref","first-page":"1750","DOI":"10.1109\/22.310584","volume":"42","author":"M Kamon","year":"Sept. 1994","unstructured":"Kamon M, Tsuk M, White J. FastHenry: A multipole accelerated 3-D inductance extraction program. IEEE Trans. Microwave Theory Tech., Sept. 1994, 42: 1750?1758.","journal-title":"IEEE Trans. Microwave Theory Tech."},{"key":"CR157","doi-asserted-by":"crossref","first-page":"1447","DOI":"10.1109\/43.97624","volume":"10","author":"K Nabors","year":"Nov. 1991","unstructured":"Nabors K, White J K. FASTCAP: A multipole-accelerated 3-D capacitance extraction program. IEEE Trans. Computer-Aided Design, Nov. 1991, 10: 1447?1459.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"CR158","doi-asserted-by":"crossref","first-page":"330","DOI":"10.1109\/43.986426","volume":"21","author":"W Shi","year":"March 2002","unstructured":"Shi W, Liu J, Kakani N, Yu T. A fast hierarchical algorithm for three-dimensional capacitance extraction. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, March 2002, 21: 330?336.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR159","doi-asserted-by":"crossref","first-page":"288","DOI":"10.1109\/TCAD.2003.822109","volume":"23","author":"M W Beattie","year":"Feb. 2004","unstructured":"Beattie M W, Pileggi L T. Parasitics extraction with multipole refinement. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Feb. 2004, 23: 288?292.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"CR160","doi-asserted-by":"crossref","unstructured":"Yan S, Liu J, Shi W. Improving boundary element methods for parasitic extraction. In Proc. the Asia and South Pacific Design Automation Conf., Jan. 2003, pp.261?267.","DOI":"10.1145\/1119772.1119823"},{"key":"CR161","doi-asserted-by":"crossref","first-page":"665","DOI":"10.1109\/5.929649","volume":"89","author":"G E Friedman","year":"May 2001","unstructured":"Friedman E G. Clock distribution networks in synchronous digital integrated circuits. In Proc. the IEEE, May 2001, 89: 665?692.","journal-title":"Proc. the IEEE"},{"key":"CR162","doi-asserted-by":"crossref","first-page":"945","DOI":"10.1109\/12.55696","volume":"39","author":"P J Fishburn","year":"July 1990","unstructured":"Fishburn J P. Clock skew optimization. IEEE Trans. Comput., July 1990, 39: 945?951.","journal-title":"IEEE Trans. Comput."},{"key":"CR163","doi-asserted-by":"crossref","unstructured":"Szymanski T G, Shenoy N. Verifying clock schedules. In Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1992, pp.124?131.","DOI":"10.1109\/ICCAD.1992.279387"},{"key":"CR164","doi-asserted-by":"crossref","unstructured":"Deokar R B, Sapatnekar S S. A graph-theoretic approach to clock skew optimization. In Proc. the IEEE Int. Symp. Circuits and Systems, 1995, pp.407?410.","DOI":"10.1109\/ISCAS.1994.408825"},{"key":"CR165","doi-asserted-by":"crossref","unstructured":"Shenoy N, Brayton R K, Sangiovanni-Vincentelli A L. Graph algorithms for clock schedule optimization. Int. Conf. Computer-Aided Design, 1992, pp.132?136.","DOI":"10.1109\/ICCAD.1992.279401"},{"key":"CR166","doi-asserted-by":"crossref","unstructured":"Szymanski T. Computing optimal clock schedules. In Proc. Design Automation Conf., June 1992, pp.399?404.","DOI":"10.1109\/DAC.1992.227771"},{"key":"CR167","doi-asserted-by":"crossref","unstructured":"Albrecht C, Korte B, Schietke J, Vygen J. Cycle time and slack optimization for VLSI-Chips. Int. Conf. Computer Aided Design, 1999, pp.232?238.","DOI":"10.1109\/ICCAD.1999.810654"},{"key":"CR168","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-4411-1","volume-title":"Timing Optimization Through Clock Skew Scheduling","author":"I S Kourtev","year":"2000","unstructured":"Kourtev I S, Friedman E G. Timing Optimization Through Clock Skew Scheduling. Kluwer, Boston, 2000."},{"key":"CR169","doi-asserted-by":"crossref","unstructured":"Kourtev I S, Friedman E G. A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations. In Proc. the IEEE Int. ASIC\/SOC Conference, 1999, pp.210?215.","DOI":"10.1109\/ASIC.1999.806506"},{"key":"CR170","doi-asserted-by":"crossref","unstructured":"Held S et al. Clock scheduling and clocktree construction for high performance ASICs. Int. Conf. Computer-Aided Design, Nov. 2003, pp.232?239.","DOI":"10.1109\/ICCAD.2003.159695"},{"key":"CR171","doi-asserted-by":"crossref","unstructured":"Huang S-H, Nieh Y-T. Clock period minimization of non-zero clock skew circuits. Int. Conf. Computer-Aided Design, Nov. 2003, pp.809?812.","DOI":"10.1109\/ICCAD.2003.159769"},{"key":"CR172","doi-asserted-by":"crossref","first-page":"5","DOI":"10.1007\/BF01759032","volume":"6","author":"C E Leiserson","year":"1991","unstructured":"Leiserson C E, Saxe J B. Retiming synchronous circuitry. Algorithmica, 1991, 6: 5?35.","journal-title":"Algorithmica"},{"key":"CR173","doi-asserted-by":"crossref","unstructured":"Chu C, Young E F Y, Tong D K Y, Dechu S. Retiming with interconnect and gate delay. Int. Conf. Computer-Aided Design, Nov. 2003, pp.221?226.","DOI":"10.1109\/ICCAD.2003.159693"},{"key":"CR174","doi-asserted-by":"crossref","unstructured":"Ravindran K, Kuehlmann A, Sentovich E M. Multi-domain clock skew scheduling. Int. Conf. Computer-Aided Design, Nov. 2003, pp.801?808.","DOI":"10.1109\/ICCAD.2003.159768"},{"key":"CR175","doi-asserted-by":"crossref","unstructured":"Velenis D, Papaefthymiou M C, Friedman E G. Reduced delay uncertainty in high performance clock distribution networks. Design, Automation and Test in Europe Conference and Exhibition, 2003, pp.68?73.","DOI":"10.1109\/DATE.2003.1253589"}],"container-title":["Journal of Computer Science and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-005-0147-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11390-005-0147-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-005-0147-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,31]],"date-time":"2024-12-31T19:52:08Z","timestamp":1735674728000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11390-005-0147-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,3]]},"references-count":175,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2005,3]]}},"alternative-id":["147"],"URL":"https:\/\/doi.org\/10.1007\/s11390-005-0147-5","relation":{},"ISSN":["1000-9000","1860-4749"],"issn-type":[{"type":"print","value":"1000-9000"},{"type":"electronic","value":"1860-4749"}],"subject":[],"published":{"date-parts":[[2005,3]]}}}