{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T19:40:03Z","timestamp":1740598803681,"version":"3.38.0"},"reference-count":14,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Comput. Sci. Technol."],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1007\/s11390-010-9390-5","type":"journal-article","created":{"date-parts":[[2010,9,5]],"date-time":"2010-09-05T09:12:13Z","timestamp":1283677933000},"page":"1092-1100","source":"Crossref","is-referenced-by-count":0,"title":["Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips"],"prefix":"10.1007","volume":"25","author":[{"given":"Xu-Guang","family":"Guan","sequence":"first","affiliation":[]},{"given":"Xing-Yuan","family":"Tong","sequence":"additional","affiliation":[]},{"given":"Yin-Tang","family":"Yang","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2010,9,10]]},"reference":[{"key":"9390_CR1","doi-asserted-by":"crossref","unstructured":"Dally W J, Towles B. Route packets, not wires: On-chip interconnection networks. In Proc. 38th ACM Conf. Design Automation, Las Vegas, Nevada, Jun. 18-22, 2001, pp.684\u2013689.","DOI":"10.1109\/DAC.2001.935594"},{"issue":"1","key":"9390_CR2","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L Benini","year":"2002","unstructured":"Benini L, Micheli G D. Networks on chips: A new SoC paradigm. Computer, 2002, 35(1): 70\u201378.","journal-title":"Computer"},{"issue":"2","key":"9390_CR3","doi-asserted-by":"crossref","first-page":"257","DOI":"10.1007\/s11390-010-9322-4","volume":"25","author":"JL Wang","year":"2010","unstructured":"Wang J L, Xue Y B, Wang H X, Li C M, Wang D S. CCNoC: Cache-coherent network on chip for chip multiprocessors. J. Comput. Sci. & Technol., 2010, 25(2): 257\u2013266.","journal-title":"J. Comput. Sci. & Technol."},{"issue":"5","key":"9390_CR4","doi-asserted-by":"crossref","first-page":"16","DOI":"10.1109\/MM.2002.1044296","volume":"22","author":"J Bainbridge","year":"2002","unstructured":"Bainbridge J, Furber S B. CHAIN: A delay-insensitive chip area Interconnect. IEEE Micro, 2002, 22(5): 16\u201323.","journal-title":"IEEE Micro"},{"issue":"1","key":"9390_CR5","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1109\/MM.2004.1268991","volume":"24","author":"A Lines","year":"2004","unstructured":"Lines A. Asynchronous interconnect for synchronous SoC design. IEEE Micro, 2004, 24(1): 32\u201341.","journal-title":"IEEE Micro"},{"issue":"3","key":"9390_CR6","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1109\/MC.2005.106","volume":"38","author":"D Geer","year":"2005","unstructured":"Geer D. Is it time for clockless chips? Computer, 2005, 38(3): 18\u201321.","journal-title":"Computer"},{"issue":"5","key":"9390_CR7","doi-asserted-by":"crossref","first-page":"418","DOI":"10.1109\/MDT.2007.151","volume":"24","author":"P Teehan","year":"2007","unstructured":"Teehan P, Greenstreet M, Lemieux G. A survey and taxonomy of GALS design styles. IEEE Design & Test of Computers, 2007, 24(5): 418\u2013428.","journal-title":"IEEE Design & Test of Computers"},{"issue":"6","key":"9390_CR8","doi-asserted-by":"crossref","first-page":"572","DOI":"10.1109\/MDT.2008.167","volume":"25","author":"A Sheibanyrad","year":"2008","unstructured":"Sheibanyrad A, Greiner A, Miro-Panades I. Multisynchronous and fully asynchronous NoCs for GALS architectures. IEEE Design & Test of Computers, 2008, 25(6): 572\u2013580.","journal-title":"IEEE Design & Test of Computers"},{"issue":"5","key":"9390_CR9","doi-asserted-by":"crossref","first-page":"430","DOI":"10.1109\/MDT.2007.164","volume":"24","author":"M Krstic","year":"2007","unstructured":"Krstic M, Grass E, Gurkaynak F K, Vivet P. Globally asynchronous, locally synchronous circuits: Overview and outlook. IEEE Design & Test of Computers, 2007, 24(5): 430\u2013441.","journal-title":"IEEE Design & Test of Computers"},{"issue":"3","key":"9390_CR10","doi-asserted-by":"crossref","first-page":"367","DOI":"10.1016\/j.vlsi.2008.11.006","volume":"42","author":"RR Dobkin","year":"2009","unstructured":"Dobkin R R, Ginosar R. Two-phase synchronization with subcycle latency. Integration, the VLSI Journal, 2009, 42(3): 367\u2013375.","journal-title":"Integration, the VLSI Journal"},{"issue":"1","key":"9390_CR11","doi-asserted-by":"crossref","first-page":"17","DOI":"10.1016\/j.vlsi.2007.04.006","volume":"41","author":"A Sheibanyrad","year":"2008","unstructured":"Sheibanyrad A, Greiner PA. Two efficient synchronous \u2194 asynchronous converters well-suited for networks-on-chip in GALS architectures. Integration, the VLSI Journal, 2008, 41(1): 17\u201326.","journal-title":"Integration, the VLSI Journal"},{"key":"9390_CR12","doi-asserted-by":"crossref","unstructured":"Beigne E, Vivet P. Design of on-chip and off-chip interfaces for a GALS NoC architecture. In Proc. the 12th International Symposium on Advanced Research in Asynchronous Circuits and Systems, Grenoble, Mar. 13-15, 2006, pp.172\u2013181.","DOI":"10.1109\/ASYNC.2006.16"},{"key":"9390_CR13","doi-asserted-by":"crossref","unstructured":"Yvain T, Edith B, Pascal V. Design and implementation of a GALS adapter for ANoC based architectures. In Proc. the 15th International Symposium on Asynchronous Circuits and Systems, Chapel Hill, USA, May 17-20, 2009, pp.13\u201322.","DOI":"10.1109\/ASYNC.2009.13"},{"key":"9390_CR14","doi-asserted-by":"crossref","unstructured":"Beigne E, Clermidy F, Miermont S, Vivet P. Dynamic voltage and frequency scaling architecture for units integration within a GALS NoC. In Proc. the 2nd IEEE International Symposium on Networks-on-Chip, Newcastle Upon Tyne, UK, Apr. 7-11, 2008, pp.129\u2013138.","DOI":"10.1109\/NOCS.2008.4492732"}],"container-title":["Journal of Computer Science and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-010-9390-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11390-010-9390-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-010-9390-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T15:20:58Z","timestamp":1740496858000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11390-010-9390-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":14,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2010,9]]}},"alternative-id":["9390"],"URL":"https:\/\/doi.org\/10.1007\/s11390-010-9390-5","relation":{},"ISSN":["1000-9000","1860-4749"],"issn-type":[{"type":"print","value":"1000-9000"},{"type":"electronic","value":"1860-4749"}],"subject":[],"published":{"date-parts":[[2010,9]]}}}