{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:01:03Z","timestamp":1761580863997,"version":"3.38.0"},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2011,3,1]],"date-time":"2011-03-01T00:00:00Z","timestamp":1298937600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Comput. Sci. Technol."],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1007\/s11390-011-9436-3","type":"journal-article","created":{"date-parts":[[2011,3,6]],"date-time":"2011-03-06T21:26:54Z","timestamp":1299446814000},"page":"292-301","source":"Crossref","is-referenced-by-count":4,"title":["A Fine-Grained Runtime Power\/Performance Optimization Method for Processors with Adaptive Pipeline Depth"],"prefix":"10.1007","volume":"26","author":[{"given":"Jun","family":"Yao","sequence":"first","affiliation":[]},{"given":"Shinobu","family":"Miwa","sequence":"additional","affiliation":[]},{"given":"Hajime","family":"Shimada","sequence":"additional","affiliation":[]},{"given":"Shinji","family":"Tomita","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2011,3,5]]},"reference":[{"key":"9436_CR1","unstructured":"Shimada H, Ando H, Shimada T. Pipeline stage unification for low-power vonsumption. In Proc. the 5th International Symposium on Low-Power and High-Speed Chips (COOL Chips V), Tokyo, Japan, Apr. 18\u201320, 2002, pp.194\u2013200."},{"issue":"3","key":"9436_CR2","first-page":"75","volume":"48","author":"H Shimada","year":"2007","unstructured":"Shimada H, Ando H, Shimada T. Power consumption reduction through combining pipeline stage unification and DVS. IPSJ Transactions on Advanced Computing Systems (ACS), Feb. 2007, 48(3): 75\u201387. (In Japanese)","journal-title":"IPSJ Transactions on Advanced Computing Systems (ACS)"},{"key":"9436_CR3","doi-asserted-by":"crossref","unstructured":"Koppanalil J, Ramrakhyani P, Desai S, Vaidyanathan A, Rotenberg E. A case for dynamic pipeline scaling. In Proc. the 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, Grenoble, France, Oct. 8\u201311, 2002, pp.1\u20138.","DOI":"10.1145\/581630.581632"},{"issue":"9","key":"9436_CR4","doi-asserted-by":"crossref","first-page":"1277","DOI":"10.1109\/4.535411","volume":"31","author":"R Gonzalez","year":"1996","unstructured":"Gonzalez R, Horowitz M. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, Sept. 1996, 31(9): 1277\u20131284.","journal-title":"IEEE Journal of Solid-State Circuits, Sept."},{"issue":"4","key":"9436_CR5","doi-asserted-by":"crossref","first-page":"1010","DOI":"10.1093\/ietisy\/e91-d.4.1010","volume":"E91-D","author":"J Yao","year":"2008","unstructured":"Yao J, Miwa S, Shimada H, Tomita S. A dynamic control mechanism for pipeline stage unification by identifying program phases. IEICE Transactions on Information and Systems, Apr. 2008, E91-D(4): 1010\u20131022.","journal-title":"IEICE Transactions on Information and Systems"},{"key":"9436_CR6","unstructured":"Intel Pentium M processor on 90nm process with 2MB L2 cache datasheet. Intel Corporation, 2006."},{"key":"9436_CR7","unstructured":"Hartstein A, Puzak T R. Optimum power\/performance pipeline depth. In Proc. the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, San Diego, USA, Dec. 3\u20135, 2003, pp.117\u2013128."},{"key":"9436_CR8","doi-asserted-by":"crossref","unstructured":"Srinivasan V, Brooks D, Gschwind M, Bose P, Zyuban V, Strenski P N, Emma P G. Optimizing pipelines for power and performance. In Proc. the 35th Annual ACM\/IEEE International Symposium on Microarchitecture, Istanbul, Turkey, Nov. 18\u201322, 2002, pp.333\u2013344.","DOI":"10.1109\/MICRO.2002.1176261"},{"key":"9436_CR9","doi-asserted-by":"crossref","unstructured":"Geissler S, Appenzeller D, Cohen E, Charlebois S, Kartschoke P, McCormick P, Rohrer N, Salem G, Sandon P, Singer B, Reyn T V, Zimmerman J. A low-power RISC microprocessor using dual PLLs in a 0.13 \u03bcm SOI technology with copper interconnect and low-k BEOL dielectric. In Proc. IEEE International Solid-State Circuits Conference, San Francisco, USA, Feb. 3\u20137, 2002, Vol.1, pp.148\u2013149.","DOI":"10.1109\/ISSCC.2002.992979"},{"key":"9436_CR10","unstructured":"Senger R M, Marsman E D, Carichner G A, Kubba S, McCorquodale M S, Brown R B. Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking. In Proc. IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21\u201324, 2006, pp.21\u201324."},{"issue":"6","key":"9436_CR11","doi-asserted-by":"crossref","first-page":"84","DOI":"10.1109\/MM.2003.1261391","volume":"23","author":"T Sherwood","year":"2003","unstructured":"Sherwood T, Perelman E, Hamerly G, Sair S, Calder B. Discovering and exploiting program phases. IEEE Micro, Nov.\/Dec. 2003, 23(6): 84\u201393.","journal-title":"IEEE Micro"},{"issue":"5","key":"9436_CR12","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1109\/MM.2005.93","volume":"25","author":"C Isci","year":"2005","unstructured":"Isci C, Buyuktosunoglu A, Martonosi M. Long-term workload phases: Duration predictions and applications to DVFS. IEEE Micro, 2005, 25(5): 39\u201351.","journal-title":"IEEE Micro"},{"key":"9436_CR13","doi-asserted-by":"crossref","unstructured":"Isci C, Contreras G, Martonosi M. Live, runtime phase monitoring and prediction on real systems with application to dynamic power management. In Proc. Micro 2006, Orlando, USA, 2006, pp.359\u2013370.","DOI":"10.1109\/MICRO.2006.30"},{"key":"9436_CR14","doi-asserted-by":"crossref","unstructured":"Hartstein A, Puzak T R. The optimum pipeline depth for a microprocessor. In Proc. the 29th Annual International Symposium on Computer Architecture, Anchorage, May 25\u201329, USA, 2002, pp.7\u201313.","DOI":"10.1145\/545214.545217"},{"key":"9436_CR15","doi-asserted-by":"crossref","unstructured":"Shimada H, Ando H, Shimada T. Pipeline stage unification: A low-energy consumption technique for future mobile processors. In Proc. the 2003 International Symposium on Low Power Electronics and Design, Seoul, Korea, Aug. 25\u201327, 2003, pp.326\u2013329.","DOI":"10.1145\/871506.871587"},{"key":"9436_CR16","doi-asserted-by":"crossref","unstructured":"Brooks D, Tiwari V, Martonosi M. Wattch: A framework for architectural-level power analysis and optimizations. In Proc. the 27th Annual International Symposium on Computer Architecture, Vancouver, Canada, Jun. 10\u201314, 2000, pp.83\u201394.","DOI":"10.1145\/342001.339657"},{"issue":"5","key":"9436_CR17","doi-asserted-by":"crossref","first-page":"564","DOI":"10.1109\/TVLSI.2005.844295","volume":"13","author":"H Li","year":"2005","unstructured":"Li H, Cher C Y, Roy K, Vijaykumar T N. Combined circuit and architectural level variable supply-voltage scaling for low power. IEEE Trans. VLSI Systems, May 2005, 13(5): 564\u2013576.","journal-title":"IEEE Trans. VLSI Systems"},{"key":"9436_CR18","doi-asserted-by":"crossref","unstructured":"Dhodapkar A S, Smith J E. Managing multi-configuration hardware via dynamic working set analysis. In Proc. the 29th Annual International Symposium on Computer Architecture, Anchorage, USA, May 25\u201329, 2002, pp.233\u2013244.","DOI":"10.1145\/545214.545241"},{"issue":"3","key":"9436_CR19","doi-asserted-by":"crossref","first-page":"13","DOI":"10.1145\/268806.268810","volume":"25","author":"D Burger","year":"1997","unstructured":"Burger D, Austin T M. The SimpleScalar tool set, Version 2.0. SIGARCH Computer Architecture News, 1997, 25(3): pp.13\u201325.","journal-title":"SIGARCH Computer Architecture News"},{"key":"9436_CR20","unstructured":"Dhodapkar A S, Smith J E. Comparing program phase detection techniques. In Proc. the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, San Diego, USA, Dec. 3\u20135, 2003, pp.217\u2013227."}],"container-title":["Journal of Computer Science and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-011-9436-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11390-011-9436-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-011-9436-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,3]],"date-time":"2025-03-03T14:49:08Z","timestamp":1741013348000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11390-011-9436-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":20,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2011,3]]}},"alternative-id":["9436"],"URL":"https:\/\/doi.org\/10.1007\/s11390-011-9436-3","relation":{},"ISSN":["1000-9000","1860-4749"],"issn-type":[{"type":"print","value":"1000-9000"},{"type":"electronic","value":"1860-4749"}],"subject":[],"published":{"date-parts":[[2011,3]]}}}