{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T04:30:02Z","timestamp":1742358602897,"version":"3.40.1"},"reference-count":23,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Comput. Sci. Technol."],"published-print":{"date-parts":[[2012,1]]},"DOI":"10.1007\/s11390-012-1210-7","type":"journal-article","created":{"date-parts":[[2012,1,9]],"date-time":"2012-01-09T18:16:58Z","timestamp":1326133018000},"page":"113-120","source":"Crossref","is-referenced-by-count":6,"title":["Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm"],"prefix":"10.1007","volume":"27","author":[{"given":"Zhu-Fei","family":"Chu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yin-Shui","family":"Xia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lun-Yao","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2012,1,9]]},"reference":[{"issue":"1","key":"1210_CR1","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1109\/JPROC.2009.2032356","volume":"98","author":"M Haselman","year":"2010","unstructured":"Haselman M, Hauck S. The future of integrated circuits: A survey of nanoelectronics. Proceedings of the IEEE, 2010, 98(1): 11-38.","journal-title":"Proceedings of the IEEE"},{"issue":"6","key":"1210_CR2","doi-asserted-by":"crossref","first-page":"871","DOI":"10.1007\/s11390-006-0871-5","volume":"21","author":"W Wang","year":"2006","unstructured":"Wang W, Liu M, Hsu A. Hybrid nanoelectronics: Future of computer technology. Journal of Computer Science and Technology, 2006, 21(6): 871-886.","journal-title":"Journal of Computer Science and Technology"},{"issue":"3","key":"1210_CR3","doi-asserted-by":"crossref","first-page":"203","DOI":"10.1166\/jno.2008.301","volume":"3","author":"KK Likharev","year":"2008","unstructured":"Likharev K\u00a0K. Hybrid CMOS\/nanoelectronic circuits: Opportunities and challenges. Journal of Nanoelectronics and Optoelectronics, 2008, 3(3): 203-230.","journal-title":"Journal of Nanoelectronics and Optoelectronics"},{"issue":"3","key":"1210_CR4","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1049\/mnl:20080012","volume":"3","author":"Z Abid","year":"2008","unstructured":"Abid Z, Barua M, Alma'aitah A. Design of a transmission gate based CMOL memory array. IET Micro & Nano Letters, 2008, 3(3): 70-76.","journal-title":"IET Micro & Nano Letters"},{"issue":"1","key":"1210_CR5","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1166\/jnn.2007.18012","volume":"7","author":"DB Strukov","year":"2007","unstructured":"Strukov D B, Likharev K\u00a0K. Defect-tolerant architectures for nanoelectronic crossbar memories. Journal of Nanoscience and Nanotechnology, 2007, 7(1): 151-167.","journal-title":"Journal of Nanoscience and Nanotechnology"},{"key":"1210_CR6","doi-asserted-by":"crossref","unstructured":"Strukov D, Mishchenko A. Monolithically stackable hybrid FPGA. In Proc. DATE, Dresden, Germany, Mar. 8-12, 2010, pp.661-666.","DOI":"10.1109\/DATE.2010.5457117"},{"issue":"6","key":"1210_CR7","doi-asserted-by":"crossref","first-page":"888","DOI":"10.1088\/0957-4484\/16\/6\/045","volume":"16","author":"DB Strukov","year":"2005","unstructured":"Strukov D B, Likharev K\u00a0K. CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices. Nanotechnology, 2005, 16(6): 888-900.","journal-title":"Nanotechnology"},{"key":"1210_CR8","doi-asserted-by":"crossref","unstructured":"T\u00dcrel \u00d6, Lee J H, Ma X, Likharev K\u00a0K. Architectures for nanoelectronic implementation of artificial neural networks: New results. Neurocomputing, 2005, 64: 271-283.","DOI":"10.1016\/j.neucom.2004.11.023"},{"key":"1210_CR9","unstructured":"Strukov D B, Likharev K\u00a0K. CMOL FPGA circuits. In Proc. Int. Conf. Computer Design, Las Vegas, USA, June 26-29, 2006, pp.213-219."},{"key":"1210_CR10","doi-asserted-by":"crossref","unstructured":"Betz V, Rose J. VPR: A new packing, placement and routing tool for FPGA research. In Proc. the 7th International Work-shop on Field-Programmable Logic and Applications, London, UK, Sep. 1-3, 1997, pp.213-222.","DOI":"10.1007\/3-540-63465-7_226"},{"issue":"6","key":"1210_CR11","doi-asserted-by":"crossref","first-page":"823","DOI":"10.1109\/JSEN.2008.923261","volume":"8","author":"WNN Hung","year":"2008","unstructured":"Hung W\u00a0N\u2009N, Gao C, Song X, Hammerstrom D. Defect-tolerant CMOL cell assignment via satisfiability. IEEE Sensors Journal, 2008, 8(6): 823-830.","journal-title":"IEEE Sensors Journal"},{"key":"1210_CR12","doi-asserted-by":"crossref","unstructured":"Kim K, Karri R, Orailoglu A. Design automation for hybrid CMOS-nonoelectronics crossbars. In Proc. IEEE International Symposium on Nanoscale Architectures, Santa Clara,USA, Oct. 21-22, 2007, pp.27-32.","DOI":"10.1109\/NANOARCH.2007.4400854"},{"key":"1210_CR13","doi-asserted-by":"crossref","unstructured":"Chu Z, Xia Y, Wang L, Hu M. CMOL cell assignment based on dynamic interchange. In Proc. the 8th ASICON, Chang-sha, China, Oct. 20-23, 2009, pp.921-924.","DOI":"10.1109\/ASICON.2009.5351545"},{"key":"1210_CR14","doi-asserted-by":"crossref","unstructured":"Xia Y, Chu Z, Hung W\u00a0N\u2009N, Wang L, Song X. CMOL cell assignment by genetic algorithm. In Proc. the 8th NEWCAS, Montreal, Canada, June 20-23, 2010, pp.25-28.","DOI":"10.1109\/NEWCAS.2010.5603746"},{"key":"1210_CR15","doi-asserted-by":"crossref","unstructured":"Snider G S, Williams R S. Nano\/CMOS architectures using a field-programmable nanowire interconnect. Nanotechnology, 2007, 18(3), Article No. 035204.","DOI":"10.1088\/0957-4484\/18\/3\/035204"},{"issue":"10","key":"1210_CR16","doi-asserted-by":"crossref","first-page":"3640","DOI":"10.1021\/nl901874j","volume":"9","author":"Q Xia","year":"2009","unstructured":"Xia Q, Robinett W, Cumbie M\u00a0W, Banerjee N, Cardinali T\u00a0J, Yang J\u00a0J, Wu W, Li X, Tong W\u00a0M, Strukov D B, Snider G S, Medeiros-Ribeiro G, Williams R S. Memristor-CMOS hybrid integrated circuits for reconfigurable logic. Nano Letters, 2009, 9(10): 3640-3645.","journal-title":"Nano Letters"},{"issue":"2","key":"1210_CR17","doi-asserted-by":"crossref","first-page":"1015","DOI":"10.1166\/jnn.2009.C076","volume":"9","author":"D Tu","year":"2009","unstructured":"Tu D, Liu M, Wang W, Haruehanroengra S. 3D CMOS\/Molecular hybrid circuits. Journal of Nanoscience and Nanotechnology, 2009, 9(2): 1015-1018.","journal-title":"Journal of Nanoscience and Nanotechnology"},{"issue":"2","key":"1210_CR18","doi-asserted-by":"crossref","first-page":"40","DOI":"10.1049\/mnl:20070034","volume":"2","author":"D Tu","year":"2007","unstructured":"Tu D, Liu M, Wang W, Haruehanroengra S. Three-dimensional CMOL: Three-dimensional integration of CMOS\/nanomaterial hybrid digital circuits. IET Micro & Nano Letters, 2007, 2(2): 40-45.","journal-title":"IET Micro & Nano Letters"},{"issue":"3","key":"1210_CR19","doi-asserted-by":"crossref","first-page":"322","DOI":"10.1109\/TNANO.2008.2011732","volume":"8","author":"G Chen","year":"2009","unstructured":"Chen G, Song X, Hu P. A theoretical investigation on CMOL FPGA cell assignment problem. IEEE Transactions on Nanotechnology, 2009, 8(3): 322-329.","journal-title":"IEEE Transactions on Nanotechnology"},{"key":"1210_CR20","doi-asserted-by":"crossref","unstructured":"Xia Y, Almaini A E A. Genetic algorithm based state assignment for power and area optimisation. IEE Proceedings \u2014 Computers and Digital Techniques, 2002, 149(4): 128-133.","DOI":"10.1049\/ip-cdt:20020431"},{"key":"1210_CR21","volume-title":"Introduction to Genetic Algorithms","author":"SN Sivanandam","year":"2008","unstructured":"Sivanandam S N, Deepa S N. Introduction to Genetic Algorithms. Heidelberg: Springer, 2008."},{"key":"1210_CR22","unstructured":"Sentovich E M, Singh K\u00a0J, Lavagno L et al. SIS: A system for sequential circuit synthesis. Technical Report UCB\/ERL M92\/41, University of California, Berkeley, 1992."},{"key":"1210_CR23","doi-asserted-by":"crossref","unstructured":"Strukov D, Likharev K. A reconfigurable architecture for hybrid CMOS\/nanodevice circuits. In Proc. the 14th ACM\/SIGDA Int. Symp. Field Programmable Gate Arrays, Monterey, USA, Feb. 22-24, 2006, pp.131-140.","DOI":"10.1145\/1117201.1117221"}],"container-title":["Journal of Computer Science and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-012-1210-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11390-012-1210-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-012-1210-7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T16:57:18Z","timestamp":1742317038000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11390-012-1210-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":23,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,1]]}},"alternative-id":["1210"],"URL":"https:\/\/doi.org\/10.1007\/s11390-012-1210-7","relation":{},"ISSN":["1000-9000","1860-4749"],"issn-type":[{"type":"print","value":"1000-9000"},{"type":"electronic","value":"1860-4749"}],"subject":[],"published":{"date-parts":[[2012,1]]}}}