{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:37:43Z","timestamp":1761323863652,"version":"3.40.4"},"reference-count":34,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Comput. Sci. Technol."],"published-print":{"date-parts":[[2013,1]]},"DOI":"10.1007\/s11390-013-1312-x","type":"journal-article","created":{"date-parts":[[2013,2,1]],"date-time":"2013-02-01T16:52:54Z","timestamp":1359737574000},"page":"54-71","source":"Crossref","is-referenced-by-count":21,"title":["Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip"],"prefix":"10.1007","volume":"28","author":[{"given":"Xiao-Hang","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peng","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mei","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maurizio","family":"Palesi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ying-Tao","family":"Jiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael C","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2013,2,1]]},"reference":[{"issue":"10","key":"1312_CR1","doi-asserted-by":"crossref","first-page":"1081","DOI":"10.1109\/TVLSI.2007.893649","volume":"15","author":"VF Pavlidis","year":"2007","unstructured":"Pavlidis V F, Friedman E G. 3-D topologies for networks-on-chip. IEEE Trans. Very Large Scale Integration Systems, 2007, 15(10): 1081-1090","journal-title":"IEEE Trans. Very Large Scale Integration Systems"},{"issue":"6","key":"1312_CR2","doi-asserted-by":"crossref","first-page":"498","DOI":"10.1109\/MDT.2005.136","volume":"22","author":"WR Davis","year":"2005","unstructured":"Davis W R, Wilson J, Mick S et al. Demystifying 3D ICs: The pros and cons of going vertical. IEEE Design and Test of Computers, 2005, 22(6): 498-511.","journal-title":"IEEE Design and Test of Computers"},{"issue":"2","key":"1312_CR3","doi-asserted-by":"crossref","first-page":"230","DOI":"10.1016\/j.micpro.2010.10.001","volume":"35","author":"F Trivi\u00f1o","year":"2011","unstructured":"Trivi\u00f1o F, S\u00e1nchez J L, Alfaro F J, Flich J. Virtualizing network-on-chip resources in chip-multiprocessors. Microprocessors and Microsystems, 2011, 35(2): 230-245.","journal-title":"Microprocessors and Microsystems"},{"issue":"8","key":"1312_CR4","doi-asserted-by":"crossref","first-page":"1479","DOI":"10.1109\/TCAD.2008.925793","volume":"27","author":"C Zhu","year":"2008","unstructured":"Zhu C, Gu Z, Shang L, Dick R P, Joseph R. Three-dimensional chip-multiprocessor run-time thermal management. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(8): 1479-1492.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"doi-asserted-by":"crossref","unstructured":"Addo-Quaye C. Thermal-aware mapping and placement for 3-D NoC designs. In Proc. Int. SoC Conf., Sept. 2005, pp.25-28.","key":"1312_CR5","DOI":"10.1109\/SOCC.2005.1554447"},{"issue":"1","key":"1312_CR6","doi-asserted-by":"crossref","first-page":"78","DOI":"10.1109\/TCAD.2009.2034348","volume":"29","author":"CL Chou","year":"2010","unstructured":"Chou C L, Marculescu R. Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(1): 78-91.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"10","key":"1312_CR7","doi-asserted-by":"crossref","first-page":"1866","DOI":"10.1109\/TCAD.2008.2003301","volume":"27","author":"CL Chou","year":"2008","unstructured":"Chou C L, Ogras U Y, Marculescu R. Energy- and performance-aware incremental mapping for networks on chip with multiple voltage levels. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(10): 1866-1879.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"doi-asserted-by":"crossref","unstructured":"Matsutani H, Koibuchi M, Amano H. Tightly-coupled multi-layer topologies for 3-D NoCs, In Proc. Int. Conf. Parallel Processing, Sept. 2007, Article No.75.","key":"1312_CR8","DOI":"10.1109\/ICPP.2007.79"},{"issue":"1","key":"1312_CR9","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1109\/TC.2008.142","volume":"58","author":"BS Feero","year":"2009","unstructured":"Feero B S, Pande P P. Networks-on-chip in a three-dimensional environment: A performance evaluation. IEEE Trans. Computers, 2009, 58(1): 32-45.","journal-title":"IEEE Trans. Computers"},{"doi-asserted-by":"crossref","unstructured":"Kim J, Nicopoulos C, Park D et al. A novel dimensionally-decomposed router for on-chip communication in 3D architectures. In Proc. Int. Symp. Computer Architecture, June 2007, pp.138-149.","key":"1312_CR10","DOI":"10.1145\/1273440.1250680"},{"issue":"12","key":"1312_CR11","doi-asserted-by":"crossref","first-page":"1987","DOI":"10.1109\/TCAD.2010.2061610","volume":"29","author":"C Seiculescu","year":"2010","unstructured":"Seiculescu C, Murali S, Benini L, De Micheli G. Sunfloor 3D: A tool for networks on chip topology synthesis for 3-D systems on chips. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(12): 1987-2000.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"10","key":"1312_CR12","doi-asserted-by":"crossref","first-page":"1081","DOI":"10.1109\/TVLSI.2007.893649","volume":"15","author":"VF Pavlidis","year":"2007","unstructured":"Pavlidis V F, Friedman E G. 3-D topologies for networks-on-chip. IEEE Trans. Very Large Scale Integration Systems, 2007, 15(10): 1081-1090.","journal-title":"IEEE Trans. Very Large Scale Integration Systems"},{"issue":"1","key":"1312_CR13","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1736065.1736066","volume":"7","author":"X Wang","year":"2010","unstructured":"Wang X, Yang M, Jiang Y, Liu P. A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints. ACM Trans. Architecture and Code Optimization, 2010, 7(1): 1-30.","journal-title":"ACM Trans. Architecture and Code Optimization"},{"issue":"3","key":"1312_CR14","doi-asserted-by":"crossref","first-page":"497","DOI":"10.2307\/1910129","volume":"28","author":"AH Land","year":"1960","unstructured":"Land A H, Doig A G. An automatic method for solving discrete programming problems. Econometrica, 1960, 28(3): 497-520.","journal-title":"Econometrica"},{"issue":"4","key":"1312_CR15","doi-asserted-by":"crossref","first-page":"551","DOI":"10.1109\/TCAD.2005.844106","volume":"24","author":"J Hu","year":"2005","unstructured":"Hu J, Marculescu R. Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(4): 551-562.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"doi-asserted-by":"crossref","unstructured":"Addo-Quaye C. Thermal-aware mapping and placement for 3-D NoC designs. In Proc. Int. SoC Conf., Sept. 2005, pp.25-28.","key":"1312_CR16","DOI":"10.1109\/SOCC.2005.1554447"},{"unstructured":"Smit L T, Smit G J M, Hurink J L et al. Run-time assignment of tasks to multiple heterogeneous processors. In Proc. the 5th Progress Embedded System Symp., Oct. 2004, pp.185-192.","key":"1312_CR17"},{"doi-asserted-by":"crossref","unstructured":"Carvalho E, Calazans N, Moraes F. Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs. In Proc. the 18th IEEE\/IFIP Int. Workshop. Rapid System Prototyping, May 2007, pp.34-40.","key":"1312_CR18","DOI":"10.1109\/RSP.2007.26"},{"issue":"7","key":"1312_CR19","doi-asserted-by":"crossref","first-page":"712","DOI":"10.1109\/71.598346","volume":"8","author":"V Lo","year":"1997","unstructured":"Lo V, Windisch K J, Liu W, Nitzberg B. Noncontiguous processor allocation algorithms for mesh-connected multicomputers. Trans. Parallel and Distributed Systems, 1997, 8(7): 712-726.","journal-title":"Trans. Parallel and Distributed Systems"},{"doi-asserted-by":"crossref","unstructured":"Arjomand M, Sarbazi-Azad H. Voltage-frequency planning for thermal-aware, low-power design of regular 3-D NoCs. In Proc. the 23rd Int. Conf. VLSI Design, Jan. 2010, pp.57-62.","key":"1312_CR20","DOI":"10.1109\/VLSI.Design.2010.56"},{"issue":"1","key":"1312_CR21","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/TPDS.2009.27","volume":"21","author":"X Zhou","year":"2010","unstructured":"Zhou X, Yang J, Xu Y, Zhang Y, Zhao J. Thermal-aware task scheduling for 3D multi-core processors. IEEE Trans. Parallel and Distributed Systems, 2010, 21(1): 60-71.","journal-title":"IEEE Trans. Parallel and Distributed Systems"},{"doi-asserted-by":"crossref","unstructured":"Chao C H, Jheng K Y, Wang H Y et al. Traffic- and thermal-aware run-time thermal management scheme for 3D NoC systems. In Proc. the 4th ACM\/IEEE Int. Symp. Networks-on-Chip, May 2010, pp.223-230.","key":"1312_CR22","DOI":"10.1109\/NOCS.2010.32"},{"doi-asserted-by":"crossref","unstructured":"Truong D, Cheng W, Mohsenin T et al. A 167-processor 65nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling. In Proc. IEEE Symp. VLSI Circuits, June 2008, pp.22-23.","key":"1312_CR23","DOI":"10.1109\/VLSIC.2008.4585936"},{"doi-asserted-by":"crossref","unstructured":"Liu Y, Yang H, Dick R P, Wang H, Shang L. Thermal vs energy optimization for DVFS-enabled processors in embedded systems. In Proc. Int. Symp. Quality Electronic Design, March 2007, pp.204-209.","key":"1312_CR24","DOI":"10.1109\/ISQED.2007.158"},{"doi-asserted-by":"crossref","unstructured":"Srinivasan J, Adve S V, Bose P, Rivers J A. The impact of technology scaling on lifetime reliability. In Proc. Int. Conf. Dependable Systems and Networks, June 28-July 1, 2004, pp.177-186.","key":"1312_CR25","DOI":"10.1109\/DSN.2004.1311888"},{"issue":"5","key":"1312_CR26","doi-asserted-by":"crossref","first-page":"501","DOI":"10.1109\/TVLSI.2006.876103","volume":"14","author":"W Huang","year":"2006","unstructured":"Huang W, Ghosh S, Velusamy S et al. HotSpot: A compact thermal modeling methodology for early-stage VLSI design. IEEE Trans. Very Large Scale Integration Systems, 2006, 14(5): 501-513.","journal-title":"IEEE Trans. Very Large Scale Integration Systems"},{"unstructured":"Dally W J, Towles B. Principles and Practices of Interconnection Networks. San Francisco, USA: Morgan Kaufmann, 2004.","key":"1312_CR27"},{"doi-asserted-by":"crossref","unstructured":"Kahng A, Li B, Peh L S et al. Orion 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. In Proc. Conf. Design, Automation & Test in Europe, Apr. 2009, pp.423-428.","key":"1312_CR28","DOI":"10.1109\/DATE.2009.5090700"},{"key":"1312_CR29","volume-title":"Computers and Intractability: A Guide to the Theory of NP-Completeness","author":"MR Garey","year":"1979","unstructured":"Garey M R, Johnson D S. Computers and Intractability: A Guide to the Theory of NP-Completeness. New York, USA: WH Freeman, 1979."},{"issue":"2","key":"1312_CR30","doi-asserted-by":"crossref","first-page":"216","DOI":"10.1109\/TCAD.2006.887920","volume":"26","author":"M Lin","year":"2007","unstructured":"Lin M, Gamal A E, Lu Y C, Wong S. Performance benefits of monolithically stacked 3D-FPGA. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(2): 216-229.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"doi-asserted-by":"crossref","unstructured":"Dick R P, Rhodes D L, Wolf W. TGFF: Task graphs for free. In Proc. the 6th Int. Workshop on Hardware\/Software Code-sign, March 1998, pp.97-101.","key":"1312_CR31","DOI":"10.1145\/278241.278309"},{"doi-asserted-by":"crossref","unstructured":"Yang Y S, Bahn J H, Lee S E, Bagherzadeh N. Parallel and pipeline processing for block cipher algorithms on a network-on-chip. In Proc. the 6th Int. Conf. Information Technology: New Generations, Apr. 2009, pp.849-854.","key":"1312_CR32","DOI":"10.1109\/ITNG.2009.163"},{"doi-asserted-by":"crossref","unstructured":"Delorme J, Houzet D. A complete 4G radiocommunication application mapping onto a 2D mesh NoC architecture. In Proc. North-East Workshop. Circuits and Systems, June 2006, pp.93-96.","key":"1312_CR33","DOI":"10.1109\/NEWCAS.2006.250955"},{"doi-asserted-by":"crossref","unstructured":"Brooks D, Tiwari V, Martonosi M. Wattch: A framework for architectural-level power analysis and optimizations. In Proc. the 27th Int. Symp. Computer Architecture, June 2000, pp.83-94.","key":"1312_CR34","DOI":"10.1145\/342001.339657"}],"container-title":["Journal of Computer Science and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-013-1312-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11390-013-1312-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-013-1312-x","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,29]],"date-time":"2025-04-29T19:10:08Z","timestamp":1745953808000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11390-013-1312-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,1]]},"references-count":34,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2013,1]]}},"alternative-id":["1312"],"URL":"https:\/\/doi.org\/10.1007\/s11390-013-1312-x","relation":{},"ISSN":["1000-9000","1860-4749"],"issn-type":[{"type":"print","value":"1000-9000"},{"type":"electronic","value":"1860-4749"}],"subject":[],"published":{"date-parts":[[2013,1]]}}}