{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T06:24:05Z","timestamp":1761978245466,"version":"build-2065373602"},"reference-count":31,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2013,11,1]],"date-time":"2013-11-01T00:00:00Z","timestamp":1383264000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Comput. Sci. Technol."],"published-print":{"date-parts":[[2013,11]]},"DOI":"10.1007\/s11390-013-1396-3","type":"journal-article","created":{"date-parts":[[2013,11,14]],"date-time":"2013-11-14T05:46:44Z","timestamp":1384408004000},"page":"1045-1053","source":"Crossref","is-referenced-by-count":3,"title":["RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router"],"prefix":"10.1007","volume":"28","author":[{"given":"Yin-He","family":"Han","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cheng","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hang","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wen-Bo","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiao-Wei","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2013,11,8]]},"reference":[{"issue":"1","key":"1396_CR1","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L Benini","year":"2002","unstructured":"Benini L, De Micheli G. Networks on chips: A new SoC paradigm. Computer, 2002, 35(1): 70\u201378.","journal-title":"Computer"},{"key":"1396_CR2","unstructured":"De Micheli G, Benini L. Networks on Chips: Technology and Tools. Morgan Kaufmann Pub, 2006."},{"key":"1396_CR3","doi-asserted-by":"crossref","unstructured":"Borkar S. Microarchitecture and design challenges for gigascale integration. In Proc. the 37th International Symposium on Microarchitecture, Dec. 2004, p.3.","DOI":"10.1109\/MICRO.2004.24"},{"key":"1396_CR4","doi-asserted-by":"crossref","unstructured":"Dally W, Towles B. Route packets, not wires: On-chip inter-connection networks. In Proc. Design Automation Conference, June 2001, pp.684-689.","DOI":"10.1145\/378239.379048"},{"issue":"6","key":"1396_CR5","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/MM.2005.110","volume":"25","author":"S Borkar","year":"2005","unstructured":"Borkar S. Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. IEEE Micro, 2005, 25(6): 10\u201316.","journal-title":"IEEE Micro"},{"issue":"4","key":"1396_CR6","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1109\/MM.2003.1225959","volume":"23","author":"C Constantinescu","year":"2003","unstructured":"Constantinescu C. Trends and challenges in VLSI circuit reliability. IEEE Micro, 2003, 23(4): 14\u201319.","journal-title":"IEEE Micro"},{"issue":"9","key":"1396_CR7","doi-asserted-by":"crossref","first-page":"1173","DOI":"10.1109\/TVLSI.2008.2002108","volume":"17","author":"L Zhang","year":"2009","unstructured":"Zhang L, Han Y, Xu Q et al. On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems. IEEE Trans. Very Large Scale Integration Systems, 2009, 17(9): 1173\u20131186.","journal-title":"IEEE Trans. Very Large Scale Integration Systems"},{"key":"1396_CR8","doi-asserted-by":"crossref","unstructured":"Boppana R V, Chalasani S. Fault-tolerant routing with non-adaptive wormhole algorithms in mesh networks. In Proc. Supercomputing, Nov. 1994, pp.693-702.","DOI":"10.1145\/602884.602885"},{"key":"1396_CR9","doi-asserted-by":"crossref","unstructured":"Zhang Z, Greiner A, Taktak S. A reconfigurable routing algorithm for a fault-tolerant 2D-mesh network-on-chip. In Proc. Design Automation Conference, June 2008, pp.441-446.","DOI":"10.1145\/1391469.1391584"},{"key":"1396_CR10","doi-asserted-by":"crossref","unstructured":"Flick D, DeOrio A, Chen G et al. A highly resilient routing algorithm for fault-tolerant NoCs. In Proc. Conf. Design, Automation and Test in Europe, April 2009, pp.21-26.","DOI":"10.1109\/DATE.2009.5090627"},{"key":"1396_CR11","doi-asserted-by":"crossref","unstructured":"Flich J, Rodrigo S, Duato J. An efficient implementation of distributed routing algorithms for NoCs. In Proc. Int. Symp. Networks-on-Chip, April 2008, pp.87-96.","DOI":"10.1109\/NOCS.2008.4492728"},{"issue":"2","key":"1396_CR12","doi-asserted-by":"crossref","first-page":"137","DOI":"10.1016\/j.mejo.2012.12.008","volume":"44","author":"J Wang","year":"2013","unstructured":"Wang J, Gu H, Yang Y et al. An energy- and buffer-aware fully adaptive routing algorithm for Network-on-Chip. Microelectronics Journal, 2013, 44(2): 137\u2013144.","journal-title":"Microelectronics Journal"},{"issue":"5","key":"1396_CR13","doi-asserted-by":"crossref","first-page":"620","DOI":"10.1109\/TC.2008.211","volume":"58","author":"D Xiang","year":"2009","unstructured":"Xiang D, Zhang Y, Pan Y. Practical deadlock-free fault-tolerant routing in meshes based on the planar network fault model. IEEE Trans. Computers, 2009, 58(5): 620\u2013633.","journal-title":"IEEE Trans. Computers"},{"issue":"5","key":"1396_CR14","doi-asserted-by":"crossref","first-page":"800","DOI":"10.1109\/TPDS.2011.145","volume":"23","author":"D Xiang","year":"2012","unstructured":"Xiang D, Luo W. An efficient adaptive deadlock-free routing algorithm for torus networks. IEEE Trans. Parallel and Distributed System, 2012, 23(5): 800\u2013808.","journal-title":"IEEE Trans. Parallel and Distributed System"},{"key":"1396_CR15","doi-asserted-by":"crossref","unstructured":"Siewiorek D, Swarz R. Reliable Computer Systems: Design and Evaluation (3rd edition). A K Peters\/CRC Press, 1998.","DOI":"10.1201\/9781439863961"},{"key":"1396_CR16","doi-asserted-by":"crossref","unstructured":"Smolens J, Gold B, Kim J et al. Fingerprinting: Bounding soft-error-detection latency and bandwidth. In Proc. the 11th Int. Conf. Architectural Support for Programming Languages and Operating Systems, Oct. 2004, pp.224-234.","DOI":"10.1145\/1024393.1024420"},{"key":"1396_CR17","doi-asserted-by":"crossref","unstructured":"Weaver C, Austin T. A fault tolerant approach to microprocessor design. In Proc. International Conference on Dependable Systems and Networks, June 2001, pp.411-420.","DOI":"10.1109\/DSN.2001.941425"},{"key":"1396_CR18","unstructured":"Constantinides K, Plaza S, Blome J et al. BulletProof: A defect-tolerant CMP switch architecture. In Proc. the 12th International Symposium on High-Performance Computer Architecture, Feb. 2006, pp.5-16."},{"issue":"4","key":"1396_CR19","doi-asserted-by":"crossref","first-page":"379","DOI":"10.1109\/92.863617","volume":"8","author":"R Hegde","year":"2000","unstructured":"Hegde R, Shanbhag N R. Toward achieving energy efficiency in presence of deep submicronnoise. IEEE Trans. Very Large Scale Integration Systems, 2000, 8(4): 379\u2013391.","journal-title":"IEEE Trans. Very Large Scale Integration Systems"},{"key":"1396_CR20","doi-asserted-by":"crossref","unstructured":"Kim J, Park D, Nicopoulos C et al. Design and analysis of an NoC architecture from performance, reliability and energy perspective. In Proc. Int. Symp. Architecture for Networking and Communications Systems, Oct. 2005, pp.173-182.","DOI":"10.1145\/1095890.1095915"},{"key":"1396_CR21","doi-asserted-by":"crossref","unstructured":"Murali S, Atienza D, Benini L et al. A multi-path routing strategy with guaranteed in-order packet delivery and fault tolerance for networks on chip. In Proc. Design Automation Conference, June 2006, pp.845-848.","DOI":"10.1109\/DAC.2006.229239"},{"key":"1396_CR22","doi-asserted-by":"crossref","unstructured":"Koibuchi M, Matsutani H, Amano H et al. A lightweight fault-tolerant mechanism for network-on-chip. In Proc. ACM\/IEEE International Symposium on Networks-on-Chip, April 2008, pp.13-22.","DOI":"10.1109\/NOCS.2008.4492721"},{"key":"1396_CR23","doi-asserted-by":"crossref","unstructured":"Fick D, DeOrio A, Hu J et al. Vicis: A reliable network for unreliable silicon. In Proc. the 46th Design Automation Conference, July 2009, pp.812-817.","DOI":"10.1145\/1629911.1630119"},{"issue":"3","key":"1396_CR24","doi-asserted-by":"crossref","first-page":"426","DOI":"10.1109\/TCAD.2010.2041851","volume":"29","author":"M Palesi","year":"2010","unstructured":"Palesi M, Kumar S, Catania V. Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(3): 426\u2013440.","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"1396_CR25","doi-asserted-by":"crossref","unstructured":"Alaghi A, Karimi N, Sedghi M et al. Online NoC switch fault detection and diagnosis using a high level fault model. In Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems, Sept. 2007, pp.21-29.","DOI":"10.1109\/DFT.2007.55"},{"issue":"1","key":"1396_CR26","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/L-CA.2004.1","volume":"3","author":"ME Gomez","year":"2004","unstructured":"Gomez M E, Duato J, Flich J et al. An efficient fault-tolerant routing methodology for meshes and tori. Computer Architecture Letters, 2004, 3(1): 3.","journal-title":"Computer Architecture Letters"},{"issue":"4","key":"1396_CR27","doi-asserted-by":"crossref","first-page":"427","DOI":"10.1109\/TC.2004.1268400","volume":"53","author":"CT Ho","year":"2004","unstructured":"Ho C T, Stockmeyer L. A new approach to fault-tolerant wormhole routing for mesh-connected parallel computers. IEEE Trans. Computers, 2004, 53(4): 427\u2013438.","journal-title":"IEEE Trans. Computers"},{"key":"1396_CR28","doi-asserted-by":"crossref","unstructured":"Han Y, Xu Y, Li H et al. Test resource partitioning based on efficient response compaction for test time and tester channels reduction. In Proc. Asian Test Symposium, Nov. 2003, pp.440-445.","DOI":"10.1109\/ATS.2003.1250852"},{"issue":"2","key":"1396_CR29","doi-asserted-by":"crossref","first-page":"201","DOI":"10.1007\/s11390-005-0201-3","volume":"20","author":"Y Han","year":"2005","unstructured":"Han Y, Xu Y, Chandra A et al. Test resource partitioning based on efficient response compaction for test time and tester channels reduction. Journal of Computer Science and Technology, 2005, 20(2): 201\u2013210.","journal-title":"Journal of Computer Science and Technology"},{"issue":"5","key":"1396_CR30","doi-asserted-by":"crossref","first-page":"531","DOI":"10.1109\/TVLSI.2007.893652","volume":"15","author":"Y Han","year":"2007","unstructured":"Han Y, Hu Y, Li X et al. Embedded test decompressor to reduce the required channels and vector memory of tester for complex processor circuit. IEEE Trans. Very Large Scale Integration Systems, 2007, 15(5): 531\u2013540.","journal-title":"IEEE Trans. Very Large Scale Integration Systems"},{"key":"1396_CR31","doi-asserted-by":"crossref","unstructured":"Han Y, Hu Y, Li H et al. Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. In Proc. the 2005 Asia and South Pacific Design Automation Conference, Jan. 2005, pp.53-58.","DOI":"10.1145\/1120725.1120743"}],"container-title":["Journal of Computer Science and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-013-1396-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11390-013-1396-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-013-1396-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,30]],"date-time":"2025-04-30T20:31:27Z","timestamp":1746045087000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11390-013-1396-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,11]]},"references-count":31,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2013,11]]}},"alternative-id":["1396"],"URL":"https:\/\/doi.org\/10.1007\/s11390-013-1396-3","relation":{},"ISSN":["1000-9000","1860-4749"],"issn-type":[{"type":"print","value":"1000-9000"},{"type":"electronic","value":"1860-4749"}],"subject":[],"published":{"date-parts":[[2013,11]]}}}