{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,9]],"date-time":"2025-09-09T20:55:57Z","timestamp":1757451357884,"version":"3.40.4"},"reference-count":50,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Comput. Sci. Technol."],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1007\/s11390-014-1428-7","type":"journal-article","created":{"date-parts":[[2014,3,22]],"date-time":"2014-03-22T08:43:42Z","timestamp":1395477822000},"page":"255-272","source":"Crossref","is-referenced-by-count":7,"title":["MIMS: Towards a Message Interface Based Memory System"],"prefix":"10.1007","volume":"29","author":[{"given":"Li-Cheng","family":"Chen","sequence":"first","affiliation":[]},{"given":"Ming-Yu","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Yuan","family":"Ruan","sequence":"additional","affiliation":[]},{"given":"Yong-Bing","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Ze-Han","family":"Cui","sequence":"additional","affiliation":[]},{"given":"Tian-Yue","family":"Lu","sequence":"additional","affiliation":[]},{"given":"Yun-Gang","family":"Bao","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2014,3,23]]},"reference":[{"key":"1428_CR1","doi-asserted-by":"crossref","unstructured":"Udipi A N, Muralimanohar N, Chatterjee N et al. Rethinking DRAM design and organization for energy-constrained multi-cores. In Proc. the 37th Annual Int. Symposium on Computer Architecture, Jun. 2010, pp.175-186.","DOI":"10.1145\/1815961.1815983"},{"key":"1428_CR2","doi-asserted-by":"crossref","unstructured":"Wulf W A, McKee S A. Hitting the memory wall: Implications of the obvious. SIGARCH Computer Architecture News, 1995, 23(1): 20\u201324.","DOI":"10.1145\/216585.216588"},{"key":"1428_CR3","doi-asserted-by":"crossref","unstructured":"Rogers B M, Krishna A, Bell G B et al. Scaling the bandwidth wall: Challenges in and avenues for CMP scaling. In Proc. the 36th Annual Int. Symposium on Computer Architecture, Jun. 2009, pp.371-382.","DOI":"10.1145\/1555754.1555801"},{"key":"1428_CR4","doi-asserted-by":"crossref","unstructured":"Yoon D H, Jeong M K, Erez M. Adaptive granularity memory systems: A tradeoff between storage efficiency and through put. In Proc. the 38th Annual Int. Symposium on Computer Architecture, Jun. 2011, pp.295-306.","DOI":"10.1145\/2000064.2000100"},{"key":"1428_CR5","doi-asserted-by":"crossref","unstructured":"Ferdman M, Adileh A, Kocberber O et al. Clearing the clouds: A study of emerging scale-out workloads on modern hardware. In Proc. the 17th Int. Conf. Architectural Support for Programming Languages and Operating Systems, Mar. 2012, pp.37-48.","DOI":"10.1145\/2150976.2150982"},{"key":"1428_CR6","doi-asserted-by":"crossref","unstructured":"Lotfi-Kamran P, Grot B, Ferdman M et al. Scale-out processors. In Proc. the 39th Int. Symposium on Computer Architecture, Jun. 2012, pp.500-511.","DOI":"10.1109\/ISCA.2012.6237043"},{"key":"1428_CR7","doi-asserted-by":"crossref","unstructured":"Yoon D H, Jeong M K, Sullivan M et al. The dynamic granularity memory system. In Proc. the 39th Int. Symposium on Computer Architecture, Jun. 2012, pp.548-559.","DOI":"10.1109\/ISCA.2012.6237047"},{"issue":"3","key":"1428_CR8","doi-asserted-by":"crossref","first-page":"675","DOI":"10.1109\/TADVP.2009.2013818","volume":"32","author":"H Fredriksson","year":"2009","unstructured":"Fredriksson H, Svensson C. Improvement potential and equalization example for multidrop DRAM memory buses. IEEE Transactions on Advanced Packaging, 2009, 32(3): 675\u2013682.","journal-title":"IEEE Transactions on Advanced Packaging"},{"key":"1428_CR9","doi-asserted-by":"crossref","unstructured":"Cooper-Balis E, Rosenfeld P, Jacob B. Buffer-on-board memory systems. In Proc. the 39th Int. Symposium on Computer Architecture, Jun. 2012, pp.392-403.","DOI":"10.1109\/ISCA.2012.6237034"},{"key":"1428_CR10","doi-asserted-by":"crossref","unstructured":"Lee B C, Ipek E, Mutlu O et al. Architecting phase change memory as a scalable dram alternative. In Proc. the 36th Annual Int. Symposium on Computer Architecture, Jun. 2009, pp.2-13.","DOI":"10.1145\/1555754.1555758"},{"key":"1428_CR11","doi-asserted-by":"crossref","unstructured":"Udipi A N, Muralimanohar N, Balsubramonian R et al. Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. In Proc. the 38th Annual Int. Symposium on Computer Architecture, Jun. 2011, pp.425-436.","DOI":"10.1145\/2000064.2000115"},{"key":"1428_CR12","doi-asserted-by":"crossref","unstructured":"Barroso L A, H\u00f6elzle U. The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines (1st edition). Morgan and Claypool Publishers, 2009.","DOI":"10.2200\/S00193ED1V01Y200905CAC006"},{"key":"1428_CR13","doi-asserted-by":"crossref","unstructured":"Deng Q Y, Meisner D, Ramos L et al. Memscale: Active low-power modes for main memory. In Proc. the 16th Int. Conf. Architectural Support for Programming Languages and Operating Systems, Mar. 2011, pp.225-238.","DOI":"10.1145\/1950365.1950392"},{"key":"1428_CR14","doi-asserted-by":"crossref","unstructured":"Li S, Chen K, Hsieh M Y et al. System implications of memory reliability in exascale computing. In Proc. the 2011 Int. Conf. for High Performance Computing, Networking, Storage and Analysis, Nov. 2011, Article No.46.","DOI":"10.1145\/2063384.2063445"},{"key":"1428_CR15","doi-asserted-by":"crossref","unstructured":"Yoon D H, Muralimanohar N, Chang J C et al. FREE-p: Protecting non-volatile memory against both hard and soft errors. In Proc. the 17th IEEE Int. Symposium on High Performance Computer Architecture, Feb. 2011, pp.466-477.","DOI":"10.1109\/HPCA.2011.5749752"},{"key":"1428_CR16","doi-asserted-by":"crossref","unstructured":"Draper J, Chame J, Hall M et al. The architecture of the DIVA processing-in-memory chip. In Proc. the 16th Int. Conf. Supercomputing, Jun. 2002, pp.14-25.","DOI":"10.1145\/514195.514197"},{"key":"1428_CR17","doi-asserted-by":"crossref","unstructured":"Fang Z, Zhang L X, Carter J B et al. Active memory operations. In Proc. the 21st Annual Int. Conf. Supercomputing, Jun. 2007, pp.232-241.","DOI":"10.1145\/1274971.1275004"},{"issue":"1","key":"1428_CR18","doi-asserted-by":"crossref","first-page":"510","DOI":"10.1007\/s11227-011-0735-9","volume":"62","author":"Z Fang","year":"2012","unstructured":"Fang Z, Zhang L X, Carter J B et al. Active memory controller. J. Supercomput., 2012, 62(1): 510\u2013549.","journal-title":"J. Supercomput."},{"key":"1428_CR19","unstructured":"Lynch B, Kumar S. Smart memory. In Hot Chips: A Symposium on High Performance Chips, Aug. 2010. http:\/\/www.hotchips.org\/wp-content\/uploads\/hc archives\/hc22\/H-C22.23.325-1-Kumar-Smart-Memory.pdf, Feb. 2014."},{"key":"1428_CR20","doi-asserted-by":"crossref","unstructured":"Ware F A, Hampel C. Improving power and data efficiency with threaded memory modules. In Proc. the 24th Int. Conf. Computer Design, Oct. 2006, pp.417-424.","DOI":"10.1109\/ICCD.2006.4380850"},{"issue":"1","key":"1428_CR21","doi-asserted-by":"crossref","first-page":"5","DOI":"10.1109\/L-CA.2008.13","volume":"8","author":"JH Ahn","year":"2009","unstructured":"Ahn J H, Leverich J, Schreiber R S et al. Multicore DIMM: An energy efficient memory module with independently controlled DRAMs. Computer Architecture Letters, 2009, 8(1):5\u20138.","journal-title":"Computer Architecture Letters"},{"key":"1428_CR22","doi-asserted-by":"crossref","unstructured":"Ahn J H, Jouppi N P, Kozyrakis C et al. Future scaling of processor-memory interfaces. In Proc. the Conf. High Performance Computing Networking, Storage and Analysis, Nov. 2009, Article No.42.","DOI":"10.1145\/1654059.1654102"},{"key":"1428_CR23","doi-asserted-by":"crossref","unstructured":"Zheng H Z, Lin J, Zhang Z et al. Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. In Proc. the 41st Annual IEEE\/ACM Int. Symposium on Microarchitecture, Nov. 2008, pp.210-221.","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"1428_CR24","doi-asserted-by":"crossref","unstructured":"Fang K, Zheng H Z, Zhu Z C. Heterogeneous mini-rank: Adaptive, power-efficient memory architecture. In Proc. the 39th Int. Conf. Parallel Processing, Sept. 2010, pp.21-29.","DOI":"10.1109\/ICPP.2010.11"},{"key":"1428_CR25","doi-asserted-by":"crossref","unstructured":"Zhang G F, Wang H D, Chen X K et al. Heterogeneous multi-channel: Fine-grained DRAM control for both system performance and power efficiency. In Proc. the 49th ACM\/EDAC\/IEEE Design Automation Conference (DAC), Jun. 2012, pp.876-881.","DOI":"10.1145\/2228360.2228517"},{"issue":"3","key":"1428_CR26","doi-asserted-by":"crossref","first-page":"34","DOI":"10.1109\/MM.2010.43","volume":"30","author":"E Cooper-Balis","year":"2010","unstructured":"Cooper-Balis E, Jacob B. Fine-grained activation for power reduction in DRAM. IEEE Micro, 2010, 30(3): 34\u201347.","journal-title":"IEEE Micro"},{"issue":"2","key":"1428_CR27","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/MM.2010.36","volume":"30","author":"TM Brewer","year":"2010","unstructured":"Brewer T M. Instruction set innovations for the convey HC-1 computer. IEEE Micro, 2010, 30(2): 70\u201379.","journal-title":"IEEE Micro"},{"key":"1428_CR28","doi-asserted-by":"crossref","unstructured":"Abts D, Bataineh A, Scott S et al. The cray blackwidow: A highly scalable vector multiprocessor. In Proc. the 2007 ACM\/IEEE Conf. Supercomputing, Nov. 2007, Article No.17.","DOI":"10.1145\/1362622.1362646"},{"key":"1428_CR29","doi-asserted-by":"crossref","unstructured":"Chen L, Cao Y N, Zhang Z. E3CC: A memory error protection scheme with novel address mapping for subranked and low-power memories. ACM Transactions on Architecture and Code Optimization, 2013, 10(4): Article No.32.","DOI":"10.1145\/2541228.2541239"},{"key":"1428_CR30","doi-asserted-by":"crossref","unstructured":"Yoon D H, Erez M. Virtualized and exible ECC for main memory. In Proc. the 15th Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems, Mar. 2010, pp.397-408.","DOI":"10.1145\/1736020.1736064"},{"key":"1428_CR31","doi-asserted-by":"crossref","unstructured":"Udipi A N, Muralimanohar N, Balsubramonian R et al. LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. In Proc. the 39th Annual Int. Symposium on Computer Architecture, Jun. 2012, pp.285-296.","DOI":"10.1109\/ISCA.2012.6237025"},{"key":"1428_CR32","doi-asserted-by":"crossref","unstructured":"Zheng H Z, Lin J, Zhang Z et al. Decoupled DIMM: Building high-bandwidth memory system using low-speed DRAM devices. In Proc. the 36th Annual Int. Symposium on Computer Architecture, Jun. 2009, pp.255-266.","DOI":"10.1145\/1555754.1555788"},{"key":"1428_CR33","doi-asserted-by":"crossref","unstructured":"Yoon D H, Chang J C, Muralimanohar N et al. BOOM: Enabling mobile memory based low-power server DIMMs. In Proc. the 39th Int. Symposium on Computer Architecture, Jun. 2012, pp.25-36.","DOI":"10.1109\/ISCA.2012.6237003"},{"issue":"2","key":"1428_CR34","doi-asserted-by":"crossref","first-page":"7","DOI":"10.1109\/MM.2010.38","volume":"30","author":"R Kalla","year":"2010","unstructured":"Kalla R, Sinharoy B, Starke W J et al. Power7: IBM's next-generation server processor. IEEE Micro, 2010, 30(2): 7\u201315.","journal-title":"IEEE Micro"},{"key":"1428_CR35","doi-asserted-by":"crossref","unstructured":"Van Huben G A, Lamb K D, Tremaine R B et al. Server-class DDR3 SDRAM memory buffer chip. IBM Journal of Research and Development, 2012, 56(1.2): Article No.3.","DOI":"10.1147\/JRD.2011.2177897"},{"key":"1428_CR36","doi-asserted-by":"crossref","unstructured":"Fang K, Chen L, Zhang Z et al. Memory architecture for integrating emerging memory technologies. In Proc. the 2011 Int. Conf. Parallel Architectures and Compilation Techniques, Oct. 2011, pp.403-412.","DOI":"10.1109\/PACT.2011.71"},{"key":"1428_CR37","doi-asserted-by":"crossref","unstructured":"Ham T J, Chelepalli B K, Xue N et al. Disintegrated control for energy-efficient and heterogeneous memory systems. In Proc. the 19th Int. Symposium on High Performance Computer Architecture, Feb. 2013, pp.424-435.","DOI":"10.1109\/HPCA.2013.6522338"},{"key":"1428_CR38","doi-asserted-by":"crossref","unstructured":"Hall M, Kogge P, Koller J et al. Mapping irregular applications to DIVA, a PIM-based data-intensive architecture. In Proc. the 1999 ACM\/IEEE Conf. Supercomputing (CDROM), Jan. 1999, Article No.57.","DOI":"10.1145\/331532.331589"},{"key":"1428_CR39","doi-asserted-by":"crossref","unstructured":"Qureshi M K, Srinivasan V, Rivers J A. Scalable high performance main memory system using phase-change memory technology. In Proc. the 36th Annual Int. Symposium on Computer Architecture, Jun. 2009, pp.24-33.","DOI":"10.1145\/1555754.1555760"},{"key":"1428_CR40","doi-asserted-by":"crossref","unstructured":"Zhou P, Zhao B, Yang J et al. A durable and energy efficient main memory using phase change memory technology. In Proc. the 36th Annual Int. Symposium on Computer Architecture, Jun. 2009, pp.14-23.","DOI":"10.1145\/1555754.1555759"},{"key":"1428_CR41","doi-asserted-by":"crossref","unstructured":"Zhang W Y, Li T. Exploring phase change memory and 3D die-stacking for power\/thermal friendly, fast and durable memory architectures. In Proc. the 18th Int. Conf. Parallel Architectures and Compilation Techniques, Sept. 2009, pp.101-112.","DOI":"10.1109\/PACT.2009.30"},{"key":"1428_CR42","doi-asserted-by":"crossref","unstructured":"Stuecheli J, Kaseridis D, Daly D et al. The virtual write queue: Coordinating DRAM and last-level cache policies. In Proc. the 37th Annual Int. Symposium on Computer Architecture, Jun. 2010, pp.72-82.","DOI":"10.1145\/1815961.1815972"},{"key":"1428_CR43","doi-asserted-by":"crossref","unstructured":"Chatterjee N, Muralimanohar N, Balasubramonian R et al. Staged reads: Mitigating the impact of DRAM writes on DRAM reads. In Proc. the 18th Int. Symposium on High-Performance Computer Architecture, Feb. 2012, pp.41-52.","DOI":"10.1109\/HPCA.2012.6168943"},{"issue":"1","key":"1428_CR44","doi-asserted-by":"crossref","first-page":"16","DOI":"10.1109\/L-CA.2011.4","volume":"10","author":"P Rosenfeld","year":"2011","unstructured":"Rosenfeld P, Cooper-Balis E, Jacob B. DRAMSIM2: A cycle accurate memory system simulator. Computer Architecture Letters, 2011, 10(1): 16\u201319.","journal-title":"Computer Architecture Letters"},{"key":"1428_CR45","doi-asserted-by":"crossref","unstructured":"Rixner S, Dally W J, Kapasi U J et al. Memory access scheduling. In Proc. the 27th Annual Int. Symposium on Computer Architecture, Jun. 2000, pp.128-138.","DOI":"10.1145\/342001.339668"},{"key":"1428_CR46","doi-asserted-by":"crossref","unstructured":"Luk C K, Cohn R, Muth R et al. Pin: Building customized program analysis tools with dynamic instrumentation. In Proc. the 2005 ACM SIGPLAN Conf. Programming Language Design and Implementation, Jun. 2005, pp.190-200.","DOI":"10.1145\/1065010.1065034"},{"key":"1428_CR47","doi-asserted-by":"crossref","unstructured":"Bienia C, Kumar S, Singh J P et al. The PARSEC benchmark suite: Characterization and architectural implications. In Proc. the 17th Int. Conf. Parallel Architectures and Compilation Techniques, Oct. 2008, pp.72-81.","DOI":"10.1145\/1454115.1454128"},{"key":"1428_CR48","doi-asserted-by":"crossref","unstructured":"Bader D A, Cong G J, Feo J. On the architectural requirements for efficient execution of graph algorithms. In Proc. the 2005 Int. Conf. Parallel Processing, Jun. 2005, pp.547-556.","DOI":"10.1109\/ICPP.2005.55"},{"key":"1428_CR49","doi-asserted-by":"crossref","unstructured":"Bader D A, Madduri K. Design and implementation of the HPCS graph analysis benchmark on symmetric multiprocessors. In Proc. the 12th Int. Conf. High Performance Computing, Dec. 2005, pp.465-476.","DOI":"10.1007\/11602569_48"},{"key":"1428_CR50","doi-asserted-by":"crossref","unstructured":"Lu T Y, Chen L C, Chen M Y. Achieving efficient packet-based memory system by exploiting correlation of memory requests. In proc. Design, Automation & Test in Europe, Mar. 2014, to be appeared.","DOI":"10.7873\/DATE.2014.090"}],"container-title":["Journal of Computer Science and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-014-1428-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11390-014-1428-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-014-1428-7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,2]],"date-time":"2025-05-02T04:00:46Z","timestamp":1746158446000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11390-014-1428-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":50,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2014,3]]}},"alternative-id":["1428"],"URL":"https:\/\/doi.org\/10.1007\/s11390-014-1428-7","relation":{},"ISSN":["1000-9000","1860-4749"],"issn-type":[{"type":"print","value":"1000-9000"},{"type":"electronic","value":"1860-4749"}],"subject":[],"published":{"date-parts":[[2014,3]]}}}