{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,18]],"date-time":"2025-05-18T04:02:46Z","timestamp":1747540966953,"version":"3.40.5"},"reference-count":33,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J. Comput. Sci. Technol."],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1007\/s11390-015-1506-5","type":"journal-article","created":{"date-parts":[[2015,1,20]],"date-time":"2015-01-20T08:11:28Z","timestamp":1421741488000},"page":"84-96","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["CRAIS: A Crossbar-Based Interconnection Scheme on FPGA for Big Data"],"prefix":"10.1007","volume":"30","author":[{"given":"Chao","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xi","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xue-Hai","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2015,1,21]]},"reference":[{"key":"1506_CR1","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1038\/455047a","volume":"455","author":"D Howe","year":"2008","unstructured":"Howe D, Costanzo M, Fey P et al. Big data: The future of biocuration. Nature, 2008, 455:47-50.","journal-title":"Nature"},{"issue":"8","key":"1506_CR2","doi-asserted-by":"crossref","first-page":"46","DOI":"10.1145\/1978542.1978558","volume":"54","author":"S Singh","year":"2011","unstructured":"Singh S. Computing without processors. Communications of ACM, 2011, 54(8):46-54.","journal-title":"Communications of ACM"},{"key":"1506_CR3","doi-asserted-by":"crossref","unstructured":"Huang Y, Ienne P, Temam O et al. Elastic CGRAs. In Proc. ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, February 2013, pp.171-180.","DOI":"10.1145\/2435264.2435296"},{"key":"1506_CR4","doi-asserted-by":"crossref","unstructured":"Chen T, Du Z, Sun N et al. DianNao: A small-footprint high-throughput accelerator for ubiquitous machine learning. In Proc. the 19th International Conference on Architectural Support for Programming Languages and Operating Systems, March 2014, pp.269-284.","DOI":"10.1145\/2541940.2541967"},{"key":"1506_CR5","doi-asserted-by":"crossref","unstructured":"Chen Y, Luo T, Liu S et al. DaDianNao: A machinelearning supercomputer. In Proc. the 47th IEEE\/ACM International Symposium on Microarchitecture, December 2014.","DOI":"10.1109\/MICRO.2014.58"},{"key":"1506_CR6","doi-asserted-by":"crossref","unstructured":"Wang C, Li X, Chen P et al. Heterogeneous cloud framework for big data genome sequencing. IEEE\/ACM Transactions on Computational Biology and Bioinformatics, 2014. (preprint)","DOI":"10.1109\/TCBB.2014.2351800"},{"issue":"2","key":"1506_CR7","doi-asserted-by":"crossref","first-page":"46","DOI":"10.1109\/MM.2007.39","volume":"27","author":"J Wawrzynek","year":"2007","unstructured":"Wawrzynek J, Patterson D, Oskin M et al. RAMP: Research accelerator for multiple processors. IEEE Micro, 2007, 27(2):46-57.","journal-title":"IEEE Micro"},{"key":"1506_CR8","doi-asserted-by":"crossref","unstructured":"Panainte E, Bertels K, Vassiliadis S. The Molen compiler for reconfigurable processors. ACM Transactions on Embedded Computing Systems, 2007, 6(1): Article No. 6.","DOI":"10.1145\/1210268.1210274"},{"issue":"1","key":"1506_CR9","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L Benini","year":"2002","unstructured":"Benini L, De Micheli G. Networks on chips: A new SoC paradigm. IEEE Computer, 2002, 35(1):70-78.","journal-title":"IEEE Computer"},{"issue":"10","key":"1506_CR10","doi-asserted-by":"crossref","first-page":"1701","DOI":"10.1109\/TCAD.2008.923415","volume":"27","author":"W Wolf","year":"2008","unstructured":"Wolf W, Jerraya A, Martin G. Multiprocessor systemon-chip (MPSoC) technology. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(10):1701-1713.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"1506_CR11","doi-asserted-by":"crossref","unstructured":"Dally W J, Towles B. Route, packets, not wires: On-chip interconnection networks. In Proc. the 38th Annual Design Automation Conference. June 2001, pp.684-689.","DOI":"10.1145\/378239.379048"},{"key":"1506_CR12","doi-asserted-by":"crossref","unstructured":"Tuan V, Katsura N, Matsutani H et al. Evaluation of a multicore reconfigurable architecture with variable core sizes. In Proc. IEEE International Symposium on Parallel & Distributed Processing, May 2009.","DOI":"10.1109\/IPDPS.2009.5161225"},{"key":"1506_CR13","doi-asserted-by":"crossref","unstructured":"Tuan V M, Amano H. A mapping method for multi-process execution on dynamically reconfigurable processors. In Proc. the International Conference on Field-Programmable Technology, December 2007, pp.357-360.","DOI":"10.1109\/FPT.2007.4439285"},{"key":"1506_CR14","doi-asserted-by":"crossref","unstructured":"Liu S, Chen T, Li L et al. FreeRider: Non-local adaptive network-on-chip routing with packet-carried propagation of congestion information. IEEE Transactions on Parallel and Distributed Systems, 2014. (to be appeared).","DOI":"10.1109\/TPDS.2014.2345065"},{"key":"1506_CR15","doi-asserted-by":"crossref","unstructured":"Schleupen K, Lelaich S, Mannion R et al. Dynamic partial FPGA reconfiguration in a prototype microprocessor system. In Proc. the International Conference on Field Programmable Logic and Applications, August 2007, pp.533-536.","DOI":"10.1109\/FPL.2007.4380710"},{"issue":"3","key":"1506_CR16","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/MM.2006.49","volume":"26","author":"M Kistler","year":"2006","unstructured":"Kistler M, Perrone M, Petrini F. Cell multiprocessor communication network: Built for speed. IEEE Micro, 2006, 26(3):10-23.","journal-title":"IEEE Micro"},{"issue":"5","key":"1506_CR17","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1109\/MM.2007.4378783","volume":"27","author":"Y Hoskote","year":"2007","unstructured":"Hoskote Y, Vangal S, Singh A et al. A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro, 2007, 27(5):51-61.","journal-title":"IEEE Micro"},{"key":"1506_CR18","doi-asserted-by":"crossref","unstructured":"Samuelsson H, Kumar S. Ring road NoC architecture. In Proc. Norchip Conference, November 2004, pp.16-19.","DOI":"10.1109\/NORCHP.2004.1423811"},{"issue":"1","key":"1506_CR19","doi-asserted-by":"crossref","first-page":"2","DOI":"10.1016\/j.parco.2006.10.001","volume":"33","author":"JW Kwark","year":"2007","unstructured":"Kwark J W, Jhon C S. Torus ring: Improving performance of interconnection network by modifying hierarchical ring. Parallel Computing, 2007, 33(1):2-20.","journal-title":"Parallel Computing"},{"key":"1506_CR20","doi-asserted-by":"crossref","unstructured":"Bourduas S, Zilic Z. A hybrid ring\/mesh interconnect for network-on-chip using hierarchical rings for global routing. In Proc. the 1st International Symposium on Networks-on-Chip, May 2007, pp.195-204.","DOI":"10.1109\/NOCS.2007.3"},{"key":"1506_CR21","doi-asserted-by":"crossref","unstructured":"Madsen J, Stidsen T, Kjaerulf P et al. Multi-objective design space exploration of embedded system platforms. In Proc. the IFIP TC 10 Working Conference on Distributed and Parallel Embedded Systems, October 2006, pp.185-194.","DOI":"10.1007\/978-0-387-39362-9_20"},{"key":"1506_CR22","doi-asserted-by":"crossref","unstructured":"Kumar A, Hansson A, Huisken J et al. An FPGA design flow for reconfigurable network-based multi-processor systems on chip. In Proc. the Design, Automation & Test in Europe Conference & Exhibition, April 2007.","DOI":"10.1109\/DATE.2007.364577"},{"key":"1506_CR23","doi-asserted-by":"crossref","unstructured":"Dittmann F, Gotz M, Rettberg A. Model and methodology for the synthesis of heterogeneous and partially reconfigurable systems. In Proc. IEEE International Parallel and Distributed Processing Symposium, March 2007.","DOI":"10.1109\/IPDPS.2007.370388"},{"key":"1506_CR24","doi-asserted-by":"crossref","unstructured":"Faruque M, Ebi T, Henkel J. Runtime adaptive on-chip communication scheme. In Proc. IEEE\/ACM International Conference on Computer-Aided Design, November 2007, pp.26-31.","DOI":"10.1109\/ICCAD.2007.4397239"},{"key":"1506_CR25","doi-asserted-by":"crossref","unstructured":"Zheng L, Cai J, Du M et al. Hybrid communication reconfigurable network on chip for MPSoC. In Proc. the 24th IEEE International Conference on Advanced Information Networking and Applications, April 2010, pp.356-361.","DOI":"10.1109\/AINA.2010.108"},{"key":"1506_CR26","doi-asserted-by":"crossref","unstructured":"Gohringer D, Becker J. High performance reconfigurable multi-processor-based computing on FPGAs. In Proc. IEEE International Symposium on Parallel & Distributed Processing, Workshops and PhD Forum, April 2010.","DOI":"10.1109\/IPDPSW.2010.5470800"},{"key":"1506_CR27","doi-asserted-by":"crossref","unstructured":"Wang C, Zhang J, Zhou X et al. A flexible high speed star network based on peer to peer links on FPGA. In Proc. the 9th IEEE International Symposium on Parallel and Distributed Processing with Applications, May 2011, pp.107-112.","DOI":"10.1109\/ISPA.2011.40"},{"key":"1506_CR28","doi-asserted-by":"crossref","unstructured":"Wang C, Li X, Zhou X et al. CRAIS: A crossbar based adaptive interconnection scheme. In Proc. the 8th International Symposium on Recon_gurable Computing: Architectures, Tools and Applications, March 2012, pp.379-384.","DOI":"10.1007\/978-3-642-28365-9_35"},{"key":"1506_CR29","doi-asserted-by":"crossref","unstructured":"Daya B, Chen C, Subramanian S et al. SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering. In Proc. the 41st ACM\/IEEE International Symposium on Computer Architecture, June 2014, pp.25-36.","DOI":"10.1109\/ISCA.2014.6853232"},{"issue":"3","key":"1506_CR30","doi-asserted-by":"crossref","first-page":"1404","DOI":"10.1007\/s11227-012-0810-x","volume":"62","author":"C Wang","year":"2012","unstructured":"Wang C, Li X, Zhang J et al. A star network approach in heterogeneous multiprocessors system on chip. The Journal of Supercomputing, 2012, 62(3):1404-1424.","journal-title":"The Journal of Supercomputing"},{"key":"1506_CR31","doi-asserted-by":"crossref","unstructured":"Freitas H, Carvalho M, Amaral A et al. Reconfigurable crossbar switch architecture for network processors. In Proc. IEEE International Symposium on Circuits and Systems, May 2006.","DOI":"10.1109\/ISCAS.2006.1693516"},{"key":"1506_CR32","doi-asserted-by":"crossref","unstructured":"Young S, Alfke P, Fewer C et al. A high I\/O reconfigurable crossbar switch. In Proc. the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, April 2003, pp.3-10.","DOI":"10.1109\/FPGA.2003.1227236"},{"key":"1506_CR33","unstructured":"Rosinger H P. Connecting customized IP to the MicroBlaze soft processor using the Fast Simplex Link (FSL) channel. XILINXr XAPP529, May 2004. http:\/\/www.xilinx.com\/support\/documentation\/applicationnotes\/xapp529.pdf , Dec. 2014."}],"container-title":["Journal of Computer Science and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-015-1506-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11390-015-1506-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11390-015-1506-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,17]],"date-time":"2025-05-17T04:45:38Z","timestamp":1747457138000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11390-015-1506-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":33,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2015,1]]}},"alternative-id":["1506"],"URL":"https:\/\/doi.org\/10.1007\/s11390-015-1506-5","relation":{},"ISSN":["1000-9000","1860-4749"],"issn-type":[{"type":"print","value":"1000-9000"},{"type":"electronic","value":"1860-4749"}],"subject":[],"published":{"date-parts":[[2015,1]]}}}