{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T15:42:26Z","timestamp":1758123746274,"version":"3.38.0"},"reference-count":35,"publisher":"Springer Science and Business Media LLC","issue":"9","license":[{"start":{"date-parts":[[2011,8,3]],"date-time":"2011-08-03T00:00:00Z","timestamp":1312329600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sci. China Inf. Sci."],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1007\/s11432-011-4366-9","type":"journal-article","created":{"date-parts":[[2011,8,2]],"date-time":"2011-08-02T13:22:00Z","timestamp":1312291320000},"page":"1784-1796","source":"Crossref","is-referenced-by-count":9,"title":["Efficient multi-level fault simulation of HW\/SW systems for structural faults"],"prefix":"10.1007","volume":"54","author":[{"given":"Rafal","family":"Baranowski","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefano","family":"Di Carlo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nadereh","family":"Hatami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael E.","family":"Imhof","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael A.","family":"Kochte","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Prinetto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian G.","family":"Zoellin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2011,8,3]]},"reference":[{"key":"4366_CR1","doi-asserted-by":"crossref","first-page":"128","DOI":"10.1109\/MDT.2006.52","volume":"23","author":"K. Roy","year":"2006","unstructured":"Roy K, Mak T, Cheng K. Test consideration for nanometer-scale CMOS circuits. IEEE Des Test Comput, 2006, 23: 128\u2013136","journal-title":"IEEE Des Test Comput"},{"key":"4366_CR2","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/MM.2005.110","volume":"25","author":"S. Borkar","year":"2005","unstructured":"Borkar S. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro, 2005, 25: 10\u201316","journal-title":"IEEE Micro"},{"key":"4366_CR3","doi-asserted-by":"crossref","first-page":"406","DOI":"10.1109\/TR.2004.833310","volume":"53","author":"N. Wattanapongsakorn","year":"2004","unstructured":"Wattanapongsakorn N, Levitan S P. Reliability optimization models for embedded systems with multiple applications. IEEE Trans Reliab, 2004, 53: 406\u2013416","journal-title":"IEEE Trans Reliab"},{"key":"4366_CR4","doi-asserted-by":"crossref","unstructured":"Cano J, Rios D. Reliability forecasting in complex hardware\/software systems. In: Proceedings of the First International Conference on Availability, Reliability and Security, Vienna, Austria, 2006. 300\u2013304","DOI":"10.1109\/ARES.2006.106"},{"key":"4366_CR5","doi-asserted-by":"crossref","unstructured":"Leveugle R, Cimonnet D, Ammari A. System-level dependability analysis with RT-level fault injection accuracy. In: Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, Cannes, France, 2004. 451\u2013458","DOI":"10.1109\/DFTVS.2004.1347870"},{"key":"4366_CR6","doi-asserted-by":"crossref","first-page":"559","DOI":"10.1023\/A:1025178014797","volume":"19","author":"R. Leveugle","year":"2003","unstructured":"Leveugle R, Hadjiat K. Multi-level fault injections in VHDL descriptions: Alternative approaches and experiments. J Electron Test, 2003, 19: 559\u2013575","journal-title":"J Electron Test"},{"key":"4366_CR7","doi-asserted-by":"crossref","unstructured":"Jhumka A, Klaus S, Huss S A. A dependability-driven system-level design approach for embedded systems. In: Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, 2005. 372\u2013377","DOI":"10.1109\/DATE.2005.10"},{"key":"4366_CR8","doi-asserted-by":"crossref","unstructured":"Rothbart K, Neffe U, Steger C, et al. High level fault injection for attack simulation in smart cards. In: Proceedings of the 13th Asian Test Symposium, Kenting, Taiwan, China, 2004. 118\u2013121","DOI":"10.1109\/ATS.2004.48"},{"key":"4366_CR9","doi-asserted-by":"crossref","first-page":"1241","DOI":"10.1109\/43.466340","volume":"14","author":"W. Meyer","year":"1995","unstructured":"Meyer W, Camposano R. Active timing multilevel fault-simulation with switch-level accuracy. IEEE Trans CAD Integr Circ Syst, 1995, 14: 1241\u20131256","journal-title":"IEEE Trans CAD Integr Circ Syst"},{"key":"4366_CR10","doi-asserted-by":"crossref","unstructured":"Santos M B, Teixeira J P. Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL. In: Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, 1999. 549","DOI":"10.1145\/307418.307562"},{"key":"4366_CR11","doi-asserted-by":"crossref","first-page":"575","DOI":"10.1007\/s10677-004-4247-z","volume":"20","author":"Z. Navabi","year":"2004","unstructured":"Navabi Z, Mirkhani S, Lavasani M, et al. Using RT level component descriptions for single stuck-at hierarchical fault simulation. J Electron Test, 2004, 20: 575\u2013589","journal-title":"J Electron Test"},{"key":"4366_CR12","doi-asserted-by":"crossref","first-page":"1005","DOI":"10.1109\/43.7799","volume":"7","author":"S. Gai","year":"1988","unstructured":"Gai S, Montessoro P L, Somenzi F. MOZART: a concurrent multilevel simulator. IEEE Trans CAD Integr Circ Syst, 1988, 7: 1005\u20131016","journal-title":"IEEE Trans CAD Integr Circ Syst"},{"key":"4366_CR13","doi-asserted-by":"crossref","unstructured":"Lentz K P, Homer J B. Handling behavioral components in multi-level concurrent fault simulation. In: Proceedings of the 33th Annual Simulation Symposium, Washington DC, USA, 2000. 149\u2013156","DOI":"10.1109\/SIMSYM.2000.844911"},{"key":"4366_CR14","doi-asserted-by":"crossref","unstructured":"Hsiao M S, Patel J H. A new architectural-level fault simulation using propagation prediction of grouped fault-effects. In: Proceedings of International Conference on Computer Design, Austin, TX, USA, 1995. 628","DOI":"10.1109\/ICCD.1995.528934"},{"key":"4366_CR15","doi-asserted-by":"crossref","unstructured":"Sinanoglu O, Orailoglu A. RT-level fault simulation based on symbolic propagation. In: Proceedings of the 19th IEEE VLSI Test Symposium, Marina Del Rey, CA, USA, 2001. 240\u2013245","DOI":"10.1109\/VTS.2001.923445"},{"key":"4366_CR16","doi-asserted-by":"crossref","first-page":"270","DOI":"10.1016\/j.micpro.2008.03.013","volume":"32","author":"S. Misera","year":"2008","unstructured":"Misera S, Vierhaus H T, Sieber A. Simulated fault injections and their acceleration in SystemC. Microproc Microsyst Embed Hardware Des, 2008, 32: 270\u2013278","journal-title":"Microproc Microsyst Embed Hardware Des"},{"key":"4366_CR17","doi-asserted-by":"crossref","unstructured":"Beltrame G, Bolchini C, Miele A. Multi-level fault modeling for transaction-level specifications. In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI, Boston Area, MA, USA, 2009. 87\u201392","DOI":"10.1145\/1531542.1531565"},{"volume-title":"Transaction-Level Modeling with SystemC-TLM Concepts and Applications for Embedded Systems","year":"2005","key":"4366_CR18","unstructured":"Ghenassia F, ed. Transaction-Level Modeling with SystemC-TLM Concepts and Applications for Embedded Systems. NewYork: Springer, 2005"},{"key":"4366_CR19","doi-asserted-by":"crossref","first-page":"1517","DOI":"10.1109\/TCAD.2009.2026356","volume":"28","author":"A. Gerstlauer","year":"2009","unstructured":"Gerstlauer A, Haubelt C, Pimentel A, et al. Electronic system-level synthesis methodologies. IEEE Trans CAD Integr Circ Syst, 2009, 28: 1517\u20131530","journal-title":"IEEE Trans CAD Integr Circ Syst"},{"key":"4366_CR20","volume-title":"Advances in Design and Specification Languages for Embedded Systems","author":"M. Radetzki","year":"2007","unstructured":"Radetzki M. Object-oriented transaction level modelling. In: Huss S, ed. Advances in Design and Specification Languages for Embedded Systems. New York: Springer, 2007"},{"key":"4366_CR21","doi-asserted-by":"crossref","unstructured":"Hwang Y, Abdi S, Gajski D. Cycle-approximate retargetable performance estimation at the transaction level. In: Proceedings of Design, Automation and Test in Europe, Munich, Germany, 2008. 3\u20138","DOI":"10.1109\/DATE.2008.4484651"},{"key":"4366_CR22","doi-asserted-by":"crossref","unstructured":"Cheema M, Hammami O. Introducing energy and area estimation in HW\/SW design flow based on transaction level modeling. In: Proceedings of International Conference on Microelectronics, Dhahran, Saudi Arabia, 2006. 182\u2013185","DOI":"10.1109\/ICM.2006.373297"},{"key":"4366_CR23","unstructured":"Open SystemC Initiative (OSCI) TLM Working Group. Transaction level modeling standard 2 (OSCI TLM 2), June 2008. www.systemc.org"},{"key":"4366_CR24","unstructured":"Cai L, Gajski D. Transaction level modeling: an overview. In: Proceedings of International Conference on Hardware\/Software Codesign and System Synthesis, Newport Beach, CA, USA, 2003. 19\u201324"},{"key":"4366_CR25","unstructured":"Mukherjee S S, Emer J S, Reinhardt S K. The soft error problem: An architectural perspective. In: Proceedings of the 11th International Conference on High-Performance Computer Architecture, San Francisco, CA, USA, 2005. 243\u2013247"},{"key":"4366_CR26","doi-asserted-by":"crossref","first-page":"512","DOI":"10.1109\/TC.2004.1275294","volume":"53","author":"M. Hiller","year":"2004","unstructured":"Hiller M, Jhumka A, Suri N. EPIC: Profiling the propagation and effect of data errors in software. IEEE Trans Comput, 2004, 53: 512\u2013530","journal-title":"IEEE Trans Comput"},{"key":"4366_CR27","doi-asserted-by":"crossref","unstructured":"Radetzki M, Khaligh R S. Accuracy-adaptive simulation of transaction level models. In: Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, 2008. 788\u2013791","DOI":"10.1145\/1403375.1403566"},{"key":"4366_CR28","doi-asserted-by":"crossref","unstructured":"Kochte M A, Schaal M, Wunderlich H J, et al. Efficient fault simulation on many-core processors. In: Proceedings of ACM\/IEEE Design Automation Conference, Anaheim, CA, USA, 2010","DOI":"10.1145\/1837274.1837369"},{"key":"4366_CR29","unstructured":"Ulrich E, Baker T. The concurrent simulation of nearly identical digital networks. In: Proceedings of the 10th Workshop on Design Automation, New Delhi, India, 1973. 145\u2013150"},{"key":"4366_CR30","unstructured":"Lee H K, Ha D S. Hope: An efficient parallel fault simulator for synchronous sequential circuits. In: Proceedings of ACM\/IEEE Design Automation Conference, Anaheim, CA, USA, 1992. 336\u2013340"},{"key":"4366_CR31","volume-title":"Self-checking and Fault-tolerant Digital Design","author":"P. Lala","year":"2001","unstructured":"Lala P. Self-checking and Fault-tolerant Digital Design. San Fransisco: Morgan Kaufmann, 2001"},{"key":"4366_CR32","doi-asserted-by":"crossref","unstructured":"da Silva Farina A, Prieto S. On the use of dynamic binary instrumentation to perform faults injection in transaction level models. In: Proceedings of the 4th International Conference on Dependability of Computer Systems, Brun\u00f3w, Poland, 2009. 237\u2013244","DOI":"10.1109\/DepCoS-RELCOMEX.2009.30"},{"key":"4366_CR33","doi-asserted-by":"crossref","first-page":"50","DOI":"10.1109\/MDT.2009.135","volume":"26","author":"D. Lee","year":"2009","unstructured":"Lee D, Na J. A novel simulation fault injection method for dependability analysis. IEEE Des Test Comput, 2009, 26: 50\u201361","journal-title":"IEEE Des Test Comput"},{"key":"4366_CR34","first-page":"133","volume-title":"Models in Hardware Testing","author":"H. Wunderlich","year":"2009","unstructured":"Wunderlich H, Holst S. Generalized fault modeling for logic diagnosis. In: Models in Hardware Testing. New York: Springer, 2009. 133\u2013155"},{"key":"4366_CR35","doi-asserted-by":"crossref","first-page":"329","DOI":"10.1109\/TVLSI.2008.2010045","volume":"18","author":"G. Natale Di","year":"2010","unstructured":"Di Natale G, Doulcier M, Flottes M L, et al. Self-test techniques for crypto-devices. IEEE Trans VLSI Syst, 2010, 18: 329\u2013333","journal-title":"IEEE Trans VLSI Syst"}],"container-title":["Science China Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-011-4366-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11432-011-4366-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-011-4366-9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,8]],"date-time":"2025-03-08T01:52:22Z","timestamp":1741398742000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11432-011-4366-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,8,3]]},"references-count":35,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2011,9]]}},"alternative-id":["4366"],"URL":"https:\/\/doi.org\/10.1007\/s11432-011-4366-9","relation":{},"ISSN":["1674-733X","1869-1919"],"issn-type":[{"type":"print","value":"1674-733X"},{"type":"electronic","value":"1869-1919"}],"subject":[],"published":{"date-parts":[[2011,8,3]]}}}