{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T11:25:11Z","timestamp":1648639511446},"reference-count":30,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2013,1,24]],"date-time":"2013-01-24T00:00:00Z","timestamp":1358985600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sci. China Inf. Sci."],"published-print":{"date-parts":[[2013,6]]},"DOI":"10.1007\/s11432-013-4812-y","type":"journal-article","created":{"date-parts":[[2013,1,23]],"date-time":"2013-01-23T23:48:51Z","timestamp":1358984931000},"page":"1-16","source":"Crossref","is-referenced-by-count":1,"title":["ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor"],"prefix":"10.1007","volume":"56","author":[{"given":"LeiBo","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wen","family":"Jia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"ShouYi","family":"Yin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dong","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"GuanYi","family":"Sun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eugene","family":"Tang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"ShaoJun","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2013,1,24]]},"reference":[{"key":"4812_CR1","doi-asserted-by":"crossref","first-page":"193","DOI":"10.1049\/ip-cdt:20045086","volume":"152","author":"T J Todman","year":"2005","unstructured":"Todman T J, Constantinides G A, Wilton S J E, et al. Reconfigurable computing: architectures and design methods. IEE Proc-Comput Digit Tech, 2005, 152: 193\u2013207","journal-title":"IEE Proc-Comput Digit Tech"},{"key":"4812_CR2","doi-asserted-by":"crossref","first-page":"465","DOI":"10.1109\/12.859540","volume":"49","author":"H Singh","year":"2000","unstructured":"Singh H, Lee M-H, Lu G, et al. MorphoSys: an integrated reconfigurable system for data-parallel and computationintensive applications. IEEE Trans Comput, 2000, 49: 465\u2013481","journal-title":"IEEE Trans Comput"},{"key":"4812_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1007\/978-3-540-45234-8_7","volume-title":"Field-Programmable Logic and Applications","author":"B Mei","year":"2003","unstructured":"Mei B, Vernalde S, Verkest D, et al. ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In: Brebner G, Woods R, eds. Field-Programmable Logic and Applications, Lecture Notes in Computer Science, Vol. 2778. Berlin: Springer, 2003. 61\u201370"},{"key":"4812_CR4","doi-asserted-by":"crossref","first-page":"167","DOI":"10.1023\/A:1024499601571","volume":"26","author":"V Baumgarte","year":"2003","unstructured":"Baumgarte V, Ehlers G, May F, et al. PACT XPP-a self-reconfigurable data processing architecture. J Supercomput, 2003, 26: 167\u2013184","journal-title":"J Supercomput"},{"key":"4812_CR5","doi-asserted-by":"crossref","first-page":"2011","DOI":"10.1109\/ISCAS.2010.5537147","volume-title":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris","author":"M Zhu","year":"2010","unstructured":"Zhu M, Liu L, Yin S, et al. A reconfigurable multi-processor SoC for media applications. In: Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, 2010. 2011\u20132014"},{"key":"4812_CR6","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/FPL.2006.311212","volume-title":"Proceedings of 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid","author":"W Fu","year":"2006","unstructured":"Fu W, Compton K. A simulation platform for reconfigurable computing research. In: Proceedings of 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, 2006. 1\u20137"},{"key":"4812_CR7","first-page":"17","volume":"1","author":"P A Hsiung","year":"2008","unstructured":"Hsiung P A, Lin C S, Liao C F. Perfecto: a systemc-based design-space exploration framework for dynamically reconfigurable architectures. ACM T Reconfigurable Technol Syst, 2008, 1: 17","journal-title":"ACM T Reconfigurable Technol Syst"},{"key":"4812_CR8","first-page":"1","volume-title":"Proceedings of 21st International Parallel and Distributed Processing Symposium (IPDPS 2007), Long Beach","author":"A V Brito","year":"2007","unstructured":"Brito A V, Kuehnle M, Melcher E U K, et al. A general purpose partially reconfigurable processor simulator (PReProS). In: Proceedings of 21st International Parallel and Distributed Processing Symposium (IPDPS 2007), Long Beach, 2007. 1\u20137"},{"key":"4812_CR9","doi-asserted-by":"crossref","first-page":"434","DOI":"10.1109\/ISVLSI.2006.23","volume-title":"Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI), Karlsruhe","author":"A V Brito De","year":"2006","unstructured":"De Brito A V, Melcher E U K, Rosas W. An open-source tool for simulation of partially reconfigurable systems using SystemC. In: Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI), Karlsruhe, 2006. 434\u2013435"},{"key":"4812_CR10","unstructured":"PACT Inc. The XPP White Paper-release 2.1. http:\/\/www.pactxpp.com"},{"key":"4812_CR11","first-page":"34","volume-title":"Proceedings of 6th IEEE Symposium on Application Specific Processors (SASP), Anaheim","author":"C Morra","year":"2008","unstructured":"Morra C, Cardoso J M P, Bispo J, et al. Retargeting, evaluating, and generating reconfigurable array-based architectures. In: Proceedings of 6th IEEE Symposium on Application Specific Processors (SASP), Anaheim, 2008. 34\u201341"},{"key":"4812_CR12","doi-asserted-by":"crossref","first-page":"3202","DOI":"10.1587\/transinf.E93.D.3202","volume":"E93-D","author":"M Zhu","year":"2010","unstructured":"Zhu M, Liu L, Yin S, et al. A cycle-accurate simulator for a reconfigurable multi-media system. IEICE Trans Inf Syst, 2010, E93-D: 3202\u20133210","journal-title":"IEICE Trans Inf Syst"},{"key":"4812_CR13","unstructured":"Open SystemC Initiative (OSCI). OSCI TLM-2.0 USER MANUAL. http:\/\/www.cl.cam.ac.uk\/research\/srg\/han\/ACSP35\/documents\/TLM_2_0_usermanual.pdf"},{"key":"4812_CR14","unstructured":"Synopsys Inc. Simulation tool chain Synopsys VCS. http:\/\/www.synopsys.com\/tools\/verification\/functionalverification\/pages\/vcs.aspx"},{"key":"4812_CR15","unstructured":"Bellard F. QEMU: open source processor emulator. http:\/\/www.qemu.org"},{"key":"4812_CR16","unstructured":"ARM Inc. Multi-layer AHB technical overview v2.0. http:\/\/infocenter.arm.com\/help\/index.jsp"},{"key":"4812_CR17","unstructured":"Synopsys Inc. DesignWare DW ahb icm Databook. http:\/\/www.synopsys.com\/dw\/ipdir.php?c=DW_ahb_icm"},{"key":"4812_CR18","doi-asserted-by":"crossref","first-page":"1284","DOI":"10.1587\/transele.E92.C.1284","volume":"E92-C","author":"C Yin","year":"2009","unstructured":"Yin C, Yin S, Liu L, et al. Compiler framework for reconfigurable computing architecture. IEICE Trans Electron, 2009, E92-C: 1284\u20131290","journal-title":"IEICE Trans Electron"},{"key":"4812_CR19","volume-title":"An Overview of the SUIF2 Compiler Infrastructure. Technical Report","author":"G Aigner","year":"2000","unstructured":"Aigner G, Diwan A, Heine D L, et al. An Overview of the SUIF2 Compiler Infrastructure. Technical Report. Computer Systems Laboratory, Stanford University, 2000"},{"key":"4812_CR20","volume-title":"An introduction to MachineSUIF and its portable libraries for analysis and optimization","author":"M D Smith","year":"2002","unstructured":"Smith M D, Holloway G. An introduction to MachineSUIF and its portable libraries for analysis and optimization. The MachineSUIF Documentation Set. Harvard University, 2002"},{"key":"4812_CR21","first-page":"834","volume":"28","author":"M Ling","year":"2005","unstructured":"Ling M, Yang J, Zhang Y. SDRAM power model and instruction FIFO optimization. Chin J Electron Devices, 2005, 28: 834\u2013838","journal-title":"Chin J Electron Devices"},{"key":"4812_CR22","unstructured":"Google Inc. Android OS: an light-weighted OS for mobile device. http:\/\/www.android.com"},{"key":"4812_CR23","doi-asserted-by":"crossref","first-page":"221","DOI":"10.1109\/PRIMEASIA.2010.5604920","volume-title":"Proceedings of the 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Shanghai","author":"W Jia","year":"2010","unstructured":"Jia W, Liu L, Yin S, et al. A fast complete deblocking filter on a coarse-grained reconfigurable processor supporting H.264 high profile decoding. In: Proceedings of the 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Shanghai, 2010. 221\u2013224"},{"key":"4812_CR24","doi-asserted-by":"crossref","first-page":"467","DOI":"10.1109\/FPL.2007.4380691","volume-title":"Proceedings of 2007 International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam","author":"M K A Ganesan","year":"2007","unstructured":"Ganesan M K A, Singh S, May F, et al. H.264 decoder at HD resolution on a coarse grain dynamically reconfigurable architecture. In: Proceedings of 2007 International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam, 2007. 467\u2013471"},{"key":"4812_CR25","first-page":"362-I","volume":"I","author":"K Chang","year":"2008","unstructured":"Chang K, Choi K. Mapping control intensive kernels onto coarse-grained reconfigurable array architecture. In: Proceedings of the 5th International SoC Design Conference (ISOCC), Busan, 2008. I:362-I: 365","journal-title":"Proceedings of the 5th International SoC Design Conference (ISOCC), Busan"},{"key":"4812_CR26","first-page":"177","volume-title":"Proceedings of Design, Automation and Test in Europe (DATE), Nice Acropolis","author":"C Arbelo","year":"2007","unstructured":"Arbelo C, Kanstein A, L\u00f2pez S, et al. Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264\/AVC deblocking filter. In: Proceedings of Design, Automation and Test in Europe (DATE), Nice Acropolis, 2007. 177\u2013182"},{"key":"4812_CR27","unstructured":"Simplight Nanoelectronics Inc. Multi-threaded processor. http:\/\/www.simplnano.com\/Info_Product.asp?id=180"},{"key":"4812_CR28","unstructured":"Simplight Nanoelectronics Inc. Key features of SLM110. http:\/\/www.simplnano.com\/Info_Product.asp?id=174"},{"key":"4812_CR29","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1109\/2.982918","volume":"35","author":"J Emer","year":"2002","unstructured":"Emer J, Ahuja P, Borch E, et al. Asim: a performance model framework. Comput, 2002, 35: 68\u201376","journal-title":"Comput"},{"key":"4812_CR30","doi-asserted-by":"crossref","first-page":"249","DOI":"10.1109\/MICRO.2007.36","volume-title":"Proceedings of the 40th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), Chicago","author":"D Chiou","year":"2007","unstructured":"Chiou D, Sunwoo D, Kim J, et al. FPGA-accelerated simulation technologies (FAST): fast, full-system, cycle-accurate simulators. In: Proceedings of the 40th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), Chicago, 2007. 249\u2013261"}],"container-title":["Science China Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-013-4812-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11432-013-4812-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-013-4812-y","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T15:37:51Z","timestamp":1559403471000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11432-013-4812-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,1,24]]},"references-count":30,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2013,6]]}},"alternative-id":["4812"],"URL":"https:\/\/doi.org\/10.1007\/s11432-013-4812-y","relation":{},"ISSN":["1674-733X","1869-1919"],"issn-type":[{"value":"1674-733X","type":"print"},{"value":"1869-1919","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,1,24]]}}}