{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,1,13]],"date-time":"2023-01-13T10:15:13Z","timestamp":1673604913648},"reference-count":32,"publisher":"Springer Science and Business Media LLC","issue":"12","license":[{"start":{"date-parts":[[2015,6,15]],"date-time":"2015-06-15T00:00:00Z","timestamp":1434326400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Sci. China Inf. Sci."],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1007\/s11432-015-5352-4","type":"journal-article","created":{"date-parts":[[2015,6,15]],"date-time":"2015-06-15T15:15:30Z","timestamp":1434381330000},"page":"1-14","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Reducing DRAM refreshing in an error correction manner"],"prefix":"10.1007","volume":"58","author":[{"given":"DanFeng","family":"Zhu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rui","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"YanJiang","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"DePei","family":"Qian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2015,6,15]]},"reference":[{"key":"5352_CR1","volume-title":"Flash Memory Summit","author":"JH Yoon","year":"2013","unstructured":"Yoon JH, Hunter HC, Tressler GA. Flash & DRAM Si scaling challenges, emerging non-volatile memory technology enablement. In: Flash Memory Summit, 2013"},{"key":"5352_CR2","volume-title":"VLSI Technology Short Course","author":"SY Cha","year":"2011","unstructured":"Cha SY. DRAM and future commodity memories. VLSI Technology Short Course, 2011"},{"key":"5352_CR3","doi-asserted-by":"crossref","first-page":"846","DOI":"10.1109\/LED.2009.2023248","volume":"30","author":"K Kim","year":"2009","unstructured":"Kim K, Lee J. A new investigation of data retention time in truly nanoscaled DRAMs. IEEE Electron Dev Lett, 2009, 30: 846\u2013848","journal-title":"IEEE Electron Dev Lett"},{"key":"5352_CR4","first-page":"361","volume-title":"Proceedings of the 41st International Symposium on Computer Architecture (ISCA), Minneapolis","author":"Y Kim","year":"2014","unstructured":"Kim Y, Daly R, Kim J, et al. Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors. In: Proceedings of the 41st International Symposium on Computer Architecture (ISCA), Minneapolis, 2014. 361\u2013372"},{"key":"5352_CR5","first-page":"384","volume-title":"Proceedings of the 17th IEEE VLSI Test Symposium, Dana Point","author":"S Hellebrand","year":"1999","unstructured":"Hellebrand S, Wunderlich H, Ivaniuk A, et al. Error detecting refreshment for embedded DRAMs. In: Proceedings of the 17th IEEE VLSI Test Symposium, Dana Point, 1999. 384\u2013390"},{"key":"5352_CR6","doi-asserted-by":"crossref","first-page":"1006","DOI":"10.1109\/TVLSI.2003.817524","volume":"11","author":"J P M Kim","year":"2003","unstructured":"Kim J, Papaefthymiou M. Block-based multiperiod dynamic memory design for low data-retention power. IEEE Trans Very Large Scale Integr Syst, 2003, 11: 1006\u20131018","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"5352_CR7","first-page":"193","volume-title":"Proceedings of the 14th ASIC\/SOC Conference, Arlington","author":"J Kim","year":"2001","unstructured":"Kim J, Papaefthymiou M. Block-based multi-period refresh for energy efficient dynamic memory. In: Proceedings of the 14th ASIC\/SOC Conference, Arlington, 2001. 193\u2013197"},{"key":"5352_CR8","first-page":"82","volume-title":"Proceedings of International Symposium on Low Power Electronics and Design, Monterey","author":"T Ohsawa","year":"1998","unstructured":"Ohsawa T, Kai K, Murakami K. Optimizing the DRAM refreshing count for merged DRAM\/logic LSIs. In: Proceedings of International Symposium on Low Power Electronics and Design, Monterey, 1998. 82\u201387"},{"key":"5352_CR9","first-page":"311","volume-title":"Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Albuquerque","author":"Y Katayama","year":"1999","unstructured":"Katayama Y, Stuckey EJ, Morioka S, et al. Fault-tolerant refreshing power reduction of drams for quasi-nonvolatile data retention. In: Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Albuquerque, 1999. 311\u2013318"},{"key":"5352_CR10","first-page":"134","volume-title":"Proceedings of the 40th International Symposium on Microarchitecture, Chicago","author":"M Ghosh","year":"2007","unstructured":"Ghosh M, Lee HS. Smart refreshing: an enhanced memory controller design for reducing energy in conventional and 3d die-stacked drams. In: Proceedings of the 40th International Symposium on Microarchitecture, Chicago, 2007. 134\u2013145"},{"key":"5352_CR11","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1109\/MM.2008.93","volume":"28","author":"PG Emma","year":"2008","unstructured":"Emma PG, Reohr WR, Meterelliyoz M. Rethinking refreshing: increasing availability and reducing power in DRAM for cache applications. IEEE Micro, 2008, 28: 47\u201356","journal-title":"IEEE Micro"},{"key":"5352_CR12","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1145\/1816038.1815973","volume":"03","author":"C Wilkerson","year":"2010","unstructured":"Wilkerson C, Alameldeen AR, Chishti Z, et al. Reducing cache power with low-cost, multi-bit error correcting codes. ACM SIGARCH Comput Architect News, 2010, 03: 83\u201393","journal-title":"ACM SIGARCH Comput Architect News"},{"key":"5352_CR13","first-page":"155","volume-title":"Proceedings of International Symposium on High Performance Computer Architecture, Austin","author":"R Venkatesan","year":"2006","unstructured":"Venkatesan R, Herr S, Rotenberg E. Retention-aware placement in dram (rapid): software methods forquasi-nonvolatiledram. In: Proceedings of International Symposium on High Performance Computer Architecture, Austin, 2006. 155\u2013165"},{"key":"5352_CR14","first-page":"1","volume-title":"Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA), Portland","author":"J Liu","year":"2012","unstructured":"Liu J, Jaiyen B, Veras R, et al. RAIDR: retention-aware intelligent DRAM refresh. In: Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA), Portland, 2012. 1\u201312"},{"key":"5352_CR15","doi-asserted-by":"crossref","first-page":"337","DOI":"10.1145\/1669112.1669156","volume-title":"Proceedings of the 42nd IEEE\/ACM International Symposium on Microarchitecture, New York","author":"C Isen","year":"2009","unstructured":"Isen C, John L. ESKIMO: energy savings using semantic knowledge of inconsequential memory occupancy for DRAM subsystem. In: Proceedings of the 42nd IEEE\/ACM International Symposium on Microarchitecture, New York, 2009. 337\u2013346"},{"key":"5352_CR16","first-page":"213","volume-title":"ACM SIGPLAN Notices","author":"S Liu","year":"2012","unstructured":"Liu S, Pattabiraman K, Moscibroda T, et al. Flikker: saving DRAM Refresh-power through critical data partitioning. ACM SIGPLAN Notices, 2012, 39: 213\u2013224"},{"key":"5352_CR17","first-page":"147","volume-title":"Bell Syst Tech J","author":"RW Hamming","year":"1950","unstructured":"Hamming RW. Error detecting and error correcting codes. Bell Syst Tech J, 1950, 29: 147\u2013160"},{"key":"5352_CR18","first-page":"10","volume-title":"IEEE Micro","author":"C Mcnairy","year":"2005","unstructured":"Mcnairy C, Bhatia R. Montecito: a dual-core, dual-thread Itanium processor. IEEE Micro, 2005, 25: 10\u201320"},{"key":"5352_CR19","first-page":"141","volume-title":"Proceedings of the 37th International Symposium on Computer Architecture (ISCA), Saint-Malo","author":"S Schechter","year":"2010","unstructured":"Schechter S, Loh GH, Strauss K, et al. Use ECP, not ECC, for hard failures in resistive memories. In: Proceedings of the 37th International Symposium on Computer Architecture (ISCA), Saint-Malo, 2010. 141\u2013152"},{"key":"5352_CR20","first-page":"684","volume-title":"Proceedings of the 14th Annual European Symposium on Algorithms, Zurich","author":"F Bonomi","year":"2006","unstructured":"Bonomi F, Mitzenmacher M, Panigrahy R, et al. An improved construction for counting bloom filters. In: Proceedings of the 14th Annual European Symposium on Algorithms, Zurich, 2006. 684\u2013695"},{"key":"5352_CR21","first-page":"346","volume-title":"ACM Trans Model Comput Simul","author":"F Panneton","year":"2005","unstructured":"Panneton F, L\u2019Ecuyer P. On the xorshift random number generators. ACM Trans Model Comput Simul, 2005, 15: 346\u2013361"},{"key":"5352_CR22","first-page":"1","volume-title":"Comput Architect News","author":"B Beckmann","year":"2011","unstructured":"Beckmann B, Binkert N, Black G, et al. The gem5 simulator. Comput Architect News, 2011, 39: 1\u20137"},{"key":"5352_CR23","first-page":"16","volume-title":"Comput Architect Lett","author":"P Rosenfeld","year":"2011","unstructured":"Rosenfeld P, Cooper-Balis E, Jacob B. DRAMSim2: a cycle accurate memory system simulator. Comput Architect Lett, 2011, 10: 16\u201319"},{"key":"5352_CR24","first-page":"5","volume-title":"Comput Architect News","author":"JP Singh","year":"1995","unstructured":"Singh JP, Weber WD, Gupta A. SPLASH-2: stanford parallel applications for shared-memory. Comput Architect News, 1995, 20: 5\u201344"},{"key":"5352_CR25","first-page":"218","volume-title":"Proceedings of the 15th IEEE International Conference on Networks, Adelaide","author":"M Ahmadi","year":"2007","unstructured":"Ahmadi M, Wong S. A cache architecture for counting bloom filters. In: Proceedings of the 15th IEEE International Conference on Networks, Adelaide, 2007. 218\u2013223"},{"key":"5352_CR26","first-page":"1042","volume-title":"Microelectron J","author":"C Kim","year":"2007","unstructured":"Kim C, Kong B, Lee C, et al. CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control. Microelectron J, 2007, 38: 1042\u20131049"},{"key":"5352_CR27","volume-title":"Restore tracking system for DRAM.U.S. patent No 6389505","author":"PG Emma","year":"2002","unstructured":"Emma PG, Reohr WR, Wang L. Restore tracking system for DRAM.U.S. patent No 6389505, 2002"},{"key":"5352_CR28","volume-title":"U.S patent No 5890198","author":"JT Pawlowski","year":"1999","unstructured":"Pawlowski JT. Intelligent refreshing controller for dynamic memory devices. U.S patent No 5890198, 1999"},{"key":"5352_CR29","volume-title":"U.S. patent No 6094705","author":"SP Song","year":"2000","unstructured":"Song SP. Method and system for selective DRAM refreshing to reduce power consumption. U.S. patent No 6094705, 2000"},{"key":"5352_CR30","doi-asserted-by":"crossref","first-page":"72","DOI":"10.1145\/2485922.2485929","volume-title":"Proceedings of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv","author":"PJ Nair","year":"2013","unstructured":"Nair PJ, Kim DH, Qureshi MK, et al. ArchShield: architectural framework for assisting dram scaling by tolerating high error rates. In: Proceedings of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv, 2013. 72\u201383"},{"key":"5352_CR31","first-page":"115","volume-title":"Proceedings of the 43rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), Atlanta","author":"NH Seong","year":"2010","unstructured":"Seong NH, Woo DH, Srinivasan V, et al. SAFER: stuck-at-fault error recovery for memories. In: Proceedings of the 43rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), Atlanta, 2010. 115\u2013124"},{"key":"5352_CR32","first-page":"375","volume-title":"Proceedings of the 43rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), Atlanta","author":"J Stuecheli","year":"2010","unstructured":"Stuecheli J, Kaseridis D, Hunter HC, et al. Elastic refresh: techniques to mitigate refresh penalties in high density memory. In: Proceedings of the 43rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), Atlanta, 2010. 375\u2013384"}],"container-title":["Science China Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-015-5352-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11432-015-5352-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-015-5352-4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,13]],"date-time":"2022-05-13T07:23:55Z","timestamp":1652426635000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11432-015-5352-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6,15]]},"references-count":32,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2015,12]]}},"alternative-id":["5352"],"URL":"https:\/\/doi.org\/10.1007\/s11432-015-5352-4","relation":{},"ISSN":["1674-733X","1869-1919"],"issn-type":[{"value":"1674-733X","type":"print"},{"value":"1869-1919","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,6,15]]}}}