{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:05:20Z","timestamp":1759147520417},"reference-count":173,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2016,5,6]],"date-time":"2016-05-06T00:00:00Z","timestamp":1462492800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Sci. China Inf. Sci."],"published-print":{"date-parts":[[2016,6]]},"DOI":"10.1007\/s11432-016-5560-6","type":"journal-article","created":{"date-parts":[[2016,5,10]],"date-time":"2016-05-10T00:43:16Z","timestamp":1462840996000},"update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":33,"title":["Design for manufacturability and reliability in extreme-scaling VLSI"],"prefix":"10.1007","volume":"59","author":[{"given":"Bei","family":"Yu","sequence":"first","affiliation":[]},{"given":"Xiaoqing","family":"Xu","sequence":"additional","affiliation":[]},{"given":"Subhendu","family":"Roy","sequence":"additional","affiliation":[]},{"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Jiaojiao","family":"Ou","sequence":"additional","affiliation":[]},{"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,5,6]]},"reference":[{"key":"5560_CR1","doi-asserted-by":"crossref","first-page":"2","DOI":"10.1117\/12.210341","volume":"2438","author":"G E Moore","year":"1995","unstructured":"Moore G E. Lithography and the future of Moore\u2019s law. Proc SPIE, 1995, 2438: 2\u201317","journal-title":"Proc SPIE"},{"key":"5560_CR2","doi-asserted-by":"crossref","first-page":"1453","DOI":"10.1109\/TCAD.2013.2276751","volume":"32","author":"D Z Pan","year":"2013","unstructured":"Pan D Z, Yu B, Gao J-R. Design for manufacturing with emerging nanolithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2013, 32: 1453\u20131472","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR3","volume-title":"Springer","author":"B Yu","year":"2015","unstructured":"Yu B, Pan D Z. Design for Manufacturability with Advanced Lithography. Springer, 2015"},{"key":"5560_CR4","volume-title":"Springer","author":"R Reis","year":"2014","unstructured":"Reis R, Cao Y, Wirth G. Circuit Design for Reliability. Springer, 2014"},{"key":"5560_CR5","doi-asserted-by":"crossref","first-page":"50","DOI":"10.1109\/JETCAS.2011.2135470","volume":"1","author":"E Maricau","year":"2011","unstructured":"Maricau E, Gielen G. Computer-aided analog circuit design for reliability in nanometer CMOS. IEEE J Emerg Sel Top Circ Syst, 2011, 1: 50\u201358","journal-title":"IEEE J Emerg Sel Top Circ Syst"},{"issue":"1\u201324","key":"5560_CR6","first-page":"6","volume":"24","author":"A Mallik","year":"2013","unstructured":"Mallik A, Zuber P, Liu T T, et al. TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), Austin, 2013. 24: 1\u201324: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), Austin"},{"key":"5560_CR7","first-page":"9427","volume-title":"Proc SPIE","author":"L Liebmann","year":"2015","unstructured":"Liebmann L, Chu A, Gutwin P. The daunting complexity of scaling to 7nm without EUV: pushing DTCO to the extreme. Proc SPIE, 2015: 9427"},{"key":"5560_CR8","first-page":"9427","volume-title":"Proc SPIE","author":"B Chava","year":"2015","unstructured":"Chava B, Rio D, Sherazi Y, et al. Standard cell design in N7: EUV vs. immersion. Proc SPIE, 2015: 9427"},{"key":"5560_CR9","first-page":"344","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego","author":"B Taylor","year":"2007","unstructured":"Taylor B, Pileggi L. Exact combinatorial optimization methods for physical design of regular logic bricks. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego, 2007. 344\u2013349"},{"key":"5560_CR10","first-page":"954","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego","author":"W Maly","year":"2007","unstructured":"Maly W, Lin Y W, Sadowska M M. OPC-free and minimally irregular IC design style. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego, 2007. 954\u2013957"},{"key":"5560_CR11","first-page":"838","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Taipei","author":"H B Zhang","year":"2010","unstructured":"Zhang H B, Wong M D F, Chao K Y. On process-aware 1-D standard cell design. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Taipei, 2010. 838\u2013842"},{"key":"5560_CR12","first-page":"83","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego","author":"N Ryzhenko","year":"2011","unstructured":"Ryzhenko N, Burns S. Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego, 2011. 83\u201388"},{"key":"5560_CR13","doi-asserted-by":"crossref","first-page":"419","DOI":"10.1109\/TCAD.2012.2226454","volume":"32","author":"P H Wu","year":"2013","unstructured":"Wu P H, Lin M P, Chen T C, et al. 1-D cell generation with printability enhancement. IEEE Trans Comput Aided Des Integr Circ Syst, 2013, 32: 419\u2013432","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR14","first-page":"453","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama","author":"S Hougardy","year":"2013","unstructured":"Hougardy S, Nieberg T, Schneider J. BonnCell: automatic layout of leaf cells. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, 2013. 453\u2013460"},{"key":"5560_CR15","first-page":"289","volume-title":"Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh","author":"W Ye","year":"2015","unstructured":"Ye W, Yu B, Ban Y-C, et al. Standard cell layout regularity and pin access optimization considering middle-of-line. In: Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, 2015. 289\u2013294"},{"key":"5560_CR16","first-page":"9427","volume-title":"Proc SPIE","author":"X Q Xu","year":"2015","unstructured":"Xu X Q, Cline B, Yeric G, et al. A systematic framework for evaluating cell level middle-of-line (MOL) robustness for multiple patterning. Proc SPIE, 2015: 9427"},{"key":"5560_CR17","doi-asserted-by":"crossref","first-page":"699","DOI":"10.1109\/TCAD.2015.2399439","volume":"34","author":"X Q Xu","year":"2015","unstructured":"Xu X Q, Cline B, Yeric G, et al. Self-aligned double patterning aware pin access and standard cell layout cooptimization. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 699\u2013712","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR18","first-page":"27","volume-title":"Proceedings of ACM International Symposium on Physical Design (ISPD), Austin","author":"S Y Hu","year":"2007","unstructured":"Hu S Y, Hu J. Pattern sensitive placement for manufacturability. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Austin, 2007. 27\u201334"},{"key":"5560_CR19","doi-asserted-by":"crossref","first-page":"2145","DOI":"10.1109\/TCAD.2008.2006148","volume":"27","author":"T C Chen","year":"2008","unstructured":"Chen T C, Cho M, Pan D Z, et al. Metal-density-driven placement for CMP variation and routability. IEEE Trans Comput Aided Des Integr Circ Syst, 2008, 27: 2145\u20132155","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR20","first-page":"47","volume-title":"Proceedings of 19th Asia and South Pacific Design Automation Conference (ASPDAC), Singapore","author":"S Shim","year":"2014","unstructured":"Shim S, Lee Y, Shin Y. Lithographic defect aware placement using compact standard cells without inter-cell margin. In: Proceedings of 19th Asia and South Pacific Design Automation Conference (ASPDAC), Singapore, 2014. 47\u201352"},{"key":"5560_CR21","doi-asserted-by":"crossref","first-page":"1229","DOI":"10.1109\/TCAD.2010.2049041","volume":"29","author":"M Gupta","year":"2010","unstructured":"Gupta M, Jeong K, Kahng A B. Timing yield-aware color reassignment and detailed placement perturbation for bimodal cd distribution in double patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2010, 29: 1229\u20131242","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR22","first-page":"7974","volume-title":"Proc SPIE","author":"L Liebmann","year":"2011","unstructured":"Liebmann L, Pietromonaco D, Graf M. Decomposition-aware standard cell design flows to enable double-patterning technology. Proc SPIE, 2011: 7974"},{"key":"5560_CR23","volume-title":"Multi-patterning lithography aware cell placement in integrated circuit design","author":"K B Agarwal","year":"2013","unstructured":"Agarwal K B, Alpert C J, Li Z, et al. Multi-patterning lithography aware cell placement in integrated circuit design, 2013. US Patent 8-495-548"},{"key":"5560_CR24","first-page":"8684","volume-title":"Proc SPIE","author":"J-R Gao","year":"2013","unstructured":"Gao J-R, Yu B, Huang R, et al. Self-aligned double patterning friendly configuration for standard cell library considering placement. Proc SPIE, 2013: 8684"},{"key":"5560_CR25","first-page":"116","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"H T Tian","year":"2014","unstructured":"Tian H T, Du Y L, Zhang H B, et al. Triple patterning aware detailed placement with constrained pattern assignment. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2014. 116\u2013123"},{"key":"5560_CR26","first-page":"108","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"J Kuang","year":"2014","unstructured":"Kuang J, Chow W-K, Young E F Y. Triple patterning lithography aware optimization for standard cell based design. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2014. 108\u2013115"},{"key":"5560_CR27","first-page":"75","volume-title":"Proceedings of ACM International Symposium on Physical Design (ISPD), Monterey","author":"T Lin","year":"2015","unstructured":"Lin T, Chu C. TPL-aware displacement-driven detailed placement refinement with coloring constraints. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Monterey, 2015. 75\u201380"},{"key":"5560_CR28","doi-asserted-by":"crossref","first-page":"726","DOI":"10.1109\/TCAD.2015.2401571","volume":"34","author":"B Yu","year":"2015","unstructured":"Yu B, Xu X Q, Ga J-R, et al. Methodology for standard cell compliance and detailed placement for triple patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 726\u2013739","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR29","doi-asserted-by":"crossref","first-page":"778","DOI":"10.1109\/TCAD.2015.2408253","volume":"34","author":"H-A Chien","year":"2015","unstructured":"Chien H-A, Chen Y-H, Han S-Y, et al. On refining row-based detailed placement for triple patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 778\u2013793","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR30","first-page":"396","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), Austin","author":"Y B Lin","year":"2015","unstructured":"Lin Y B, Yu B, Xu B Y, et al. Triple patterning aware detailed placement toward zero cross-row middle-of-line conflict. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), Austin, 2015. 396\u2013403"},{"key":"5560_CR31","first-page":"349","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"B Yu","year":"2013","unstructured":"Yu B, Xu X Q, Gao J-R, et al. Methodology for standard cell compliance and detailed placement for triple patterning lithography. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 349\u2013356"},{"key":"5560_CR32","first-page":"186","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Macao","author":"Y B Lin","year":"2016","unstructured":"Lin Y B, Yu B, Zou Y, et al. Stitch aware detailed placement for multiple e-beam lithography. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Macao, 2016. 186\u2013191"},{"key":"5560_CR33","first-page":"249","volume-title":"Proceedings of IEEE International Conference on Computer Design (ICCD), Seoul","author":"C-Y Liu","year":"2014","unstructured":"Liu C-Y, Chang Y-W. Simultaneous EUV flare-and CMP-aware placement. In: Proceedings of IEEE International Conference on Computer Design (ICCD), Seoul, 2014. 249\u2013255"},{"key":"5560_CR34","first-page":"404","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), Austin","author":"S Shim","year":"2015","unstructured":"Shim S, Chung W, Shin Y. Defect probability of directed self-assembly lithography: fast identification and postplacement optimization. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), Austin, 2015. 404\u2013409"},{"key":"5560_CR35","first-page":"6","volume":"357","author":"Y L Du","year":"2014","unstructured":"Du Y L, Wong M D F. Optimization of standard cell based detailed placement for 16 nm FinFET process. In: Proceedings of IEEE\/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Dresden, 2014. 357: 6","journal-title":"Proceedings of IEEE\/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Dresden"},{"key":"5560_CR36","first-page":"6","volume":"25","author":"S-Y Fang","year":"2013","unstructured":"Fang S-Y, Liu I-J, Chang Y-W. Stitch-aware routing for multiple e-beam lithography. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), Austin, 2013. 25: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), Austin"},{"key":"5560_CR37","first-page":"506","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"M Cho","year":"2008","unstructured":"Cho M, Ban Y, Pan D Z. Double patterning technology friendly detailed routing. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2008. 506\u2013511"},{"key":"5560_CR38","first-page":"63","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco","author":"K Yuan","year":"2009","unstructured":"Yuan K, Lu K, and Pan D Z. Double patterning lithography friendly detailed routing with redundant via consideration. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2009. 63\u201366"},{"key":"5560_CR39","first-page":"398","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), Anaheim","author":"Y-H Lin","year":"2010","unstructured":"Lin Y-H, Li Y-L. Double patterning lithography aware gridless detailed routing with innovative conflict graph. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), Anaheim, 2010. 398\u2013403"},{"key":"5560_CR40","first-page":"283","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"Y-H Lin","year":"2011","unstructured":"Lin Y-H, Ban Y-C, Pan D Z, et al. DOPPLER: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2011. 283\u2013289"},{"key":"5560_CR41","first-page":"591","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco","author":"Q Ma","year":"2012","unstructured":"Ma Q, Zhang H B, Wong M D F. Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2012. 591\u2013596"},{"key":"5560_CR42","doi-asserted-by":"crossref","first-page":"123","DOI":"10.1145\/2429384.2429408","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"Y-H Lin","year":"2012","unstructured":"Lin Y-H, Yu B, Pan D Z, et al. TRIAD: a triple patterning lithography aware detailed router. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2012. 123\u2013129"},{"key":"5560_CR43","doi-asserted-by":"crossref","first-page":"390","DOI":"10.1109\/ASPDAC.2015.7059036","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba\/Tokyo","author":"P-Y Hsu","year":"2015","unstructured":"Hsu P-Y, Chang Y-W. Non-stitch triple patterning-aware routing based on conflict graph pre-coloring. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba\/Tokyo, 2015. 390\u2013395"},{"key":"5560_CR44","first-page":"1641","volume-title":"Proceedings of IEEE\/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Grenoble","author":"Z Q Liu","year":"2015","unstructured":"Liu Z Q, Liu C W, Young E F Y. An effective triple patterning aware grid-based detailed routing approach. In: Proceedings of IEEE\/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Grenoble, 2015. 1641\u20131646"},{"key":"5560_CR45","first-page":"9427","volume-title":"Proc SPIE","author":"W Gillijns","year":"2015","unstructured":"Gillijns W, Sherazi S M Y, Trivkovic D, et al. Impact of a SADP flow on the design and process for N10\/N7 metal layers. Proc SPIE, 2015: 9427"},{"key":"5560_CR46","first-page":"7974","volume-title":"Proc SPIE","author":"M Mirsaeedi","year":"2011","unstructured":"Mirsaeedi M, Torres J A, Anis M. Self-aligned double-patterning (SADP) friendly detailed routing. Proc SPIE, 2011: 7974"},{"key":"5560_CR47","first-page":"25","volume-title":"Proceedings of ACM International Symposium on Physical Design (ISPD), Napa Valley","author":"J-R Gao","year":"2012","unstructured":"Gao J-R, Pan D Z. Flexible self-aligned double patterning aware detailed routing with prescribed layout planning. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Napa Valley, 2012. 25\u201332"},{"key":"5560_CR48","first-page":"267","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama","author":"C Kodama","year":"2013","unstructured":"Kodama C, Ichikawa H, Nakayama K, et al. Self-aligned double and quadruple patterning-aware grid routing with hotspots control. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, 2013. 267\u2013272"},{"key":"5560_CR49","first-page":"6","volume":"93","author":"Y L Du","year":"2013","unstructured":"Du Y L, Ma Q, Song H, et al. Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), Austin, 2013. 93: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), Austin"},{"key":"5560_CR50","first-page":"6","volume":"50","author":"I-J Liu","year":"2014","unstructured":"Liu I-J, Fang S-Y, Chang Y-W. Overlay-aware detailed routing for self-aligned double patterning lithography using the cut process. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2014. 50: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco"},{"key":"5560_CR51","doi-asserted-by":"crossref","first-page":"396","DOI":"10.1109\/ASPDAC.2015.7059037","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba\/Tokyo","author":"S-Y Fang","year":"2015","unstructured":"Fang S-Y. Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba\/Tokyo, 2015. 396\u2013401"},{"key":"5560_CR52","first-page":"6","volume":"69","author":"Y X Ding","year":"2015","unstructured":"Ding Y X, Chu C, Mak W-K. Detailed routing for spacer-is-metal type self-aligned double\/quadruple patterning lithography. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2015. 69: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco"},{"key":"5560_CR53","first-page":"6","volume":"28","author":"X Q Xu","year":"2015","unstructured":"Xu X Q, Yu B, Gao J-R, et al. PARR: pin access planning and regular routing for self-aligned double patterning. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2015. 28: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco"},{"key":"5560_CR54","first-page":"488","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"J-S Yang","year":"2008","unstructured":"Yang J-S and Pan D Z. Overlay aware interconnect and timing variation modeling for double patterning technology. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2008. 488\u2013493"},{"key":"5560_CR55","first-page":"6730","volume-title":"Proc SPIE","author":"A Oosten van","year":"2007","unstructured":"van Oosten A, Nikolsky P, Huckabay J, et al. Pattern split rules! A feasibility study of rule based pitch decomposition for double patterning. Proc SPIE, 2007, 6730"},{"key":"5560_CR56","doi-asserted-by":"crossref","first-page":"939","DOI":"10.1109\/TCAD.2010.2048374","volume":"29","author":"A B Kahng","year":"2010","unstructured":"Kahng A B, Park C-H, Xu X, et al. Layout decomposition approaches for double patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2010, 29: 939\u2013952","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR57","doi-asserted-by":"crossref","first-page":"185","DOI":"10.1109\/TCAD.2009.2035577","volume":"29","author":"K Yuan","year":"2010","unstructured":"Yuan K, Yang J-S, Pan D Z. Double patterning layout decomposition for simultaneous conflict and stitch minimization. IEEE Trans Comput Aided Des Integr Circ Syst, 2010, 29: 185\u2013196","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR58","first-page":"601","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"Y Xu","year":"2009","unstructured":"Xu Y, Chu C. GREMA: graph reduction based efficient mask assignment for double patterning technology. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2009. 601\u2013606"},{"key":"5560_CR59","doi-asserted-by":"crossref","first-page":"121","DOI":"10.1145\/1735023.1735054","volume-title":"Proceedings of ACM International Symposium on Physical Design (ISPD), San Francisco","author":"Y Xu","year":"2010","unstructured":"Xu Y, Chu C. A matching based decomposer for double patterning lithography. In: Proceedings of ACM International Symposium on Physical Design (ISPD), San Francisco, 2010. 121\u2013126"},{"key":"5560_CR60","first-page":"9","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"X P Tang","year":"2011","unstructured":"Tang X P, Cho M. Optimal layout decomposition for double patterning technology. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2011. 9\u201313"},{"key":"5560_CR61","first-page":"637","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Taipei","author":"J-S Yang","year":"2010","unstructured":"Yang J-S, Lu K, Cho M, et al. A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Taipei, 2010. 637\u2013644"},{"key":"5560_CR62","doi-asserted-by":"crossref","first-page":"433","DOI":"10.1109\/TCAD.2014.2387840","volume":"34","author":"B Yu","year":"2015","unstructured":"Yu B, Yuan K, Ding D, et al. Layout decomposition for triple patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 433\u2013446","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR63","first-page":"1","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"B Yu","year":"2011","unstructured":"Yu B, Yuan K, Zhang B Y, et al. Layout decomposition for triple patterning lithography. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2011. 1\u20138"},{"key":"5560_CR64","first-page":"6","volume":"53","author":"B Yu","year":"2014","unstructured":"Yu B, Pan D Z. Layout decomposition for quadruple patterning lithography and beyond. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2014. 53: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco"},{"key":"5560_CR65","doi-asserted-by":"crossref","first-page":"397","DOI":"10.1109\/TCAD.2013.2288678","volume":"33","author":"S-Y Fang","year":"2014","unstructured":"Fang S-Y, Chang Y-W, and Chen W-Y. A novel layout decomposition algorithm for triple patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2014, 33: 397\u2013408","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR66","first-page":"6","volume":"69","author":"J Kuang","year":"2013","unstructured":"Kuang J, Young E F Y. An efficient layout decomposition approach for triple patterning lithography. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), Austin, 2013. 69: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), Austin"},{"key":"5560_CR67","first-page":"170","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"Y L W-S Zhang","year":"2013","unstructured":"Zhang Y, Luk W-S, Zhou H, et al. Layout decomposition with pairwise coloring for multiple patterning lithography. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 170\u2013177"},{"key":"5560_CR68","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1145\/2429384.2429396","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"H T Tian","year":"2012","unstructured":"Tian H T, Zhang H B, Ma Q, et al. A polynomial time triple patterning algorithm for cell based row-structure layout. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2012. 57\u201364"},{"key":"5560_CR69","first-page":"178","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"H T Tian","year":"2013","unstructured":"Tian H T, Du Y L, Zhang H B, et al. Constrained pattern assignment for standard cell based triple patterning lithography. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 178\u2013185"},{"key":"5560_CR70","doi-asserted-by":"crossref","first-page":"208","DOI":"10.1109\/ASPDAC.2015.7059006","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba\/Tokyo","author":"H T Tian","year":"2015","unstructured":"Tian H T, Zhang H B, Xiao Z G, et al. An efficient linear time triple patterning solver. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba\/Tokyo, 2015. 208\u2013213"},{"key":"5560_CR71","first-page":"67","volume-title":"Proceedings of ACM International Symposium on Physical Design (ISPD), Monterey","author":"H-A Chien","year":"2015","unstructured":"Chien H-A, Han S-Y, Chen Y-H, et al. A cell-based row-structure layout decomposer for triple patterning lithography. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Monterey, 2015. 67\u201374"},{"key":"5560_CR72","first-page":"1","volume-title":"Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara","author":"M Mirsaeedi","year":"2011","unstructured":"Mirsaeedi M, Torres J A, Anis M. Self-aligned double patterning (SADP) layout decomposition. In: Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, 2011. 1\u20137"},{"key":"5560_CR73","first-page":"71","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego","author":"H B Zhang","year":"2011","unstructured":"Zhang H B, Du Y L, Wong M D, et al. Self-aligned double patterning decomposition for overlay minimization and hot spot detection. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego, 2011. 71\u201376"},{"key":"5560_CR74","first-page":"789","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego","author":"Y Ban","year":"2011","unstructured":"Ban Y, Lucas K, Pan D Z. Flexible 2D layout decomposition framework for spacer-type double pattering lithography. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego, 2011. 789\u2013794"},{"key":"5560_CR75","first-page":"17","volume-title":"Proceedings of ACM International Symposium on Physical Design (ISPD), Napa Valley","author":"Z G Xiao","year":"2012","unstructured":"Xiao Z G, Zhang H B, Du Y L, et al. A polynomial time exact algorithm for self-aligned double patterning layout decomposition. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Napa Valley, 2012. 17\u201324"},{"key":"5560_CR76","first-page":"32","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"Z G Xiao","year":"2013","unstructured":"Xiao Z G, Du Y L, Tian H T, et al. Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 32\u201339"},{"key":"5560_CR77","first-page":"8326","volume-title":"Proc SPIE","author":"H B Zhang","year":"2012","unstructured":"Zhang H B, Du Y L, Wong M D F, et al. Characterization and decomposition of self-aligned quadruple patterning friendly layout. Proc SPIE, 2012: 8326"},{"key":"5560_CR78","first-page":"8684","volume-title":"Proc SPIE","author":"W L Kang","year":"2013","unstructured":"Kang W L, Feng C, Chen Y. Mask strategy and layout decomposition for self-aligned quadruple patterning. Proc SPIE, 2013: 8684"},{"key":"5560_CR79","first-page":"9231","volume-title":"Proc SPIE","author":"Y S Ma","year":"2014","unstructured":"Ma Y S, Torres J A, Fenger G, et al. Challenges and opportunities in applying grapho-epitaxy DSA lithography to metal cut and contact\/via applications. Proc SPIE, 2014: 9231"},{"key":"5560_CR80","first-page":"9423","volume-title":"Proc SPIE","author":"Y S Ma","year":"2015","unstructured":"Ma Y S, Lei J J, Torres J A, et al. Directed self-assembly (DSA) grapho-epitaxy template generation with immersion lithography. Proc SPIE, 2015: 9423"},{"key":"5560_CR81","first-page":"65","volume-title":"Proceedings of ACM International Symposium on Physical Design (ISPD), Monterey","author":"H-S P Wong","year":"2015","unstructured":"Wong H-S P, Yi H, Tung M, et al. Physical layout design of directed self-assembly guiding alphabet for IC contact hole\/via patterning. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Monterey, 2015. 65\u201366"},{"key":"5560_CR82","doi-asserted-by":"crossref","first-page":"939","DOI":"10.1126\/science.1159352","volume":"321","author":"I Bita","year":"2008","unstructured":"Bita I, Yang J K W, Jung Y S, et al. Graphoepitaxy of self-assembled block copolymers on two-dimensional periodic patterned templates. Science, 2008, 321: 939\u2013943","journal-title":"Science"},{"key":"5560_CR83","doi-asserted-by":"crossref","first-page":"7567","DOI":"10.1021\/ma401112y","volume":"46","author":"M Luo","year":"2013","unstructured":"Luo M, Epps T H. Directed block copolymer thin film self-assembly: emerging trends in nanopattern fabrication. Macromolecules, 2013, 46: 7567\u20137579","journal-title":"Macromolecules"},{"key":"5560_CR84","first-page":"8323","volume-title":"Proc SPIE","author":"H Yi","year":"2012","unstructured":"Yi H, Bao X-Y, Zhang J, et al. Contact-hole patterning for random logic circuit using block copolymer directed self-assembly. Proc SPIE, 2012: 8323"},{"key":"5560_CR85","first-page":"186","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"Y L Du","year":"2013","unstructured":"Du Y L, Guo D F, Wong M D F, et al. Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 186\u2013193"},{"key":"5560_CR86","first-page":"8880","volume-title":"Proc SPIE","author":"Z G Xiao","year":"2013","unstructured":"Xiao Z G, Du Y L, Wong M D F, et al. DSA template mask determination and cut redistribution for advanced 1D gridded design. Proc SPIE, 2013: 8880"},{"key":"5560_CR87","first-page":"83","volume-title":"Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh","author":"J J Ou","year":"2015","unstructured":"Ou J J, Yu B, Gao J-R, et al. Directed self-assembly based cut mask optimization for unidirectional design. In: Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, 2015. 83\u201386"},{"key":"5560_CR88","first-page":"410","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), Austin","author":"S-Y Fang","year":"2015","unstructured":"Fang S-Y, Hong Y-X, Lu Y-Z. Simultaneous guiding template optimization and redundant via insertion for directed self-assembly. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), Austin, 2015. 410\u2013417"},{"key":"5560_CR89","first-page":"9422","volume-title":"Proc SPIE","author":"A Mallik","year":"2015","unstructured":"Mallik A, Ryckaert J, Mercha A, et al. Maintaining Moore\u2019s law -enabling cost-friendly dimensional scaling. Proc SPIE, 2015: 9422"},{"key":"5560_CR90","first-page":"6","volume":"70","author":"Y Badr","year":"2015","unstructured":"Badr Y, Torres A, Gupta P. Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts\/vias. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2015. 70: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco"},{"key":"5560_CR91","first-page":"5751","volume-title":"Proc SPIE","author":"L Pain","year":"2005","unstructured":"Pain L, Jurdit M, Todeschini J, et al. Electron beam direct write lithography flexibility for ASIC manufacturing an opportunity for cost reduction. Proc SPIE, 2005, 5751"},{"key":"5560_CR92","first-page":"5567","volume-title":"Proc SPIE","author":"A B Kahng","year":"2004","unstructured":"Kahng A B, Xu X, Zelikovsky A. Yield-and cost-driven fracturing for variable shaped-beam mask writing. Proc SPIE, 2004, 5567"},{"key":"5560_CR93","first-page":"6283","volume-title":"Proc SPIE","author":"A B Kahng","year":"2006","unstructured":"Kahng A B, Xu X, Zelikovsky A. Fast yield-driven fracture for variable shaped-beam mask writing. Proc SPIE, 2006, 6283"},{"key":"5560_CR94","first-page":"7973","volume-title":"Proc SPIE","author":"X Ma","year":"2011","unstructured":"Ma X, Jiang S L, Zakhor A. A cost-driven fracture heuristics to minimize sliver length. Proc SPIE, 2011: 7973"},{"key":"5560_CR95","first-page":"7823","volume-title":"Proc SPIE","author":"E Sahouria","year":"2010","unstructured":"Sahouria E, Bowhill A. Generalization of shot definition for variable shaped e-beam machines for write time reduction. Proc SPIE, 2010: 7823"},{"key":"5560_CR96","first-page":"8166","volume-title":"Proc SPIE","author":"A Elayat","year":"2011","unstructured":"Elayat A, Lin T, Sahouria E, et al. Assessment and comparison of different approaches for mask write time reduction. Proc SPIE, 2011: 8166"},{"key":"5560_CR97","doi-asserted-by":"crossref","first-page":"167","DOI":"10.1109\/TCAD.2011.2179041","volume":"31","author":"K Yuan","year":"2012","unstructured":"Yuan K, Yu B, Pan D Z. E-Beam lithography stencil planning and optimization with overlapped characters. IEEE Trans Comput Aided Des Integr Circ Syst, 2012, 31: 167\u2013179","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR98","doi-asserted-by":"crossref","first-page":"167","DOI":"10.1016\/S0734-189X(84)80041-9","volume":"28","author":"A Edelsbrunner","year":"1984","unstructured":"Edelsbrunner A, O\u2019Rourke J, Welzl E. Stationing guards in rectilinear art galleries. Comput Vis Graph Image Process, 1984, 28: 167\u2013176","journal-title":"Comput Vis Graph Image Process"},{"key":"5560_CR99","doi-asserted-by":"crossref","first-page":"371","DOI":"10.1145\/234860.234865","volume":"1","author":"M A Lopez","year":"1996","unstructured":"Lopez M A, Mehta D P. Efficient decomposition of polygons into L-shapes with application to VLSI layouts. ACM Trans Des Automat Electron Syst, 1996, 1: 371\u2013395","journal-title":"ACM Trans Des Automat Electron Syst"},{"key":"5560_CR100","first-page":"249","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama","author":"B Yu","year":"2013","unstructured":"Yu B, Gao J-R, Pan D Z. L-Shape based layout fracturing for E-Beam lithography. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, 2013. 249\u2013254"},{"key":"5560_CR101","first-page":"5256","volume-title":"Proc SPIE","author":"J Kim","year":"2003","unstructured":"Kim J, Fan M. Hotspot detection on Post-OPC layout using full chip simulation based verification tool: A case study with aerial image simulation. Proc SPIE, 2003, 5256"},{"key":"5560_CR102","first-page":"6521","volume-title":"Proc SPIE","author":"E Roseboom","year":"2007","unstructured":"Roseboom E, Rossman M, Chang F-C, et al. Automated full-chip hotspot detection and removal flow for interconnect layers of cell-based designs. Proc SPIE, 2007, 6521"},{"key":"5560_CR103","first-page":"6349","volume-title":"Proc SPIE","author":"A B Kahng","year":"2006","unstructured":"Kahng A B, Park C-H, Xu X. Fast dual graph based hotspot detection. Proc SPIE, 2006, 6349"},{"key":"5560_CR104","first-page":"625","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"H Yao","year":"2006","unstructured":"Yao H, Sinha S, Chiang C, et al. Efficient process-hotspot detection using range pattern matching. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2006. 625\u2013632"},{"key":"5560_CR105","first-page":"839","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"J Y Xu","year":"2007","unstructured":"Xu J Y, Sinha S, Chiang C C. Accurate detection for process-hotspots with vias and incomplete specification. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2007. 839\u2013846"},{"key":"5560_CR106","first-page":"1167","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco","author":"Y-T Yu","year":"2012","unstructured":"Yu Y-T, Chan Y-C, Sinha S, et al. Accurate process-hotspot detection using critical design rule extraction. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2012. 1167\u20131172"},{"key":"5560_CR107","doi-asserted-by":"crossref","first-page":"1671","DOI":"10.1109\/TCAD.2014.2351273","volume":"33","author":"W-Y Wen","year":"2014","unstructured":"Wen W-Y, Li J-C, Lin S-Y, et al. A fuzzy-matching model with grid reduction for lithography hotspot detection. IEEE Trans Comput Aided Des Integr Circ Syst, 2014, 33: 1671\u20131680","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR108","first-page":"219","volume-title":"Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), Austin","author":"D Ding","year":"2009","unstructured":"Ding D, Wu X, Ghosh J, et al. Machine learning based lithographic hotspot detection with critical-feature extraction and classification. In: Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), Austin, 2009. 219\u2013222"},{"key":"5560_CR109","first-page":"545","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco","author":"D G Drmanac","year":"2009","unstructured":"Drmanac D G, Liu F, Wang L-C. Predicting variability in nanoscale lithography processes. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2009. 545\u2013550"},{"key":"5560_CR110","doi-asserted-by":"crossref","first-page":"1621","DOI":"10.1109\/TCAD.2011.2164537","volume":"30","author":"D Ding","year":"2011","unstructured":"Ding D, Torres J A, Pan D Z. High performance lithography hotspot detection with successively refined pattern identifications and machine learning. IEEE Trans Comput Aided Des Integr Circ Syst, 2011, 30: 1621\u20131634","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR111","doi-asserted-by":"crossref","first-page":"781","DOI":"10.1109\/ASPDAC.2011.5722295","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama","author":"J-Y Wuu","year":"2011","unstructured":"Wuu J-Y, Pikus F-G, Torres A, et al. Rapid layout pattern classification. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, 2011. 781\u2013786"},{"key":"5560_CR112","doi-asserted-by":"crossref","first-page":"263","DOI":"10.1109\/ASPDAC.2012.6164956","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Sydney","author":"D Ding","year":"2012","unstructured":"Ding D, Yu B, Ghosh J, et al. EPIC: efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Sydney, 2012. 263\u2013270"},{"key":"5560_CR113","doi-asserted-by":"crossref","first-page":"460","DOI":"10.1109\/TCAD.2014.2387858","volume":"34","author":"Y-T Yu","year":"2015","unstructured":"Yu Y-T, Lin G-H, Jiang I H-R, et al. Machine-learning-based hotspot detection using topological classification and critical feature extraction. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 460\u2013470","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR114","doi-asserted-by":"crossref","first-page":"011003","DOI":"10.1117\/1.JMM.14.1.011003","volume":"14","author":"B Yu","year":"2015","unstructured":"Yu B, Gao J-R, Ding D, et al. Accurate lithography hotspot detection based on principal component analysis-support vector machine classifier with hierarchical data clustering. J Micro\/Nanolithogr MEMS MOEMS, 2015, 14: 011003","journal-title":"J Micro\/Nanolithogr MEMS MOEMS"},{"key":"5560_CR115","first-page":"9427","volume-title":"Proc SPIE","author":"T Matsunawa","year":"2015","unstructured":"Matsunawa T, Gao J-R, Yu B, et al. A new lithography hotspot detection framework based on AdaBoost classifier and simplified feature extraction. Proc SPIE, 2015: 9427"},{"key":"5560_CR116","first-page":"493","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"S V Kumar","year":"2006","unstructured":"Kumar S V, Kim C H, Sapatnekar S. An analytical model for negative bias temperature instability. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2006. 493\u2013496"},{"key":"5560_CR117","first-page":"33.5.1","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC","author":"R S Wang","year":"2013","unstructured":"Wang R S, Luo M L, Guo S F, et al. A unified approach for trap-aware device\/circuit co-design in nanoscale CMOS technology. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC, 2013. 33.5.1\u201333.5.4"},{"key":"5560_CR118","first-page":"38","volume-title":"Proceedings of International Conference on VLSI Design, Mumbai","author":"S Roy","year":"2014","unstructured":"Roy S, Pan D Z. Reliability aware gate sizing combating NBTI and oxide breakdown. In: Proceedings of International Conference on VLSI Design, Mumbai, 2014. 38\u201343"},{"key":"5560_CR119","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1145\/1735023.1735056","volume-title":"Proceedings of ACM International Symposium on Physical Design (ISPD), San Francisco","author":"A Chakraborty","year":"2010","unstructured":"Chakraborty A, Pan D Z. Skew management of NBTI impacted gated clock trees. In: Proceedings of ACM International Symposium on Physical Design (ISPD), San Francisco, 2010. 127\u2013133"},{"key":"5560_CR120","volume-title":"The University of Texas at Austin","author":"S Roy","year":"2015","unstructured":"Roy S. Logic and Clock Network Optimization in Nanometer VLSI Circuits. Dissertation for the Doctoral Degree. The University of Texas at Austin, 2015"},{"key":"5560_CR121","first-page":"370","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego","author":"S V Kumar","year":"2007","unstructured":"Kumar S V, Kim C H, Sapatnekar S S. NBTI aware synthesis of digital circuits. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Diego, 2007. 370\u2013375"},{"key":"5560_CR122","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1109\/ISQED.2007.48","volume-title":"Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), San Jose","author":"X Yang","year":"2007","unstructured":"Yang X, Saluja K. Combating NBTI degradation via gate sizing. In: Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, 2007. 47\u201352"},{"key":"5560_CR123","first-page":"1047","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco","author":"R Vattikonda","year":"2006","unstructured":"Vattikonda R, Wang W P, Cao Y. Modeling and minimization of PMOS NBTI effect for robust nanometer design. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2006. 1047\u20131052"},{"key":"5560_CR124","first-page":"75","volume-title":"Proceedings of IEEE\/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Nice","author":"K-C Wu","year":"2009","unstructured":"Wu K-C, Marculescu D. Joint logic restructuring and pin reordering against NBTI-induced performance degradation. In: Proceedings of IEEE\/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Nice, 2009. 75\u201380"},{"key":"5560_CR125","first-page":"236","volume-title":"Proceedings of IEEE International Conference on Computer Design (ICCD), New York","author":"C-H Lin","year":"2015","unstructured":"Lin C-H, Roy S, Wang C-Y, et al. CSL: coordinated and scalable logic synthesis techniques for effective NBTI reduction. In: Proceedings of IEEE International Conference on Computer Design (ICCD), New York, 2015. 236\u2013243"},{"key":"5560_CR126","first-page":"389","volume-title":"IEEE Electron Dev Lett","author":"K-T Lee","year":"2008","unstructured":"Lee K-T, Kang C Y, Yoo O S, et al. PBTI-associated high-temperature hot carrier degradation of nMOSFETs with metal-gate\/high-k dielectrics. IEEE Electron Dev Lett, 2008. 389\u2013391"},{"key":"5560_CR127","first-page":"61","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"M Ebrahimi","year":"2013","unstructured":"Ebrahimi M, Oboril F, Kiamehr S, et al. Aging-aware logic synthesis. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 61\u201368"},{"key":"5560_CR128","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/DSN.2012.6263957","volume-title":"Proceedings of IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN), Boston","author":"F Oboril","year":"2012","unstructured":"Oboril F, Tahoori M B. ExtraTime: modeling and analysis of wearout due to transistor aging at microarchitecturelevel. In: Proceedings of IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN), Boston, 2012. 1\u201312"},{"key":"5560_CR129","first-page":"638","volume-title":"Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), San Jose","author":"J X Fang","year":"2010","unstructured":"Fang J X, Sapatnekar S S. Scalable methods for the analysis and optimization of gate oxide breakdown. In: Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, 2010. 638\u2013645"},{"key":"5560_CR130","first-page":"1","volume-title":"Proceedings of IEEE\/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Grenoble","author":"K V Aadithya","year":"2011","unstructured":"Aadithya K V, Demir A, Venugopalan S, et al. SAMURAI: an accurate method for modelling and simulating nonstationary random telegraph noise in SRAMs. In: Proceedings of IEEE\/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Grenoble, 2011. 1\u20136"},{"key":"5560_CR131","doi-asserted-by":"crossref","first-page":"1716","DOI":"10.1109\/TED.2013.2254118","volume":"60","author":"S Realov","year":"2013","unstructured":"Realov S, Shepard K L. Analysis of random telegraph noise in 45-nm CMOS using on-chip characterization system. IEEE Trans Electron Dev, 2013, 60: 1716\u20131722","journal-title":"IEEE Trans Electron Dev"},{"key":"5560_CR132","doi-asserted-by":"crossref","first-page":"3652","DOI":"10.1109\/TED.2011.2164543","volume":"58","author":"T Grasser","year":"2011","unstructured":"Grasser T, Kaczer B, Goes W, et al. The paradigm shift in understanding the bias temperature instability: from reaction\u2013diffusion to switching oxide traps. IEEE Trans Electron Dev, 2011, 58: 3652\u20133666","journal-title":"IEEE Trans Electron Dev"},{"key":"5560_CR133","first-page":"821","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC","author":"R S Wang","year":"2007","unstructured":"Wang R S, Huang R, Kim D-W, et al. New observations on the hot carrier and NBTI reliability of silicon nanowire transistors. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC, 2007. 821\u2013824"},{"key":"5560_CR134","first-page":"4A.5.1","volume-title":"Proceedings of IEEE International Reliability Physics Symposium (IRPS), Waikoloa","author":"T Grasser","year":"2014","unstructured":"Grasser T, Rott K, Reisinger H, et al. A unified perspective of RTN and BTI. In: Proceedings of IEEE International Reliability Physics Symposium (IRPS), Waikoloa, 2014. 4A.5.1\u20134A.5.7"},{"key":"5560_CR135","volume-title":"Bias Temperature Instability for Devices and Circuits","author":"T Grasser","year":"2013","unstructured":"Grasser T. Bias Temperature Instability for Devices and Circuits. New York: Springer Science & Business Media, 2013"},{"key":"5560_CR136","first-page":"25.4.1","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC","author":"C Z Liu","year":"2011","unstructured":"Liu C Z, Zou J B, Wang R S, et al. Towards the systematic study of aging induced dynamic variability in nano-MOSFETs: adding the missing cycle-to-cycle variation effects into device-to-device variation. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC, 2011. 25.4.1\u201325.4.4"},{"key":"5560_CR137","first-page":"19.5.1","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco","author":"C Z Liu","year":"2012","unstructured":"Liu C Z, Ren P P, Wang R S, et al. New observations on AC NBTI induced dynamic variability in scaled high-\u03ba\/metal-gate MOSFETs: characterization, origin of frequency dependence, and impacts on circuits. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2012. 19.5.1\u201319.5.4"},{"key":"5560_CR138","first-page":"34.1.1","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco","author":"P P Ren","year":"2014","unstructured":"Ren P P, Wang R S, Ji Z G, et al. New insights into the design for end-of-life variability of NBTI in scaled high-\u03ba\/metal-gate technology for the nano-reliability era. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014. 34.1.1\u201334.1.4"},{"key":"5560_CR139","first-page":"139","volume-title":"Proceedings of Symposium on VLSI Technology (VLSIT), Honolulu","author":"J B Zou","year":"2012","unstructured":"Zou J B, Wang R S, Gong N B, et al. New insights into AC RTN in scaled high-k\/metal-gate MOSFETs under digital circuit operations. In: Proceedings of Symposium on VLSI Technology (VLSIT), Honolulu, 2012. 139\u2013140"},{"key":"5560_CR140","first-page":"T186","volume-title":"Proceedings of Symposium on VLSI Technology (VLSIT), Kyoto","author":"J B Zou","year":"2013","unstructured":"Zou J B, Wang R S, Luo M L, et al. Deep understanding of AC RTN in MuGFETs through new characterization method and impacts on logic circuits. In: Proceedings of Symposium on VLSI Technology (VLSIT), Kyoto, 2013. T186\u2013T187"},{"key":"5560_CR141","first-page":"1725","volume":"62","author":"M Luo","year":"2015","unstructured":"Luo M, Wang R Q, Guo S N, et al. Impacts of random telegraph noise (RTN) on digital circuits. IEEE Trans Electron Dev, 2015, 62: 1725\u20131732","journal-title":"IEEE Trans Electron Dev"},{"key":"5560_CR142","first-page":"11.7.1","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC","author":"P P Ren","year":"2015","unstructured":"Ren P P, Xu X Q, Hao P, et al. Adding the missing time-dependent layout dependency into device-circuit-layout co-optimization: new findings on the layout dependent aging effects. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC, 2015. 11.7.1\u201311.7.4"},{"key":"5560_CR143","doi-asserted-by":"crossref","first-page":"G45","DOI":"10.1149\/1.1828419","volume":"152","author":"T C Wang","year":"2005","unstructured":"Wang T C, Hsieh T E, Wang M-T, et al. Stress migration and electromigration improvement for copper dual damascene interconnection. J Electrochem Soc, 2005, 152: G45\u2013G49","journal-title":"J Electrochem Soc"},{"key":"5560_CR144","doi-asserted-by":"crossref","first-page":"775","DOI":"10.1016\/j.microrel.2010.01.007","volume":"50","author":"R L Orio De","year":"2010","unstructured":"De Orio R L, Ceric H, Selberherr S. Physically based models of electromigration: from Black\u2019s equation to modern TCAD models. Microelectron Reliab, 2010, 50: 775\u2013789","journal-title":"Microelectron Reliab"},{"key":"5560_CR145","doi-asserted-by":"crossref","first-page":"3068","DOI":"10.1063\/1.371169","volume":"86","author":"M E Sarychev","year":"1999","unstructured":"Sarychev M E, Zhitnikov Y V, Borucki L, et al. General model for mechanical stress evolution during electromigration. J Appl Phys, 1999, 86: 3068\u20133075","journal-title":"J Appl Phys"},{"key":"5560_CR146","doi-asserted-by":"crossref","first-page":"1873","DOI":"10.1109\/TCAD.2014.2360456","volume":"33","author":"J Pak","year":"2014","unstructured":"Pak J, Lim S K, Pan D Z. Electromigration study for multiscale power\/ground vias in TSV-based 3-D ICs. IEEE Trans Comput Aided Des Integr Circ Syst, 2014, 33: 1873\u20131885","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"5560_CR147","first-page":"IT.2.1","volume-title":"Proceedings of IEEE International Reliability Physics Symposium (IRPS), Waikoloa","author":"P Gibson","year":"2014","unstructured":"Gibson P, Hogan M, Sukharev V. Electromigration analysis of full-chip integrated circuits with hydrostatic stress. In: Proceedings of IEEE International Reliability Physics Symposium (IRPS), Waikoloa, 2014. IT.2.1\u2013IT.2.7"},{"issue":"1\u201380","key":"5560_CR148","first-page":"6","volume":"80","author":"X Huang","year":"2014","unstructured":"Huang X, Yu T, Sukharev V, et al. Physics-based electromigration assessment for power grid networks. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2014. 80: 1\u201380: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco"},{"key":"5560_CR149","first-page":"33","volume-title":"Proceedings of ACM International Symposium on Physical Design (ISPD), Stateline","author":"J Lienig","year":"2013","unstructured":"Lienig J. Electromigration and its impact on physical design in future technologies. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Stateline, 2013. 33\u201340"},{"key":"5560_CR150","doi-asserted-by":"crossref","first-page":"544","DOI":"10.1109\/ASPDAC.2015.7059063","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba\/Tokyo","author":"J Pak","year":"2015","unstructured":"Pak J, Yu B, Pan D Z. Electromigration-aware redundant via insertion. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba\/Tokyo, 2015. 544\u2013549"},{"key":"5560_CR151","first-page":"486","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"G Posser","year":"2014","unstructured":"Posser G, Mishra V, Jain O, et al. A systematic approach for analyzing and optimizing cell-internal signal electromigration. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2014. 486\u2013491"},{"key":"5560_CR152","doi-asserted-by":"crossref","first-page":"299","DOI":"10.1145\/2206781.2206854","volume-title":"Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Salt Lake City","author":"J Xie","year":"2012","unstructured":"Xie J, Narayanan V, Xie Y. Mitigating electromigration of power supply networks using bidirectional current stress. In: Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Salt Lake City, 2012. 299\u2013302"},{"key":"5560_CR153","doi-asserted-by":"crossref","first-page":"118","DOI":"10.1109\/TVLSI.2014.2301458","volume":"23","author":"D-A Li","year":"2015","unstructured":"Li D-A, Marek-Sadowska M, Nassif S R. A method for improving power grid resilience to electromigration-caused via failures. IEEE Trans Very Large Scale Integr Syst, 2015, 23: 118\u2013130","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"5560_CR154","doi-asserted-by":"crossref","first-page":"325","DOI":"10.1145\/2429384.2429451","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"J Pak","year":"2012","unstructured":"Pak J, Lim S K, Pan D Z. Electromigration-aware routing for 3D ICs with stress-aware EM modeling. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2012. 325\u2013332"},{"key":"5560_CR155","first-page":"770","volume":"9","author":"X D Chen","year":"2012","unstructured":"Chen X D, Liao C, Wei T Q, et al. An interconnect reliability-driven routing technique for electromigration failure avoidance. IEEE Trans Depend Secur Comput, 2012, 9: 770\u2013776","journal-title":"IEEE Trans Depend Secur Comput"},{"key":"5560_CR156","doi-asserted-by":"crossref","first-page":"581","DOI":"10.1109\/TVLSI.2011.2116049","volume":"20","author":"I H-R Jiang","year":"2012","unstructured":"Jiang I H-R, Chang H-Y, Chang C-L. WiT: optimal wiring topology for electromigration avoidance. IEEE Trans Very Large Scale Integr Syst, 2012, 20: 581\u2013592","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"5560_CR157","doi-asserted-by":"crossref","first-page":"405","DOI":"10.1109\/TDMR.2005.855790","volume":"5","author":"M Nicolaidis","year":"2005","unstructured":"Nicolaidis M. Design for soft error mitigation. IEEE Trans Dev Mater Reliab, 2005, 5: 405\u2013418","journal-title":"IEEE Trans Dev Mater Reliab"},{"key":"5560_CR158","doi-asserted-by":"crossref","first-page":"512","DOI":"10.1109\/TCSII.2011.2158750","volume":"58","author":"P Reviriengo","year":"2011","unstructured":"Reviriengo P, Bleakly C J, Maestro J A. Structural dmr: a technique for implementation of soft-error-tolerant fir filters. IEEE Trans Circ Syst II, 2011, 58: 512\u2013516","journal-title":"IEEE Trans Circ Syst II"},{"key":"5560_CR159","first-page":"6","volume":"161","author":"K A Campbell","year":"2015","unstructured":"Campbell K A, Vissa P, Pan D Z, et al. High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2015. 161: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco"},{"key":"5560_CR160","first-page":"601","volume-title":"Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama","author":"M Ebrahimi","year":"2013","unstructured":"Ebrahimi M, Liang C, Asadi H, et al. CLASS: combined logic and architectural soft error sensitivity analysis. In: Proceedings of IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, 2013. 601\u2013607"},{"key":"5560_CR161","doi-asserted-by":"crossref","first-page":"1628","DOI":"10.1109\/TVLSI.2014.2348872","volume":"23","author":"H-M Chou","year":"2015","unstructured":"Chou H-M, Hsiao M-Y, Chen Y-C, et al. Soft-error-tolerant design methodology for balancing performance, power, and reliability. IEEE Trans Very Large Scale Integr Syst, 2015, 23: 1628\u20131639","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"5560_CR162","first-page":"502","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco","author":"W G Sheng","year":"2009","unstructured":"Sheng W G, Xiao L Y, Mao Z G. Soft error optimization of standard cell circuits based on gate sizing and multiobjective genetic algorithm. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2009. 502\u2013507"},{"key":"5560_CR163","first-page":"6","volume":"89","author":"H Cho","year":"2015","unstructured":"Cho H, Cher C-Y, Shepherd T, et al. Understanding soft errors in uncore components. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2015. 89: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco"},{"key":"5560_CR164","first-page":"6","volume":"201","author":"S Kiamehr","year":"2014","unstructured":"Kiamehr S, Osiecki T, Tahoori M B, et al. Radiation-induced soft error analysis of SRAMs in SOI FinFET technology: a device to circuit approach. In: Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2014. 201: 6","journal-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC), San Francisco"},{"key":"5560_CR165","first-page":"157","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose","author":"H-K Peng","year":"2009","unstructured":"Peng H-K, Wen C H-P, Bhadra J. On soft error rate analysis of scaled CMOS designs: a statistical perspective. In: Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2009. 157\u2013163"},{"key":"5560_CR166","unstructured":"Cadence Virtuoso DFM. http:\/\/www.cadence.com"},{"key":"5560_CR167","unstructured":"Synopsys IC Validator. http:\/\/www.synopsys.com"},{"key":"5560_CR168","unstructured":"Calibre pattern matching. http:\/\/www.mentor.com\/products"},{"key":"5560_CR169","volume-title":"IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara","author":"L Capodieci","year":"2012","unstructured":"Capodieci L. Beyond 28nm: new frontiers and innovations in design for manufacturability at the limits of the scaling roadmap. IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, 2012"},{"key":"5560_CR170","volume-title":"Mentor Graphics White Paper","author":"D Abercrombie","year":"2013","unstructured":"Abercrombie D. Mastering the magic of multi-patterning. Mentor Graphics White Paper, 2013"},{"key":"5560_CR171","volume-title":"MOS-AK Workshop, Grenoble","author":"M Selim","year":"2015","unstructured":"Selim M. Circuit aging tools and reliability verification. In: MOS-AK Workshop, Grenoble, 2015"},{"key":"5560_CR172","volume-title":"Synopsys White Paper","author":"B Tudor","year":"2011","unstructured":"Tudor B, Wang J, Liu W D, et al. MOS device aging analysis with HSPICE and CustomSim. Synopsys White Paper, 2011"},{"key":"5560_CR173","unstructured":"RedHawk-SEM. https:\/\/www.apache-da.com\/products\/redhawk\/redhawk-sem"}],"container-title":["Science China Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-016-5560-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11432-016-5560-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-016-5560-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,20]],"date-time":"2022-06-20T21:49:12Z","timestamp":1655761752000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11432-016-5560-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5,6]]},"references-count":173,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2016,6]]}},"alternative-id":["5560"],"URL":"https:\/\/doi.org\/10.1007\/s11432-016-5560-6","relation":{},"ISSN":["1674-733X","1869-1919"],"issn-type":[{"value":"1674-733X","type":"print"},{"value":"1869-1919","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,5,6]]},"article-number":"061406"}}