{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T13:50:26Z","timestamp":1774446626463,"version":"3.50.1"},"reference-count":78,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2016,4,25]],"date-time":"2016-04-25T00:00:00Z","timestamp":1461542400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Sci. China Inf. Sci."],"published-print":{"date-parts":[[2016,6]]},"DOI":"10.1007\/s11432-016-5561-5","type":"journal-article","created":{"date-parts":[[2016,4,26]],"date-time":"2016-04-26T11:17:16Z","timestamp":1461669436000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":57,"title":["Fully depleted SOI (FDSOI) technology"],"prefix":"10.1007","volume":"59","author":[{"given":"Kangguo","family":"Cheng","sequence":"first","affiliation":[]},{"given":"Ali","family":"Khakifirooz","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,4,25]]},"reference":[{"key":"5561_CR1","unstructured":"Semiconductor Industry Association Global Sales Report. http:\/\/www.semiconductors.org\/industry statistics\/global sales report\/"},{"key":"5561_CR2","first-page":"82","volume":"38","author":"G E Moore","year":"1965","unstructured":"Moore G E. Cramming more components onto integrated circuits. Electronics, 1965, 38: 82\u201385","journal-title":"Electronics"},{"key":"5561_CR3","doi-asserted-by":"crossref","first-page":"131","DOI":"10.1109\/VLSIT.2012.6242496","volume-title":"Proceedings of VLSI 2012 Symposium on Technology (VLSIT), Honolulu","author":"C Auth","year":"2012","unstructured":"Auth C, Allen C, Blattner A, et al. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. In: Proceedings of VLSI 2012 Symposium on Technology (VLSIT), Honolulu, 2012. 131\u2013132"},{"key":"5561_CR4","doi-asserted-by":"crossref","first-page":"256","DOI":"10.1109\/JSSC.1974.1050511","volume":"9","author":"R H Dennard","year":"1974","unstructured":"Dennard R H, Gaensslen F H, Rideout V L, et al. Design of ion-implanted MOSFET\u2019s with very small physical dimensions. IEEE J Solid-State Circuits, 1974, 9: 256\u2013268","journal-title":"IEEE J Solid-State Circuits"},{"key":"5561_CR5","first-page":"147","volume-title":"Technical Digest of International Electron Devices Meeting, San Francisco","author":"H Wann","year":"1992","unstructured":"Wann H, Ko P K, Hu C. Gate-induced band-to-band tunneling leakage current in LDD MOSFETs. In: Technical Digest of International Electron Devices Meeting, San Francisco, 1992. 147\u2013150"},{"key":"5561_CR6","first-page":"659","volume-title":"Technical Digest of International Electron Devices Meeting, Washington DC","author":"A Bhavnagarwala","year":"2005","unstructured":"Bhavnagarwala A, Kosonocky S, Radens C, et al. Fluctuation limits & scaling opportunities for CMOS SRAM cells. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2005. 659\u2013662"},{"key":"5561_CR7","doi-asserted-by":"crossref","first-page":"254","DOI":"10.1109\/55.841313","volume":"21","author":"Y-K Choi","year":"1999","unstructured":"Choi Y-K, Asano K, Lindert N, et al. Ultra-thin body SOI MOSFET for deep-sub-tenth micron era. IEEE Electron Dev Lett, 1999, 21: 254\u2013255","journal-title":"IEEE Electron Dev Lett"},{"key":"5561_CR8","first-page":"210","volume-title":"Proceedings of the European Solid-State Device Research Conference (ESSDERC), Sevilla","author":"J-P Noel","year":"2010","unstructured":"Noel J-P, Thomas O, Jaud M-A, et al. UTB-FDSOI device architecture dedicated to low power design techniques. In: Proceedings of the European Solid-State Device Research Conference (ESSDERC), Sevilla, 2010. 210\u2013213"},{"key":"5561_CR9","doi-asserted-by":"crossref","first-page":"836","DOI":"10.1109\/LED.2005.857725","volume":"26","author":"G Tsutsui","year":"2005","unstructured":"Tsutsui G, Saitoh M, Hiramoto T. Experimental study on superior mobility in (110)-oriented UTB SOI pMOSFETs. IEEE Electron Dev Lett, 2005, 26: 836\u2013838","journal-title":"IEEE Electron Dev Lett"},{"key":"5561_CR10","doi-asserted-by":"crossref","first-page":"16","DOI":"10.1109\/MCD.2005.1388765","volume":"21","author":"T Skotnicki","year":"2006","unstructured":"Skotnicki T, Hutchby J A, King T-J, et al. The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits Dev Mag, 2006, 21: 16\u201326","journal-title":"IEEE Circuits Dev Mag"},{"key":"5561_CR11","doi-asserted-by":"crossref","first-page":"50","DOI":"10.1016\/j.sse.2011.11.020","volume":"70","author":"V Kilchytska","year":"2012","unstructured":"Kilchytska V, Md Arshad M K, Makovejev S, et al. Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit. Solid-State Electron, 2012, 70: 50\u201358","journal-title":"Solid-State Electron"},{"key":"5561_CR12","first-page":"267","volume-title":"Technical Digest of International Electron Devices Meeting, Washington DC","author":"C Fenouillet-Beranger","year":"2007","unstructured":"Fenouillet-Beranger C, Denormel S, Icard B, et al. Fully-depleted SOI technology using high-K and single-metal gate for 32nm node LSTP applications featuring 0.179\u00b5m2 6T-SRAM bitcell. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2007. 267\u2013270"},{"key":"5561_CR13","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/SOI.2011.6081792","volume-title":"Proceedings of 2011 IEEE International SOI Conference (SOI), Tempe","author":"T Skotnicki","year":"2011","unstructured":"Skotnicki T. Competitive SOC with UTBB SOI. In: Proceedings of 2011 IEEE International SOI Conference (SOI), Tempe, 2011. 1\u201361"},{"key":"5561_CR14","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1109\/VLSIT.2010.5556120","volume-title":"Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu","author":"Q Liu","year":"2010","unstructured":"Liu Q, Yagashita A, Loubet N, et al. Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond. In: Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu, 2010. 61\u201362"},{"key":"5561_CR15","first-page":"64","volume-title":"Technical Digest of International Electron Devices Meeting, San Francisco","author":"L Grenouillet","year":"2012","unstructured":"Grenouillet L, Vinet M, Gimbert J, et al. UTBB FDSOI transistors with dual STI and shrinked back gate architecture for a multi-VT strategy at 20nm node and below. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2012. 64\u201367"},{"key":"5561_CR16","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1109\/VLSIT.2010.5556122","volume-title":"Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu","author":"F Andrieu","year":"2010","unstructured":"Andrieu F, Weber O, Mazurier J, et al. Low leakage and low variability ultra-thin body and buried oxide (UT2B) SOI technology for 20nm low power CMOS and beyond. In: Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu, 2010. 57\u201358"},{"key":"5561_CR17","first-page":"78","volume-title":"Proceedings of 2000 IEEE International SOI Conference, Wakefield","author":"T Numata","year":"2000","unstructured":"Numata T, Noguchi M, Oowaki Y, et al. Back gate engineering for suppression of threshold voltage fluctuation in fully-depleted SOI MOSFETs. In: Proceedings of 2000 IEEE International SOI Conference, Wakefield, 2000. 78\u201379"},{"key":"5561_CR18","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/IEDM.2008.4796664","volume-title":"Proceedings of 2008 International Electron Devices Meeting, San Francisco","author":"N Sugii","year":"2008","unstructured":"Sugii N, Tsuchiya R, Ishigaki T, et al. Comprehensive study on Vth variability in silicon on thin BOX (SOTB) CMOS with small random-dopant fluctuation: finding a way to further reduce variation. In: Proceedings of 2008 International Electron Devices Meeting, San Francisco, 2008. 1\u20134"},{"key":"5561_CR19","doi-asserted-by":"crossref","first-page":"835","DOI":"10.1109\/TED.2010.2040664","volume":"57","author":"N Sugii","year":"2010","unstructured":"Sugii N, Tsuchiya R, Ishigaki T, et al. Local Vth variability and scalability in silicon-on-thin-BOX (SOTB) CMOS with small random-dopant fluctuation. IEEE Trans Electron Dev, 2010, 57: 835\u2013845","journal-title":"IEEE Trans Electron Dev"},{"key":"5561_CR20","first-page":"27.3.1","volume-title":"Technical Digest of International Electron Devices Meeting, Washington DC","author":"B Doris","year":"2003","unstructured":"Doris B, Ieong M, Zhu T, et al. Device design considerations for ultra-thin SOI MOSFETs. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2003. 27.3.1\u201327.3.4"},{"key":"5561_CR21","first-page":"1","volume-title":"Proceedings of IEEE International Conference on IC Design and Technology, Kao-hsiung","author":"W Schwarzenbach","year":"2011","unstructured":"Schwarzenbach W, Cauchy X, Boedt F, et al. Excellent silicon thickness uniformity on ultra-thin SOI for controlling VT variation of FDSOI. In: Proceedings of IEEE International Conference on IC Design and Technology, Kao-hsiung, 2011. 1\u20133"},{"key":"5561_CR22","doi-asserted-by":"crossref","first-page":"288","DOI":"10.1109\/LED.2006.871542","volume":"27","author":"H M Nayfeh","year":"2006","unstructured":"Nayfeh H M, Singh D V, Hergenrother J M, et al. Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-Type MOSFETs. IEEE Electron Dev Lett, 2006, 27: 288\u2013290","journal-title":"IEEE Electron Dev Lett"},{"key":"5561_CR23","first-page":"61","volume-title":"Technical Digest of International Electron Devices Meeting, Washington DC","author":"V Barral","year":"2007","unstructured":"Barral V, Poiroux T, Andrieu F, et al. Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN\/HfO2 gate stack. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2007. 61\u201364"},{"key":"5561_CR24","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1109\/IEDM.2002.1175776","volume-title":"Technical Digest of International Electron Devices Meeting, San Francisco","author":"K Uchida","year":"2002","unstructured":"Uchida K, Watanabe H, Kinoshita A, et al. Experimental study on carrier transport mechanism in ultrathin-body SOI n-and p-MOSFETs with SOI thickness less than 5 nm. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2002. 47\u201350"},{"key":"5561_CR25","first-page":"50","volume-title":"Technical Digest of International Electron Devices Meeting, San Francisco","author":"O Faynot","year":"2010","unstructured":"Faynot O, Andrieu F, Weber O, et al. Planar fully depleted SOI technology: a powerful architecture for the 20nm node and beyond. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2010. 50\u201353"},{"key":"5561_CR26","first-page":"1","volume-title":"Technical Digest of International Electron Devices Meeting, Baltimore","author":"C Fenouillet-Beranger","year":"2009","unstructured":"Fenouillet-Beranger C, Perreau P, Pham-Nguyen L, et al. Hybrid FDSOI\/Bulk high-k\/Metal gate platform for Low Power (LP) multimedia technology. In: Technical Digest of International Electron Devices Meeting, Baltimore, 2009. 1\u20134"},{"key":"5561_CR27","doi-asserted-by":"crossref","first-page":"413","DOI":"10.1109\/LED.2009.2014086","volume":"30","author":"A Majumdar","year":"2009","unstructured":"Majumdar A, Wang X, Kumar A, et al. Gate length and performance scaling of undoped-body extremely thin SOI MOSFETs. IEEE Electron Dev Lett, 2009, 30: 413\u2013415","journal-title":"IEEE Electron Dev Lett"},{"key":"5561_CR28","doi-asserted-by":"crossref","first-page":"2270","DOI":"10.1109\/TED.2009.2028057","volume":"56","author":"A Majumdar","year":"2009","unstructured":"Majumdar A, Ren Z, Koester S J, et al. Undoped-body extremely thin SOI MOSFETs with back gates. IEEE Trans Electron Dev, 2009, 56: 2270\u20132276","journal-title":"IEEE Trans Electron Dev"},{"key":"5561_CR29","first-page":"212","volume-title":"Proceedings of 2009 Symposium on VLSI Technology (VLSIT), Honolulu","author":"K Cheng","year":"2009","unstructured":"Cheng K, Khakifirooz A, Kulkarni P, et al. Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source\/drain. In: Proceedings of 2009 Symposium on VLSI Technology (VLSIT), Honolulu, 2009. 212\u2013213"},{"key":"5561_CR30","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/VLSIT.2012.6242489","volume-title":"Proceedings of 2012 Symposium on VLSI Technology (VLSIT), Honolulu","author":"A Khakifirooz","year":"2012","unstructured":"Khakifirooz A, Cheng K, Nagumo T, et al. Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS. In: Proceedings of 2012 Symposium on VLSI Technology (VLSIT), Honolulu, 2012. 117\u2013118"},{"key":"5561_CR31","first-page":"49","volume-title":"Proceedings of 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore","author":"K Cheng","year":"2009","unstructured":"Cheng K, Khakifirooz A, Kulkarni P, et al. Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In: Proceedings of 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, 2009. 49\u201352"},{"key":"5561_CR32","first-page":"18.1.1","volume-title":"Technical Digest of International Electron Devices Meeting, San Francisco","author":"K Cheng","year":"2012","unstructured":"Cheng K, Khakifirooz A, Loubet N, et al. High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained sige channel PFET. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2012. 18.1.1\u201318.4"},{"key":"5561_CR33","first-page":"110","volume-title":"Proceedings of International Symposium on VLSI Technology Systems and Applications (VLSI-TSA), Hsinchu","author":"A Khakifirooz","year":"2010","unstructured":"Khakifirooz A, Cheng K, Kulkarni P, et al. Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications. In: Proceedings of International Symposium on VLSI Technology Systems and Applications (VLSI-TSA), Hsinchu, 2010. 110\u2013111"},{"key":"5561_CR34","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/SOI.2011.6081679","volume-title":"Proceedings of 2011 IEEE International SOI Conference, Tempe","author":"S Ponoth","year":"2011","unstructured":"Ponoth S, Vinet M, Grenouillet L, et al. Implant approaches and challenges for 20nm node and beyond ETSOI devices. In: Proceedings of 2011 IEEE International SOI Conference, Tempe, 2011. 1\u20132"},{"key":"5561_CR35","first-page":"29.1.1","volume-title":"Technical Digest of International Electron Devices Meeting, Washington DC","author":"R Chau","year":"2001","unstructured":"Chau R, Kavalieros J, Doyle B, et al. A 50nm depleted-substrate CMOS Transistor (DST). In: Technical Digest of International Electron Devices Meeting, Washington DC, 2001. 29.1.1\u201329.1.4"},{"key":"5561_CR36","first-page":"131","volume-title":"Proceedings of 2003 Symposium on VLSI Technology (VLSIT), Kyoto","author":"Z Krivokapic","year":"2003","unstructured":"Krivokapic Z, Maszara W, Arasnia F, et al. High performance 25nm FDSOI devices with extremely thin silicon channel. In: Proceedings of 2003 Symposium on VLSI Technology (VLSIT), Kyoto, 2003. 131\u2013132"},{"key":"5561_CR37","first-page":"16","volume-title":"Proceedings of 2005 Symposium on VLSI Technology (VLSIT), Kyoto","author":"H Chen","year":"2005","unstructured":"Chen H, Chang C, Huang C, et al. Novel 20nm hybrid SOI\/bulk CMOS technology with 0.183\u00b5m2 6T-SRAM cell by immersion lithography. In: Proceedings of 2005 Symposium on VLSI Technology (VLSIT), Kyoto, 2005. 16\u201317"},{"key":"5561_CR38","first-page":"89","volume-title":"Proceedings of the European Solid-State Device Research Conference (ESSDERC), Athens","author":"C Fenouillet","year":"2009","unstructured":"Fenouillet C, Perreau P, Denorme S, et al. Impact of a 10 nm ultrathin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below. In: Proceedings of the European Solid-State Device Research Conference (ESSDERC), Athens, 2009. 89\u201391"},{"key":"5561_CR39","doi-asserted-by":"crossref","first-page":"65","DOI":"10.1109\/VLSIT.2010.5556118","volume-title":"Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu","author":"C Fenouillet","year":"2010","unstructured":"Fenouillet C, Thomas O, Perreau P, et al. Efficient multi-VT FDSOI technology with UTBOX for low power circuit design. In: Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu, 2010. 65\u201366"},{"key":"5561_CR40","doi-asserted-by":"crossref","first-page":"96","DOI":"10.1109\/TED.2007.911338","volume":"55","author":"T Skotnicki","year":"2008","unstructured":"Skotnicki T, Fenouillet-Beranger C, Gallon C, et al. Innovative materials, devices, and CMOS technologies for lowpower mobile multimedia. IEEE Trans Electron Dev, 2008, 55: 96\u2013130","journal-title":"IEEE Trans Electron Dev"},{"key":"5561_CR41","first-page":"679","volume-title":"Technical Digest of International Electron Devices Meeting, Washington DC","author":"E Leobandung","year":"1999","unstructured":"Leobandung E, Barth E, Sherony M, et al. High performance 0.18 pm SOI CMOS technology. In: Technical Digest of International Electron Devices Meeting, Washington DC, 1999. 679\u2013682"},{"key":"5561_CR42","first-page":"103","volume-title":"Proceedings of 1998 IEEE International SOI Conference, Stuart","author":"R Puri","year":"1998","unstructured":"Puri R, Chuang C T. Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits. In: Proceedings of 1998 IEEE International SOI Conference, Stuart, 1998. 103\u2013104"},{"key":"5561_CR43","doi-asserted-by":"crossref","first-page":"96","DOI":"10.1109\/TED.2007.911338","volume":"55","author":"T Skotnicki","year":"2008","unstructured":"Skotnicki T, Fenouillet-Beranger C, Gallon C, et al. Innovative materials, devices, and CMOS technologies for lowpower mobile multimedia. IEEE Trans Electron Dev, 2008, 55: 96\u2013130","journal-title":"IEEE Trans Electron Dev"},{"key":"5561_CR44","doi-asserted-by":"crossref","first-page":"1391","DOI":"10.1109\/TED.2008.921017","volume":"55","author":"A Khakifirooz","year":"2008","unstructured":"Khakifirooz A, Antoniadis D A. MOSFET performance scaling\u2014Part 1: historical trends. IEEE Trans Electron Dev, 2008, 55: 1391\u20131400","journal-title":"IEEE Trans Electron Dev"},{"key":"5561_CR45","doi-asserted-by":"crossref","first-page":"1433","DOI":"10.1109\/JSSC.1989.572629","volume":"24","author":"M Pelgrom","year":"1989","unstructured":"Pelgrom M. Matching properties of MOS transistors. IEEE J Solid-State Circuits, 1989, 24: 1433\u20131439","journal-title":"IEEE J Solid-State Circuits"},{"key":"5561_CR46","first-page":"86","volume-title":"Digitally-Assisted Analog and Analog-Assisted Digital IC Design","author":"K Cheng","year":"2015","unstructured":"Cheng K, Khakifirooz A. FDSOI technology and its implications to analog and digital design. In: Jiang X C, ed. Digitally-Assisted Analog and Analog-Assisted Digital IC Design. Cambridge: Cambridge University Press, 2015. 86"},{"key":"5561_CR47","doi-asserted-by":"crossref","first-page":"1813","DOI":"10.1109\/TED.2012.2193129","volume":"59","author":"K J Kuhn","year":"2012","unstructured":"Kuhn K J. Considerations for ultimate CMOS scaling. IEEE Trans Electron Dev, 2012, 59: 1813\u20131828","journal-title":"IEEE Trans Electron Dev"},{"key":"5561_CR48","first-page":"T212","volume-title":"Proceedings of 2013 Symposium on VLSI Technology (VLSIT), Kyoto","author":"Y Yamamoto","year":"2013","unstructured":"Yamamoto Y, Makiyama H, Shinohara H, et al. Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias. In: Proceedings of 2013 Symposium on VLSI Technology (VLSIT), Kyoto, 2013. T212\u2013T213"},{"key":"5561_CR49","doi-asserted-by":"crossref","first-page":"152","DOI":"10.1109\/ISSCC.2010.5434014","volume-title":"2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco","author":"A Khakifirooz","year":"2010","unstructured":"Khakifirooz A, Cheng K, Jagannathan B, et al. Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. In: 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, 2010. 152\u2013153"},{"key":"5561_CR50","first-page":"11.6.1","volume-title":"Technical Digest of International Electron Devices Meeting, Washington DC","author":"T Ghani","year":"2003","unstructured":"Ghani T, Armstrong M, Auth C, et al. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2003. 11.6.1\u201311.6.3"},{"key":"5561_CR51","first-page":"56","volume-title":"Technical Digest of International Electron Devices Meeting, Washington DC","author":"W-H Lee","year":"2005","unstructured":"Lee W-H, Waite A, Nii H, et al. High performance 32nm SOI CMOS with high-k\/metal gate and 0.149\u00b5m2 SRAM and ultra low-k back end with eleven levels of copper. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2005. 56\u201359"},{"key":"5561_CR52","first-page":"3.3.1","volume-title":"Technical Digest of International Electron Devices Meeting, San Francisco","author":"S Narasimha","year":"2012","unstructured":"Narasimha S, Chang P, Ortolland C, et al. 22nm high-performance SOI technology featuring dual-embedded stressors, epi-plate high-k deep-trench embedded DRAM and self-aligned via 15LM BEOL. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2012. 3.3.1\u20133.3.4"},{"key":"5561_CR53","doi-asserted-by":"crossref","first-page":"126","DOI":"10.1109\/.2005.1469238","volume-title":"2005 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto","author":"E Leobandung","year":"2005","unstructured":"Leobandung E, Nayakama H, Mocuta D, et al. High performance 65 nm SOI technology with dual stress line and low capacitance SRAM cell. In: 2005 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, 2005. 126\u2013127"},{"key":"5561_CR54","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1109\/IEDM.2002.1175771","volume-title":"Proceedings of International Electron Devices Meeting, San Francisco","author":"K Ota","year":"2002","unstructured":"Ota K, Sugihara K, Sayama H, et al. Novel locally strained channel technique for high performance 55 nm CMOS. In: Proceedings of International Electron Devices Meeting, San Francisco, 2002. 27\u201330"},{"key":"5561_CR55","first-page":"10.1.1","volume-title":"Proceedings of International Electron Devices Meeting, San Francisco","author":"K-Y Lim","year":"2010","unstructured":"Lim K-Y, Lee H, Ryu C, et al. Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k\/metal gate devices. In: Proceedings of International Electron Devices Meeting, San Francisco, 2010. 10.1.1\u201310.1.4"},{"key":"5561_CR56","first-page":"3.1.1","volume-title":"Proceedings of International Electron Devices Meeting, San Francisco","author":"C-H Jan","year":"2012","unstructured":"Jan C-H, Bhattacharya U, Brain R, et al. A 22nm SoC platform technology featuring 3-D tri-gate and high-k\/metal gate, optimized for ultra low power, high performance and high density SoC applications. In: Proceedings of International Electron Devices Meeting, San Francisco, 2012. 3.1.1\u20133.1.4"},{"key":"5561_CR57","first-page":"3.7.1","volume-title":"Proceedings of International Electron Devices Meeting, San Francisco","author":"S Natarajan","year":"2014","unstructured":"Natarajan S, Agostinelli M, Akbar S, et al. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588\u00b5m2 SRAM cell size. In: Proceedings of International Electron Devices Meeting, San Francisco, 2014. 3.7.1\u20133.7.3"},{"key":"5561_CR58","doi-asserted-by":"crossref","first-page":"T12","DOI":"10.1109\/VLSIT.2015.7223683","volume-title":"Proceedings of 2015 Symposium on VLSI Technology, Kyoto","author":"C-H Jan","year":"2015","unstructured":"Jan C-H, Al-amoody F, Chang H-Y, et al. A 14 nm SoC platform technology featuring 2nd generation tri-gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products. In: Proceedings of 2015 Symposium on VLSI Technology, Kyoto, 2015. T12\u2013T13"},{"key":"5561_CR59","first-page":"9.1.1","volume-title":"Proceedings of International Electron Devices Meeting, San Francisco","author":"Q Liu","year":"2014","unstructured":"Liu Q, DeSalvo B, Morin P, et al. FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node. In: Proceedings of International Electron Devices Meeting, San Francisco, 2014. 9.1.1\u20139.1.4"},{"key":"5561_CR60","doi-asserted-by":"crossref","first-page":"54","DOI":"10.1109\/ISSCC.1976.1155515","volume-title":"Technical Digest of 1976 IEEE International Solid-State Circuits Conference, Philadelphia","author":"M Kube","year":"1976","unstructured":"Kube M, Hori R, Minato O, et al. A threshold voltage controlling circuit for short channel MOS integrated circuits. In: Technical Digest of 1976 IEEE International Solid-State Circuits Conference, Philadelphia, 1976. 54\u201355"},{"key":"5561_CR61","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1109\/VLSIT.1997.623699","volume-title":"1997 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto","author":"S Thompson","year":"1997","unstructured":"Thompson S, Young I, Greason J, et al. Dual threshold voltage and substrate bias: Keys to high performance, low power, 0.1 \u00b5m logic designs. In: 1997 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, 1997. 69\u201370"},{"key":"5561_CR62","first-page":"262","volume-title":"IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco","author":"S Nomura","year":"2008","unstructured":"Nomura S, Tachibana F, Fujita T, et al. A 9.7mW AAC-decoding, 620mW H.264 720p 60fps decoding, 8-core media processor with embedded forward-body-biasing and power-gating circuit in 65nm CMOS technology. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, 2008. 262\u2013612"},{"key":"5561_CR63","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/JSSC.2004.838013","volume":"40","author":"M Sumita","year":"2005","unstructured":"Sumita M, Sakiyama S, Kinoshita M, et al. Mixed body-bias technique with fixed V t and I ds generation circuits. IEEE J Solid-State Circuits, 2005, 40: 60\u201366","journal-title":"IEEE J Solid-State Circuits"},{"key":"5561_CR64","doi-asserted-by":"crossref","first-page":"812","DOI":"10.1109\/JSSC.2013.2295977","volume":"49","author":"D Jacquet","year":"2014","unstructured":"Jacquet D, Hasbani F, Flatresse P, et al. A 3 GHz dual core processor ARM CortexTM-A9 in 28 nm UTBB FDSOI CMOS with ultra-wide voltage range and energy efficiency optimization. IEEE J Solid-State Circuits, 2014, 49: 812\u2013826","journal-title":"IEEE J Solid-State Circuits"},{"key":"5561_CR65","doi-asserted-by":"crossref","first-page":"452","DOI":"10.1109\/ISSCC.2014.6757509","volume-title":"2014 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco","author":"R Wilson","year":"2014","unstructured":"Wilson R, Beigne E, Flatresse P, et al. A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding FMAX Tracking. In: 2014 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, 2014. 452\u2013453"},{"key":"5561_CR66","first-page":"1","volume-title":"2014 IEEE COOL Chips XVII, Yokohama","author":"K Ishibashi","year":"2014","unstructured":"Ishibashi K, Sugii N, Usami K, et al. A perpetuum mobile 32bit CPU with 13.4pJ\/cycle, 0.14\u00b5A sleep current using reverse body bias assisted 65nm SOTB CMOS technology. In: 2014 IEEE COOL Chips XVII, Yokohama, 2014. 1\u20133"},{"key":"5561_CR67","doi-asserted-by":"crossref","first-page":"125","DOI":"10.1109\/JSSC.2014.2369503","volume":"50","author":"E Beigne","year":"2015","unstructured":"Beigne E, Valentian A, Miro-Panades I, et al. A 460MHz at 397mV, 2.6GHz at 1.3V, 32 bits VLIW DSP embedding F max tracking. IEEE J Solid-State Circuits, 2015, 50: 125\u2013136","journal-title":"IEEE J Solid-State Circuits"},{"key":"5561_CR68","first-page":"1","volume-title":"Proceedings of 2015 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco","author":"S Clerc","year":"2015","unstructured":"Clerc S, Saligane M, Abouzeid F, et al. A 0.33V\/-40\u00b0C process\/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. In: Proceedings of 2015 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2015. 1\u20133"},{"key":"5561_CR69","unstructured":"SFARDS. SFARDS new 28nm BTC & LTC dual-algorithm ASIC unveiled. http:\/\/www.sfards.com\/detail?id=26"},{"key":"5561_CR70","unstructured":"Bitcoin Wiki. ASIC. https:\/\/en.bitcoin.it\/wiki\/ASIC"},{"key":"5561_CR71","volume-title":"2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco","author":"M Miyazaki","year":"2002","unstructured":"Miyazaki M, Kao J, Chandrakasan A P. A 175mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture. In: 2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, 2002"},{"key":"5561_CR72","doi-asserted-by":"crossref","first-page":"696","DOI":"10.1109\/JSSC.2003.810054","volume":"38","author":"A Keshavarizi","year":"2003","unstructured":"Keshavarizi A, Narendra S, Bloechel B, et al. Forward body bias for microprocessors in 130nm technology generation and beyond. IEEE J Solid-State Circuits, 2003, 38: 696\u2013701","journal-title":"IEEE J Solid-State Circuits"},{"key":"5561_CR73","unstructured":"Soitec. Press release \u201cSoitec and Shin-Etsu Handotai announce Smart CutTM licensing extension and expanded technology cooperation\u201d. 2012. http:\/\/www.soitec.com\/en\/news\/press-releases\/soitec-and-shin-etsu-handotai-announcesmart-cut-licensing-extension-and-expanded-technology-cooperation-1079\/"},{"key":"5561_CR74","unstructured":"Shin-Etsu Handotai Co., Ltd. Ultra Thin Body and Buried oxide substrate supply chain. FD-SOI Workshop, Kyoto, 2013. http:\/\/www.soiconsortium.org\/fully-depleted-soi\/presentations\/june-2013\/Nobuhiko%20Noto%20-%20UTBB-%20Wafer SEH June2013.pdf"},{"key":"5561_CR75","unstructured":"Soitec. Press release \u201cSoitec and SunEdison enter into patent license agreement\u201d. 2013. http:\/\/www.soitec.com\/en-\/news\/press-releases\/soitec-and-sunedison-enter-into-patent-license-agreement-1390\/"},{"key":"5561_CR76","first-page":"1","volume-title":"2014 Symposium on VLSI Technology: Digest of Technical Papers, Honolulu","author":"K-I Seo","year":"2014","unstructured":"Seo K-I, Haran B, Gupta D, et al. A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI. In: 2014 Symposium on VLSI Technology: Digest of Technical Papers, Honolulu, 2014. 1\u20132"},{"key":"5561_CR77","first-page":"36","volume-title":"Proceedings of 2011 Symposium on VLSI Technology (VLSIT), Honolulu","author":"S-C Seo","year":"2011","unstructured":"Seo S-C, Edge L F, Kanakasabapathy S, et al. Full metal gate with borderless contact for 14 nm and beyond. In: Proceedings of 2011 Symposium on VLSI Technology (VLSIT), Honolulu, 2011. 36\u201337"},{"key":"5561_CR78","first-page":"1","volume-title":"2014 Symposium on VLSI Technology: Digest of Technical Papers, Honolulu","author":"S Kamohara","year":"2014","unstructured":"Kamohara S, Sugii N, Yamamoto Y, et al. Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era. In: 2014 Symposium on VLSI Technology: Digest of Technical Papers, Honolulu, 2014. 1\u20132"}],"container-title":["Science China Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-016-5561-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11432-016-5561-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-016-5561-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,7]],"date-time":"2019-09-07T01:32:48Z","timestamp":1567819968000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11432-016-5561-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4,25]]},"references-count":78,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2016,6]]}},"alternative-id":["5561"],"URL":"https:\/\/doi.org\/10.1007\/s11432-016-5561-5","relation":{},"ISSN":["1674-733X","1869-1919"],"issn-type":[{"value":"1674-733X","type":"print"},{"value":"1869-1919","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4,25]]},"article-number":"061402"}}