{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:49:48Z","timestamp":1761648588684},"reference-count":33,"publisher":"Springer Science and Business Media LLC","issue":"10","license":[{"start":{"date-parts":[[2018,8,21]],"date-time":"2018-08-21T00:00:00Z","timestamp":1534809600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Sci. China Inf. Sci."],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1007\/s11432-017-9394-y","type":"journal-article","created":{"date-parts":[[2018,8,24]],"date-time":"2018-08-24T01:24:03Z","timestamp":1535073843000},"update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Polar-coded forward error correction for MLC NAND flash memory"],"prefix":"10.1007","volume":"61","author":[{"given":"Haochuan","family":"Song","sequence":"first","affiliation":[]},{"given":"Jen-Chien","family":"Fu","sequence":"additional","affiliation":[]},{"given":"Shih-Jia","family":"Zeng","sequence":"additional","affiliation":[]},{"given":"Jin","family":"Sha","sequence":"additional","affiliation":[]},{"given":"Zaichen","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Xiaohu","family":"You","sequence":"additional","affiliation":[]},{"given":"Chuan","family":"Zhang","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,8,21]]},"reference":[{"key":"9394_CR1","first-page":"1412","volume":"18","author":"S Li","year":"2010","unstructured":"Li S, Zhang T. Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding. IEEE Trans VLSI Syst, 2010, 18: 1412\u20131420","journal-title":"IEEE Trans^VLSI Syst"},{"key":"9394_CR2","doi-asserted-by":"publisher","first-page":"195","DOI":"10.1186\/1687-6180-2012-195","volume":"2012","author":"J Kim","year":"2012","unstructured":"Kim J, Sung W. Low-energy error correction of NAND flash memory through soft-decision decoding. EURASIP J Adv Signal Process, 2012, 2012: 195","journal-title":"EURASIP J Adv Signal Process"},{"key":"9394_CR3","volume-title":"The bleak future of^NAND flash memory","author":"L M Grupp","year":"2012","unstructured":"Grupp L M, Davis J D, Swanson S. The bleak future of NAND flash memory. In: Proceedings of the 10th USENIX Conference on File and Storage Technologies, San Jose, 2012"},{"key":"9394_CR4","volume-title":"Non-Volatile Memory Workshop","author":"J Bellorado","year":"2013","unstructured":"Bellorado J, Yaakobi E. Signal processing and coding for non-volatile memories. Non-Volatile Memory Workshop, 2013. \n                    https:\/\/doi.org\/faculty.cs.tamu.edu\/ajiang\/NVMWTutorial.pdf"},{"key":"9394_CR5","doi-asserted-by":"publisher","first-page":"195","DOI":"10.1109\/JSSC.2008.2007154","volume":"44","author":"Y Li","year":"2009","unstructured":"Li Y, Lee S, Fong Y, et al. A 16 Gb 3-Bit per cell (X3) NAND flash memory on 56 nm technology with 8 MB\/s write rate. IEEE J Solid-State Circ, 2009, 44: 195\u2013207","journal-title":"IEEE J Solid-State Circ"},{"key":"9394_CR6","doi-asserted-by":"publisher","first-page":"929","DOI":"10.1109\/JSSC.2008.917559","volume":"43","author":"N Shibata","year":"2008","unstructured":"Shibata N, Maejima H, Isobe K, et al. A 70 nm 16 Gb 16-level-cell NAND flash memory. IEEE J Solid-State Circ, 2008, 43: 929\u2013937","journal-title":"IEEE J Solid-State Circ"},{"key":"9394_CR7","first-page":"246","volume-title":"Proceedings of IEEE International Solid-State Circuits Conference, San Francisco","author":"C Trinh","year":"2009","unstructured":"Trinh C, Shibata N, Nakano T, et al. A 5.6 MB\/s 64 Gb 4b\/cell NAND flash memory in 43 nm CMOS. In: Proceedings of IEEE International Solid-State Circuits Conference, San Francisco, 2009. 246\u2013247"},{"key":"9394_CR8","first-page":"1450","volume-title":"Proceedings of IEEE International Symposiuim on Circuits and Systems, Lisbon","author":"K C Ho","year":"2015","unstructured":"Ho K C, Chen C L, Liao Y C, et al. A 3.46 Gb\/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. In: Proceedings of IEEE International Symposiuim on Circuits and Systems, Lisbon, 2015. 1450\u20131453"},{"key":"9394_CR9","first-page":"429","volume":"58","author":"G Q Dong","year":"2011","unstructured":"Dong G Q, Xie N D, Zhang T. On the use of soft-decision error-correction codes in NAND flash memory. IEEE Trans Circ Syst I, 2011, 58: 429\u2013439","journal-title":"IEEE Trans Circ Syst I"},{"key":"9394_CR10","first-page":"7029","volume-title":"Proceedings of IEEE International Conference on Communications, Ottawa","author":"J Kim","year":"2012","unstructured":"Kim J, Lee D, Sung W. Performance of rate 0.96 (68254, 65536) EG-LDPC code for NAND flash memory error correction. In: Proceedings of IEEE International Conference on Communications, Ottawa, 2012. 7029\u20137033"},{"key":"9394_CR11","first-page":"201","volume-title":"Proceedings of IEEE International Symposium on Circuits and Systems, Melbourne","author":"Z Q Cui","year":"2014","unstructured":"Cui Z Q, Wang Z F, Huang X M. Multilevel error correction scheme for MLC flash memory. In: Proceedings of IEEE International Symposium on Circuits and Systems, Melbourne, 2014. 201\u2013204"},{"key":"9394_CR12","first-page":"94","volume-title":"Proceedings of IEEE Workshop on Signal Processing Systems, Washington","author":"B N Chen","year":"2008","unstructured":"Chen B N, Zhang X M, Wang Z F. Error correction for multi-level NAND flash memory using Reed-Solomon codes. In: Proceedings of IEEE Workshop on Signal Processing Systems, Washington, 2008. 94\u201399"},{"key":"9394_CR13","doi-asserted-by":"publisher","first-page":"022309","DOI":"10.1007\/s11432-017-9128-x","volume":"61","author":"Q Y Xu","year":"2018","unstructured":"Xu Q Y, Pan Z W, Liu N, et al. A complexity-reduced fast successive cancellation list decoder for polar codes. Sci China Inf Sci, 2018, 61: 022309","journal-title":"Sci China Inf Sci"},{"key":"9394_CR14","doi-asserted-by":"publisher","first-page":"102309","DOI":"10.1007\/s11432-015-5452-1","volume":"59","author":"Z Chen","year":"2016","unstructured":"Chen Z, Yin L G, Pei Y K, et al. CodeHop: physical layer error correction and encryption with LDPC-based code hopping. Sci China Inf Sci, 2016, 59: 102309","journal-title":"Sci China Inf Sci"},{"key":"9394_CR15","first-page":"1359","volume":"59","author":"C Zhang","year":"2012","unstructured":"Zhang C, Parhi K K. A network-efficient nonbinary QC-LDPC decoder architecture. IEEE Trans Circ Syst I, 2012, 59: 1359\u20131371","journal-title":"IEEE Trans Circ Syst I"},{"key":"9394_CR16","first-page":"116","volume":"57","author":"C Zhang","year":"2010","unstructured":"Zhang C, Wang Z F, Sha J, et al. Flexible LDPC decoder design for multigigabit-per-second applications. IEEE Trans Circ Syst I, 2010, 57: 116\u2013124","journal-title":"IEEE Trans Circ Syst I"},{"key":"9394_CR17","doi-asserted-by":"publisher","first-page":"3051","DOI":"10.1109\/TIT.2009.2021379","volume":"55","author":"E Ar\u0131kan","year":"2009","unstructured":"Ar\u0131kan E. Channel polarization: a method for constructing capacity-achieving codes for symmetric binary-input memoryless channels. IEEE Trans Inf Theory, 2009, 55: 3051\u20133073","journal-title":"IEEE Trans Inf Theory"},{"key":"9394_CR18","first-page":"3471","volume-title":"Proceedings of IEEE International Conference on Communications, Ottawa","author":"C Zhang","year":"2012","unstructured":"Zhang C, Yuan B, Parhi K K. Reduced-latency sc polar decoder architectures. In: Proceedings of IEEE International Conference on Communications, Ottawa, 2012. 3471\u20133475"},{"key":"9394_CR19","doi-asserted-by":"publisher","first-page":"2429","DOI":"10.1109\/TSP.2013.2251339","volume":"61","author":"C Zhang","year":"2013","unstructured":"Zhang C, Parhi K K. Low-latency sequential and overlapped architectures for successive cancellation polar decoder. IEEE Trans Signal Process, 2013, 61: 2429\u20132441","journal-title":"IEEE Trans Signal Process"},{"key":"9394_CR20","first-page":"115","volume":"61","author":"C Zhang","year":"2014","unstructured":"Zhang C, Parhi K K. Latency analysis and architecture design of simplified SC polar decoders. IEEE Trans Circ Syst II, 2014, 61: 115\u2013119","journal-title":"IEEE Trans Circ Syst II"},{"key":"9394_CR21","first-page":"209","volume-title":"Proceedings of IEEE International Symposium on Circuits and Systems, Melbourne","author":"C Zhang","year":"2014","unstructured":"Zhang C, You X, Sha J. Hardware architecture for list successive cancellation polar decoder. In: Proceedings of IEEE International Symposium on Circuits and Systems, Melbourne, 2014. 209\u2013212"},{"key":"9394_CR22","first-page":"3032","volume-title":"Proceedings of IEEE International Symposiuim on Circuits and Systems, Lisbon","author":"C Zhang","year":"2015","unstructured":"Zhang C, Yang J, You X, et al. Pipelined implementations of polar encoder and feed-back part for SC polar decoder. In: Proceedings of IEEE International Symposiuim on Circuits and Systems, Lisbon, 2015. 3032\u20133035"},{"key":"9394_CR23","volume-title":"BLER performance of list decoding for enhanced turbo codes. 3GPP TSG RAN WG1 Meeting #87","author":"AccelerComm.","year":"2016","unstructured":"AccelerComm. BLER performance of list decoding for enhanced turbo codes. 3GPP TSG RAN WG1 Meeting #87, 2016. https:\/\/eprints.soton.ac.uk\/404002\/1\/R1-1612308.pdf"},{"key":"9394_CR24","volume-title":"In: Proceedings of International Conference on Computing, Networking and Communications, Garden Grove","author":"Y Li","year":"2015","unstructured":"Li Y, Alhussien H, Haratsch E, et al. A study of polar codes for MLC NAND flash memories. In: Proceedings of International Conference on Computing, Networking and Communications, Garden Grove, 2015. 608\u2013612"},{"key":"9394_CR25","first-page":"1","volume":"4","author":"G Atwood","year":"1997","unstructured":"Atwood G, Fazio A, Mills D, et al. Intel strataflash memory technology overview. Intel Technol J, 1997, 4: 1\u20138","journal-title":"Intel Technol J"},{"key":"9394_CR26","volume-title":"Error patterns in^MLC NAND flash memory: measurement, characterization, and analysis. In: Proceedings of the Conference on Design","author":"Y Cai","year":"2012","unstructured":"Cai Y, Haratsch E F, Mutlu O, et al. Error patterns in MLC NAND flash memory: measurement, characterization, and analysis. In: Proceedings of the Conference on Design, Automation and Test in Europe, Dresden, 2012. 521\u2013526"},{"key":"9394_CR27","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2011.5946819","volume-title":"Hardware architectures for successive cancellation decoding of polar codes. In: Proceedings of IEEE International Conference on Acoustics","author":"C Leroux","year":"2011","unstructured":"Leroux C, Tal I, Vardy A, et al. Hardware architectures for successive cancellation decoding of polar codes. In: Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, Czech, 2011. 1665\u20131668"},{"key":"9394_CR28","doi-asserted-by":"publisher","DOI":"10.1109\/WCSP.2016.7752700","volume-title":"Polar code-based error correction code scheme for NAND flash memory applications","author":"H C Song","year":"2016","unstructured":"Song H C, Zhang C, Zhang S Q, et al. Polar code-based error correction code scheme for NAND flash memory applications. In: Proceedings of International Conference onWireless Communications and Signal Processing, Yangzhou, 2016"},{"key":"9394_CR29","volume-title":"Soft information for^LDPC decoding in flash: mutual-information optimized quantization","author":"J D Wang","year":"2011","unstructured":"Wang J D, Courtade T, Shankar H, et al. Soft information for LDPC decoding in flash: mutual-information optimized quantization. In: Proceedings of IEEE Global Telecommunications Conference, Kathmandu, 2011"},{"key":"9394_CR30","volume-title":"Mutual-information optimized quantization for LDPC decoding of accurately modeled flash data","author":"J D Wang","year":"2012","unstructured":"Wang J D, Dong G Q, Zhang T, et al. Mutual-information optimized quantization for LDPC decoding of accurately modeled flash data. 2012. ArXiv:1202.1325"},{"key":"9394_CR31","first-page":"9","volume-title":"Proceedings of IEEE International Reliability Physics Symposium, Phoenix","author":"N Mielke","year":"2008","unstructured":"Mielke N, Marquart T, Wu N, et al. Bit error rate in NAND flash memories. In: Proceedings of IEEE International Reliability Physics Symposium, Phoenix, 2008. 9\u201319"},{"key":"9394_CR32","doi-asserted-by":"publisher","first-page":"1227","DOI":"10.1109\/JSSC.2009.2014027","volume":"44","author":"K Takeuchi","year":"2009","unstructured":"Takeuchi K. Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30 nm low-power high-speed solid-state drives (SSD). IEEE J Solid-State Circ, 2009, 44: 1227\u20131234","journal-title":"IEEE J Solid-State Circ"},{"key":"9394_CR33","volume-title":"LDPC decoding for 802.22 standard","author":"Y Blankenship","year":"2007","unstructured":"Blankenship Y, Kuffner S. LDPC decoding for 802.22 standard. IEEE P802.22, 2007"}],"container-title":["Science China Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-017-9394-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11432-017-9394-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-017-9394-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,20]],"date-time":"2019-08-20T19:22:29Z","timestamp":1566328949000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11432-017-9394-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,8,21]]},"references-count":33,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2018,10]]}},"alternative-id":["9394"],"URL":"https:\/\/doi.org\/10.1007\/s11432-017-9394-y","relation":{},"ISSN":["1674-733X","1869-1919"],"issn-type":[{"value":"1674-733X","type":"print"},{"value":"1869-1919","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,8,21]]},"assertion":[{"value":"5 December 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 February 2018","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 February 2018","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 August 2018","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}],"article-number":"102307"}}