{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,17]],"date-time":"2026-08-17T15:53:04Z","timestamp":1786981984984,"version":"build-2736575974"},"reference-count":35,"publisher":"Springer Science and Business Media LLC","issue":"8","license":[{"start":{"date-parts":[[2023,7,4]],"date-time":"2023-07-04T00:00:00Z","timestamp":1688428800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,7,4]],"date-time":"2023-07-04T00:00:00Z","timestamp":1688428800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Sci. China Inf. Sci."],"published-print":{"date-parts":[[2023,8]]},"DOI":"10.1007\/s11432-022-3627-8","type":"journal-article","created":{"date-parts":[[2023,7,11]],"date-time":"2023-07-11T07:01:51Z","timestamp":1689058911000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":11,"title":["Design memristor-based computing-in-memory for AI accelerators considering the interplay between devices, circuits, and system"],"prefix":"10.1007","volume":"66","author":[{"given":"Junjie","family":"An","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Linfang","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wang","family":"Ye","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Weizeng","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hanghang","family":"Gao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhi","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhidao","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jinghui","family":"Tian","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jianfeng","family":"Gao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chunmeng","family":"Dou","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Qi","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2023,7,4]]},"reference":[{"key":"3627_CR1","doi-asserted-by":"crossref","unstructured":"Patterson D. 50 years of computer architecture: from the mainframe CPU to the domain-specific TPU and the open RISC-V instruction set. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2018. 27\u201331","DOI":"10.1109\/ISSCC.2018.8310168"},{"key":"3627_CR2","doi-asserted-by":"publisher","first-page":"46","DOI":"10.1109\/MSSC.2017.2745798","volume":"9","author":"V Sze","year":"2017","unstructured":"Sze V. Designing hardware for machine learning: the important role played by circuit designers. IEEE Solid-State Circuits Mag, 2017, 9: 46\u201354","journal-title":"IEEE Solid-State Circuits Mag"},{"key":"3627_CR3","doi-asserted-by":"publisher","first-page":"216","DOI":"10.1038\/s41928-018-0059-3","volume":"1","author":"X Xu","year":"2018","unstructured":"Xu X, Ding Y, Hu S X, et al. Scaling for edge inference of deep neural networks. Nat Electron, 2018, 1: 216\u2013222","journal-title":"Nat Electron"},{"key":"3627_CR4","doi-asserted-by":"publisher","first-page":"436","DOI":"10.1038\/nature14539","volume":"521","author":"Y LeCun","year":"2015","unstructured":"LeCun Y, Bengio Y, Hinton G. Deep learning. Nature, 2015, 521: 436\u2013444","journal-title":"Nature"},{"key":"3627_CR5","unstructured":"Amodei D, Hernandez D, Sastry G, et al. AI and compute. 2019. https:\/\/openai.com\/blog\/ai-and-compute\/"},{"key":"3627_CR6","doi-asserted-by":"crossref","unstructured":"Dou C, Xu X, Zhang X, et al. Enabling RRAM-based brain-inspired computation by co-design of device, circuit, and system. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2021. 21\u201324","DOI":"10.1109\/IEDM19574.2021.9720546"},{"key":"3627_CR7","doi-asserted-by":"publisher","first-page":"43","DOI":"10.1109\/MSSC.2016.2546199","volume":"8","author":"S Yu","year":"2016","unstructured":"Yu S, Chen P-Y. Emerging memory technologies: recent trends and prospects. IEEE Solid-State Circuits Mag, 2016, 8: 43\u201356","journal-title":"IEEE Solid-State Circuits Mag"},{"key":"3627_CR8","doi-asserted-by":"publisher","first-page":"22","DOI":"10.1038\/s41928-017-0006-8","volume":"1","author":"M A Zidan","year":"2018","unstructured":"Zidan M A, Strachan J P, Lu W D. The future of electronics based on memristive systems. Nat Electron, 2018, 1: 22\u201329","journal-title":"Nat Electron"},{"key":"3627_CR9","doi-asserted-by":"publisher","first-page":"333","DOI":"10.1038\/s41928-018-0092-2","volume":"1","author":"D Ielmini","year":"2018","unstructured":"Ielmini D, Wong H S P. In-memory computing with resistive switching devices. Nat Electron, 2018, 1: 333\u2013343","journal-title":"Nat Electron"},{"key":"3627_CR10","doi-asserted-by":"crossref","unstructured":"Dou C-M, Chen W-H, Xue C-X, et al. Nonvolatile circuits-devices interaction for memory, logic and artificial intelligence. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2018. 171\u2013172","DOI":"10.1109\/VLSIT.2018.8510627"},{"key":"3627_CR11","doi-asserted-by":"crossref","unstructured":"Wan W, Kubendran R, Eryilmaz S B, et al. A 74 TMACS\/W CMOS-RRAM neurosynaptic core with dynamically reconfigurable dataflow and in-situ transposable weights for probabilistic graphical models. In: Proceedings of IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, 2020. 498\u2013500","DOI":"10.1109\/ISSCC19947.2020.9062979"},{"key":"3627_CR12","doi-asserted-by":"publisher","first-page":"1105","DOI":"10.1109\/JSSC.2020.3045369","volume":"56","author":"Z Li","year":"2021","unstructured":"Li Z, Wang Z, Xu L, et al. RRAM-DNN: an RRAM and model-compression empowered all-weights-on-chip DNN accelerator. IEEE J Solid-State Circuits, 2021, 56: 1105\u20131115","journal-title":"IEEE J Solid-State Circuits"},{"key":"3627_CR13","doi-asserted-by":"crossref","unstructured":"Su F, Chen W-H, Xia L, et al. A 462GOPs\/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2017. 260\u2013261","DOI":"10.23919\/VLSIC.2017.8008585"},{"key":"3627_CR14","doi-asserted-by":"crossref","unstructured":"Mochida R, Kouno K, Hayata Y, et al. A 4M synapses integrated analog ReRAM based 66.5 TOPS\/W neural-network processor with cell current controlled writing and flexible network architecture. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2018. 175\u2013176","DOI":"10.1109\/VLSIT.2018.8510676"},{"key":"3627_CR15","doi-asserted-by":"publisher","first-page":"2726","DOI":"10.1109\/TCSI.2018.2812419","volume":"65","author":"Y Jiang","year":"2018","unstructured":"Jiang Y, Huang P, Zhu D, et al. Design and hardware implementation of neuromorphic systems with RRAM synapses and threshold-controlled neurons for pattern recognition. IEEE Trans Circuits Syst I, 2018, 65: 2726\u20132738","journal-title":"IEEE Trans Circuits Syst I"},{"key":"3627_CR16","doi-asserted-by":"publisher","first-page":"290","DOI":"10.1038\/s41928-019-0270-x","volume":"2","author":"F Cai","year":"2019","unstructured":"Cai F, Correll J M, Lee S H, et al. A fully integrated reprogrammable memristor-CMOS system for efficient multiply-accumulate operations. Nat Electron, 2019, 2: 290\u2013299","journal-title":"Nat Electron"},{"key":"3627_CR17","doi-asserted-by":"publisher","first-page":"420","DOI":"10.1038\/s41928-019-0288-0","volume":"2","author":"W H Chen","year":"2019","unstructured":"Chen W H, Dou C, Li K X, et al. CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors. Nat Electron, 2019, 2: 420\u2013428","journal-title":"Nat Electron"},{"key":"3627_CR18","doi-asserted-by":"crossref","unstructured":"Liu Q, Gao B, Yao P, et al. A fully integrated analog ReRAM based 78.4 TOPS\/W compute-in-memory chip with fully parallel MAC computing. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2020. 500\u2013502","DOI":"10.1109\/ISSCC19947.2020.9062953"},{"key":"3627_CR19","doi-asserted-by":"crossref","unstructured":"Xue C-X, Hung J-M, Kao H-Y, et al. A 22 nm 4 Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS\/W for tiny AI edge devices. In: Proceedings of IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, 2021. 245\u2013247","DOI":"10.1109\/ISSCC42613.2021.9365769"},{"key":"3627_CR20","first-page":"2932","volume":"68","author":"K Zhou","year":"2021","unstructured":"Zhou K, Zhao C, Fang J, et al. An energy efficient computing-in-memory accelerator with 1T2R cell and fully analog processing for edge AI applications. IEEE Trans Circuits Syst II, 2021, 68: 2932\u20132936","journal-title":"IEEE Trans Circuits Syst II"},{"key":"3627_CR21","doi-asserted-by":"crossref","unstructured":"Song T, Chen X, Zhang X, et al. BRAHMS: beyond conventional RRAM-based neural network accelerators using hybrid analog memory system. In: Proceedings of the 58th ACM\/IEEE Design Automation Conference (DAC), San Francisco, 2021. 1033\u20131038","DOI":"10.1109\/DAC18074.2021.9586247"},{"key":"3627_CR22","doi-asserted-by":"publisher","first-page":"68","DOI":"10.1109\/JSSC.2021.3101209","volume":"57","author":"J H Yoon","year":"2022","unstructured":"Yoon J H, Chang M, Khwa W S, et al. A 40-nm, 64-Kb, 56.67 TOPS\/W voltage-sensing computing-in-memory\/digital RRAM macro supporting iterative write with verification and online read-disturb detection. IEEE J Solid-State Circuits, 2022, 57: 68\u201379","journal-title":"IEEE J Solid-State Circuits"},{"key":"3627_CR23","doi-asserted-by":"crossref","unstructured":"Hung J-M, Huang Y-H, Huang S-P, et al. An 8-Mb DC-current-free binary-to-8b precision ReRAM nonvolatile computing-inmemory macro using time-space-readout with 1286.4\u201321.6TOPS\/W for edge-AI devices. In: Proceedings of IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, 2022. 1\u20133","DOI":"10.1109\/ISSCC42614.2022.9731715"},{"key":"3627_CR24","doi-asserted-by":"publisher","first-page":"2868","DOI":"10.1109\/JSSC.2022.3163197","volume":"57","author":"W Li","year":"2022","unstructured":"Li W, Sun X, Huang S, et al. A 40-nm MLC-RRAM compute-in-memory macro with sparsity control, on-chip write-verify, and temperature-independent ADC references. IEEE J Solid-State Circuits, 2022, 57: 2868\u20132877","journal-title":"IEEE J Solid-State Circuits"},{"key":"3627_CR25","doi-asserted-by":"publisher","first-page":"371","DOI":"10.1038\/s41928-020-0435-7","volume":"3","author":"W Zhang","year":"2020","unstructured":"Zhang W, Gao B, Tang J, et al. Neuro-inspired computing chips. Nat Electron, 2020, 3: 371\u2013382","journal-title":"Nat Electron"},{"key":"3627_CR26","doi-asserted-by":"publisher","first-page":"160404","DOI":"10.1007\/s11432-020-3227-1","volume":"64","author":"X Q Zou","year":"2021","unstructured":"Zou X Q, Xu S, Chen X M, et al. Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology. Sci China Inf Sci, 2021, 64: 160404","journal-title":"Sci China Inf Sci"},{"key":"3627_CR27","doi-asserted-by":"publisher","first-page":"31","DOI":"10.1109\/MCAS.2021.3092533","volume":"21","author":"S Yu","year":"2021","unstructured":"Yu S, Jiang H, Huang S, et al. Compute-in-memory chips for deep learning: recent trends and prospects. IEEE Circuits Syst Mag, 2021, 21: 31\u201356","journal-title":"IEEE Circuits Syst Mag"},{"key":"3627_CR28","doi-asserted-by":"publisher","first-page":"504","DOI":"10.1038\/s41586-022-04992-8","volume":"608","author":"W Wan","year":"2022","unstructured":"Wan W, Kubendran R, Schaefer C, et al. A compute-in-memory chip based on resistive random-access memory. Nature, 2022, 608: 504\u2013512","journal-title":"Nature"},{"key":"3627_CR29","doi-asserted-by":"crossref","unstructured":"Zhu H, Jiao B, Zhang J, et al. COMB-MCM: computing-on-memory-boundary NN processor with bipolar bitwise sparsity optimization for scalable multi-chiplet-module edge machine learning. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2022. 1\u20133","DOI":"10.1109\/ISSCC42614.2022.9731657"},{"key":"3627_CR30","doi-asserted-by":"publisher","first-page":"677","DOI":"10.1109\/TNANO.2017.2703985","volume":"16","author":"J M Portal","year":"2017","unstructured":"Portal J M, Bocquet M, Onkaraiah S, et al. Design and simulation of a 128 kb embedded nonvolatile memory based on a hybrid RRAM (HfO2)\/28 nm FDSOI CMOS technology. IEEE Trans Nanotechnol, 2017, 16: 677\u2013686","journal-title":"IEEE Trans Nanotechnol"},{"key":"3627_CR31","doi-asserted-by":"publisher","first-page":"3355","DOI":"10.1557\/adv.2016.377","volume":"1","author":"K Beckmann","year":"2016","unstructured":"Beckmann K, Holt J, Manem H, et al. Nanoscale hafnium oxide RRAM devices exhibit pulse dependent behavior and multilevel resistance capability. MRS Adv, 2016, 1: 3355\u20133360","journal-title":"MRS Adv"},{"key":"3627_CR32","unstructured":"Sekar D C, Bateman B, Raghuram U, et al. Technology and circuit optimization of resistive RAM for low-power, reproducible operation. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014. 21\u201324"},{"key":"3627_CR33","unstructured":"Wan W, Kubendran R, Schaefer C, et al. Edge AI without compromise: efficient, versatile and accurate neurocomputing in resistive random-access memory. 2021. ArXiv:2108.07879"},{"key":"3627_CR34","doi-asserted-by":"crossref","unstructured":"Xue X Y, Jian W X, Yang J G, et al. A 0.13 \u00b5m 8 Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction. In: Proceedings of IEEE Symposium on VLSI Circuits, Honolulu, 2012. 42\u201343","DOI":"10.1109\/VLSIC.2012.6243780"},{"key":"3627_CR35","doi-asserted-by":"crossref","unstructured":"Jain P, Arslan U, Sekhar M, et al. A 3.6 Mb 10.1 Mb\/mm2 embedded non-volatile ReRAM macro in 22 nm FinFET technology with adaptive forming\/set\/reset schemes yielding down to 0.5 V with sensing time of 5 ns at 0.7 V. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2019. 212\u2013214","DOI":"10.1109\/ISSCC.2019.8662393"}],"container-title":["Science China Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-022-3627-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11432-022-3627-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-022-3627-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,18]],"date-time":"2024-09-18T16:22:01Z","timestamp":1726676521000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11432-022-3627-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,7,4]]},"references-count":35,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2023,8]]}},"alternative-id":["3627"],"URL":"https:\/\/doi.org\/10.1007\/s11432-022-3627-8","relation":{},"ISSN":["1674-733X","1869-1919"],"issn-type":[{"value":"1674-733X","type":"print"},{"value":"1869-1919","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,7,4]]},"assertion":[{"value":"18 June 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"2 September 2022","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"17 November 2022","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"4 July 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}],"article-number":"182404"}}