{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T21:11:23Z","timestamp":1771535483354,"version":"3.50.1"},"reference-count":27,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T00:00:00Z","timestamp":1734393600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T00:00:00Z","timestamp":1734393600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Sci. China Inf. Sci."],"published-print":{"date-parts":[[2025,1]]},"DOI":"10.1007\/s11432-023-3965-1","type":"journal-article","created":{"date-parts":[[2024,12,18]],"date-time":"2024-12-18T22:13:32Z","timestamp":1734560012000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Software-defined process-near-memory architecture using 3D hybrid bonding integration"],"prefix":"10.1007","volume":"68","author":[{"given":"Anlin","family":"Xu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chenchen","family":"Deng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianfeng","family":"Zhu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yao","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shaojun","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leibo","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2024,12,17]]},"reference":[{"key":"3965_CR1","first-page":"8","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference","author":"L Su","year":"2023","unstructured":"Su L, Naffziger S. Innovation for the next decade of compute efficiency. In: Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, 2023. 8\u201312"},{"key":"3965_CR2","first-page":"20","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference","author":"G Moore","year":"2003","unstructured":"Moore G. No exponential is forever: but \u201cforever\u201d can be delayed! In: Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, 2003. 20\u201323"},{"key":"3965_CR3","doi-asserted-by":"publisher","first-page":"48","DOI":"10.1145\/3282307","volume":"62","author":"J L Hennessy","year":"2019","unstructured":"Hennessy J L, Patterson D A. A new golden age for computer architecture. Commun ACM, 2019, 62: 48\u201360","journal-title":"Commun ACM"},{"key":"3965_CR4","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3357375","volume":"52","author":"L Liu","year":"2019","unstructured":"Liu L, Zhu J, Li Z, et al. A survey of coarse-grained reconfigurable architecture and design. ACM Comput Surv, 2019, 52: 1\u201339","journal-title":"ACM Comput Surv"},{"key":"3965_CR5","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-19-6994-2","volume-title":"Software Defined Chips: Volume I","author":"S Wei","year":"2022","unstructured":"Wei S, Liu L, Zhu J, et al. Software Defined Chips: Volume I. Berlin: Springer, 2022"},{"key":"3965_CR6","first-page":"1027","volume-title":"Proceedings of the 48th Annual International Symposium on Computer Architecture (ISCA)","author":"G Gobieski","year":"2021","unstructured":"Gobieski G, Atli A, Mai K, et al. Snafu: an ultra-low-power, energy-minimal CGRA generation framework and architecture. In: Proceedings of the 48th Annual International Symposium on Computer Architecture (ISCA), 2021. 1027\u20131040"},{"key":"3965_CR7","first-page":"381","volume":"65","author":"L Liu","year":"2018","unstructured":"Liu L, Li Z, Yang C, et al. HReA: an energy-efficient embedded dynamically reconfigurable fabric for 13-dwarfs processing. IEEE Trans Circ Syst II, 2018, 65: 381\u2013385","journal-title":"IEEE Trans Circ Syst II"},{"key":"3965_CR8","first-page":"412","volume-title":"Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)","author":"C Torng","year":"2021","unstructured":"Torng C, Pan P, Ou Y, et al. Ultra-elastic CGRAs for irregular loop specialization. In: Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, 2021. 412\u2013425"},{"key":"3965_CR9","doi-asserted-by":"publisher","first-page":"48","DOI":"10.1145\/3361682","volume":"63","author":"W J Dally","year":"2020","unstructured":"Dally W J, Turakhia Y, Han S. Domain-specific hardware accelerators. Commun ACM, 2020, 63: 48\u201357","journal-title":"Commun ACM"},{"key":"3965_CR10","doi-asserted-by":"publisher","first-page":"191","DOI":"10.1109\/JSSC.2014.2360379","volume":"50","author":"D U Lee","year":"2015","unstructured":"Lee D U, Kim K W, Kim K W, et al. A 1.2 V 8 Gb 8-channel 128 GB\/s high-bandwidth memory (HBM) stacked DRAM with effective I\/O test circuits. IEEE J Solid-State Circ, 2015, 50: 191\u2013203","journal-title":"IEEE J Solid-State Circ"},{"key":"3965_CR11","doi-asserted-by":"publisher","first-page":"256","DOI":"10.1109\/JSSC.2022.3193354","volume":"58","author":"M J Park","year":"2023","unstructured":"Park M J, Lee J, Cho K, et al. A 192-Gb 12-High 896-GB\/s HBM3 DRAM with a TSV auto-calibration scheme and machine-learning-based layout optimization. IEEE J Solid-State Circ, 2023, 58: 256\u2013269","journal-title":"IEEE J Solid-State Circ"},{"key":"3965_CR12","doi-asserted-by":"publisher","first-page":"529","DOI":"10.1038\/s41565-020-0655-z","volume":"15","author":"A Sebastian","year":"2020","unstructured":"Sebastian A, Le Gallo M, Khaddam-Aljameh R, et al. Memory devices and applications for in-memory computing. Nat Nanotechnol, 2020, 15: 529\u2013544","journal-title":"Nat Nanotechnol"},{"key":"3965_CR13","doi-asserted-by":"publisher","first-page":"221402","DOI":"10.1007\/s11432-021-3327-7","volume":"64","author":"C D Cheng","year":"2021","unstructured":"Cheng C D, Tiw P J, Cai Y M, et al. In-memory computing with emerging nonvolatile memory devices. Sci China Inf Sci, 2021, 64: 221402","journal-title":"Sci China Inf Sci"},{"key":"3965_CR14","volume-title":"Proceedings of the IEEE International Electron Devices (IEDM)","author":"F Bai","year":"2020","unstructured":"Bai F, Jiang X, Wang S, et al. A stacked embedded DRAM array for LPDDR4\/4X using hybrid bonding 3D integration with 34 GB\/s\/1 Gb 0.88 pJ\/b logic-to-memory interface. In: Proceedings of the IEEE International Electron Devices (IEDM), San Francisco, 2020"},{"key":"3965_CR15","doi-asserted-by":"publisher","first-page":"110","DOI":"10.1109\/LSSC.2022.3171862","volume":"5","author":"X Jiang","year":"2022","unstructured":"Jiang X, Zuo F, Wang S, et al. A 1596-GB\/s 48-Gb stacked embedded DRAM 384-core SoC with hybrid bonding integration. IEEE Solid-State Circ Lett, 2022, 5: 110\u2013113","journal-title":"IEEE Solid-State Circ Lett"},{"key":"3965_CR16","first-page":"1","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC)","author":"D Niu","year":"2022","unstructured":"Niu D, Li S, Wang Y, et al. 184QPS\/W 64 Mb\/mm23D logic-to-DRAM hybrid bonding with process-near-memory engine for recommendation system. In: Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2022. 1\u20133"},{"key":"3965_CR17","first-page":"75","volume-title":"Proceedings of the International Symposium on Code Generation and Optimization","author":"C Lattner","year":"2004","unstructured":"Lattner C, Adve V. LLVM: a compilation framework for lifelong program analysis & transformation. In: Proceedings of the International Symposium on Code Generation and Optimization, San Jose, 2004. 75\u201386"},{"key":"3965_CR18","doi-asserted-by":"publisher","first-page":"1284","DOI":"10.1145\/2228360.2228600","volume-title":"Proceedings of the 49th Annual Design Automation Conference","author":"M Hamzeh","year":"2012","unstructured":"Hamzeh M, Shrivastava A, Vrudhula S. EPIMap: using epimorphism to map applications on CGRAs. In: Proceedings of the 49th Annual Design Automation Conference, San Francisco, 2012. 1284\u20131291"},{"key":"3965_CR19","volume-title":"Gurobi optimization reference manual","author":"Gurobi Optimization LLC","year":"2021","unstructured":"Gurobi Optimization LLC. Gurobi optimization reference manual. 2021. https:\/\/docs.gurobi.com\/projects\/optimizer\/en\/11.0\/"},{"key":"3965_CR20","first-page":"1","volume-title":"Proceedings of the 55th ACM\/ESDA\/IEEE Design Automation Conference (DAC)","author":"S Chin","year":"2018","unstructured":"Chin S, Anderson J. An architecture-agnostic integer linear programming approach to CGRA mapping. In: Proceedings of the 55th ACM\/ESDA\/IEEE Design Automation Conference (DAC), San Francisco, 2018. 1\u20136"},{"key":"3965_CR21","first-page":"1","volume-title":"Proceedings of the 55th ACM\/ESDA\/IEEE Design Automation Conference (DAC)","author":"S Dave","year":"2018","unstructured":"Dave S, Balasubramanian M, Shrivastava A. RAMP: resource-aware mapping for CGRAs. In: Proceedings of the 55th ACM\/ESDA\/IEEE Design Automation Conference (DAC), San Francisco, 2018. 1\u20136"},{"key":"3965_CR22","first-page":"381","volume-title":"Proceedings of the 38th International Conference on Computer Design (ICCD)","author":"C Tan","year":"2020","unstructured":"Tan C, Xie C, Li A, et al. OpenCGRA: an open-source unified framework for modeling, testing, and evaluating CGRAs. In: Proceedings of the 38th International Conference on Computer Design (ICCD), Hartford, 2020. 381\u2013388"},{"key":"3965_CR23","first-page":"1041","volume-title":"Proceedings of the 48th Annual International Symposium on Computer Architecture (ISCA)","author":"Y Zhang","year":"2021","unstructured":"Zhang Y, Zhang N, Zhao T, et al. SARA: scaling a reconfigurable dataflow accelerator. In: Proceedings of the 48th Annual International Symposium on Computer Architecture (ISCA), Valencia, 2021. 1041\u20131054"},{"key":"3965_CR24","first-page":"236","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC)","author":"H Jia","year":"2021","unstructured":"Jia H, Ozatay M, Tang Y, et al. A programmable neural-network inference accelerator based on scalable in-memory computing. In: Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2021. 236\u2013238"},{"key":"3965_CR25","first-page":"1","volume-title":"Proceedings of the IEEE Hot Chips Symposium (HCS)","author":"J Choquette","year":"2020","unstructured":"Choquette J, Gandhi W. Nvidia A100 GPU: performance & innovation for GPU computing. In: Proceedings of the IEEE Hot Chips Symposium (HCS), Palo Alto, 2020. 1\u201343"},{"key":"3965_CR26","first-page":"350","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC)","author":"Y Kwon","year":"2021","unstructured":"Kwon Y, Lee S, Kwon S, et al. A 20 nm 6 GB function-in-memory DRAM, based on HBM2 with a 1.2TFLOPS programmable computing unit using bank-level parallelism, for machine learning applications. In: Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2021. 350\u2013351"},{"key":"3965_CR27","volume-title":"Technical reference manual for 66AK2G1X multicore DSP+Arm\u00ae KeyStone II System-on-Chip(SoC)","author":"Texas Instruments","year":"2019","unstructured":"Texas Instruments. Technical reference manual for 66AK2G1X multicore DSP+Arm\u00ae KeyStone II System-on-Chip(SoC). 2019. https:\/\/www.ti.com\/documentviewer\/66ak2g12\/datasheet"}],"container-title":["Science China Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-023-3965-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11432-023-3965-1","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-023-3965-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T20:28:48Z","timestamp":1771532928000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11432-023-3965-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,17]]},"references-count":27,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2025,1]]}},"alternative-id":["3965"],"URL":"https:\/\/doi.org\/10.1007\/s11432-023-3965-1","relation":{},"ISSN":["1674-733X","1869-1919"],"issn-type":[{"value":"1674-733X","type":"print"},{"value":"1869-1919","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,12,17]]},"assertion":[{"value":"2 September 2023","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 November 2023","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 February 2024","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"17 December 2024","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}],"article-number":"112402"}}