{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T16:39:18Z","timestamp":1775666358774,"version":"3.50.1"},"reference-count":38,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2025,1,15]],"date-time":"2025-01-15T00:00:00Z","timestamp":1736899200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,1,15]],"date-time":"2025-01-15T00:00:00Z","timestamp":1736899200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Sci. China Inf. Sci."],"published-print":{"date-parts":[[2025,2]]},"DOI":"10.1007\/s11432-024-4078-1","type":"journal-article","created":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T09:37:49Z","timestamp":1737193069000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["A monolithic 3D IGZO-RRAM-SRAM-integrated architecture for robust and efficient compute-in-memory enabling equivalent-ideal device metrics"],"prefix":"10.1007","volume":"68","author":[{"given":"Shengzhe","family":"Yan","sequence":"first","affiliation":[]},{"given":"Zhaori","family":"Cong","sequence":"additional","affiliation":[]},{"given":"Zi","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Zhuoyu","family":"Dai","sequence":"additional","affiliation":[]},{"given":"Zeyu","family":"Guo","sequence":"additional","affiliation":[]},{"given":"Zhihang","family":"Qian","sequence":"additional","affiliation":[]},{"given":"Xufan","family":"Li","sequence":"additional","affiliation":[]},{"given":"Xu","family":"Zheng","sequence":"additional","affiliation":[]},{"given":"Chuanke","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Nianduan","family":"Lu","sequence":"additional","affiliation":[]},{"given":"Chunmeng","family":"Dou","sequence":"additional","affiliation":[]},{"given":"Guanhua","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Xiaoxin","family":"Xu","sequence":"additional","affiliation":[]},{"given":"Di","family":"Geng","sequence":"additional","affiliation":[]},{"given":"Jinshan","family":"Yue","sequence":"additional","affiliation":[]},{"given":"Lingfei","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Ling","family":"Li","sequence":"additional","affiliation":[]},{"given":"Ming","family":"Liu","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,1,15]]},"reference":[{"key":"4078_CR1","first-page":"252","volume-title":"Proceedings of IEEE International Solid-State Circuits Conference (ISSCC)","author":"Y-D Chih","year":"2021","unstructured":"Chih Y-D, Lee P-H, Fujiwara H, et al. 16.4 An 89 TOPS\/W and 16.3 TOPS\/mm2 all-digital SRAM-based full-precision compute-in memory macro in 22nm for machine-learning edge applications. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2021. 252\u2013254"},{"key":"4078_CR2","first-page":"1","volume-title":"Proceedings of IEEE International Solid-State Circuits Conference(ISSCC)","author":"F Tu","year":"2022","unstructured":"Tu F, Wang Y, Wu Z, et al. A 28nm 29.2 TFLOPS\/W BF16 and 36.5 TOPS\/W INT8 reconfigurable digital CIM processor with unified FP\/INT pipeline and bitwise in-memory booth multiplication for cloud deep learning acceleration. In: Proceedings of IEEE International Solid-State Circuits Conference(ISSCC), 2022. 1\u20133"},{"key":"4078_CR3","volume-title":"Proceedings of IEEE International Solid-State Circuits Conference (ISSCC)","author":"J Yue","year":"2023","unstructured":"Yue J, He C, Wang Z, et al. A 28nm 16.9-300TOPS\/W computing-in-memory processor supporting floating-point NN inference\/training with intensive-CIM sparse-digital architecture. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2023"},{"key":"4078_CR4","volume-title":"Proceedings of IEEE Symposium on VLSI Circuits","author":"J Yang","year":"2020","unstructured":"Yang J, Xue X, Xu X, et al. A 28nm 1.5 Mb embedded 1T2R RRAM with 14.8 Mb\/mm2 using sneaking current suppression and compensation techniques. In: Proceedings of IEEE Symposium on VLSI Circuits, 2020"},{"key":"4078_CR5","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM)","author":"X Duan","year":"2021","unstructured":"Duan X, Huang K, Feng J, et al. Novel vertical channel-all-around (CAA) IGZO FETs for 2T0C DRAM with high density beyond 4F2 by monolithic stacking. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2021"},{"key":"4078_CR6","doi-asserted-by":"publisher","first-page":"2630","DOI":"10.1109\/JSSC.2024.3363871","volume":"59","author":"S Yan","year":"2024","unstructured":"Yan S, Yue J, He C, et al. A 28-nm floating-point computing-in-memory processor using intensive-CIM sparse-digital architecture. IEEE J Solid-State Circ, 2024, 59: 2630\u20132643","journal-title":"IEEE J Solid-State Circ"},{"key":"4078_CR7","doi-asserted-by":"publisher","first-page":"2560","DOI":"10.1109\/JSSC.2022.3148273","volume":"57","author":"J Yue","year":"2022","unstructured":"Yue J, Liu Y, Yuan Z, et al. STICKER-IM: a 65 nm computing-in-memory NN processor using block-wise sparsity optimization and inter\/intra-macro data reuse. IEEE J Solid-State Circ, 2022, 57: 2560\u20132573","journal-title":"IEEE J Solid-State Circ"},{"key":"4078_CR8","first-page":"1","volume-title":"Proceedings of IEEE International Solid-State Circuits Conference (ISSCC)","author":"H Fujiwara","year":"2022","unstructured":"Fujiwara H, Mori H, Zhao W-C, et al. A 5-nm 254-TOPS\/W 221-TOPS\/mm2 fully-digital computing-in-memory macro supporting wide-range dynamic-voltage-frequency scaling and simultaneous MAC and write operations. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2022. 1\u20133"},{"key":"4078_CR9","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530576","volume-title":"YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip","author":"Y Chen","year":"2022","unstructured":"Chen Y, Yin G, Tan Z, et al. YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip. 2022. ArXiv:2206.00379"},{"key":"4078_CR10","first-page":"238","volume-title":"Proceedings of IEEE International Solid-State Circuits Conference (ISSCC)","author":"J Yue","year":"2021","unstructured":"Yue J, Feng X, He Y, et al. 15.2 A 2.75-to-75.9 TOPS\/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and ping-pong CIM with simultaneous computation and weight updating. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2021. 238\u2013240"},{"key":"4078_CR11","doi-asserted-by":"publisher","first-page":"1612","DOI":"10.1109\/JSSC.2023.3324954","volume":"59","author":"J Yue","year":"2024","unstructured":"Yue J, Liu Y, Feng X, et al. An energy-efficient computing-in-memory NN processor with set-associate blockwise sparsity and ping-pong weight update. IEEE J Solid-State Circ, 2024, 59: 1612\u20131627","journal-title":"IEEE J Solid-State Circ"},{"key":"4078_CR12","doi-asserted-by":"publisher","first-page":"919","DOI":"10.1109\/LED.2023.3269080","volume":"44","author":"X Zheng","year":"2023","unstructured":"Zheng X, Wu L, Dong D, et al. Endurance prediction based on hidden Markov model and programming optimization for 28nm 1Mbit resistive random access memory chip. IEEE Electron Device Lett, 2023, 44: 919\u2013922","journal-title":"IEEE Electron Device Lett"},{"key":"4078_CR13","first-page":"245","volume-title":"Proceedings of IEEE International Solid-State Circuits Conference (ISSCC)","author":"C-X Xue","year":"2021","unstructured":"Xue C-X, Hung J-M, Kao H-Y, et al. 16.1 A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS\/W for tiny AI edge devices. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2021. 245\u2013247"},{"key":"4078_CR14","first-page":"244","volume-title":"Proceedings of IEEE International Solid-State Circuits Conference","author":"C-X Xue","year":"2020","unstructured":"Xue C-X, Huang T-Y, Liu J-S, et al. 15.4 A 22nm 2Mb ReRAM compute-in-memory macro with 121\u201328TOPS\/W for multibit MAC computing for tiny AI edge devices. In: Proceedings of IEEE International Solid-State Circuits Conference, 2020. 244\u2013246"},{"key":"4078_CR15","first-page":"1075","volume-title":"Proceedings of the 58th ACM\/IEEE Design Automation Conference (DAC)","author":"T-H Nguyen","year":"2021","unstructured":"Nguyen T-H, Imran M, Choi J, et al. Low-cost and effective fault-tolerance enhancement techniques for emerging memories-based deep neural networks. In: Proceedings of the 58th ACM\/IEEE Design Automation Conference (DAC), 2021. 1075\u20131080"},{"key":"4078_CR16","doi-asserted-by":"publisher","first-page":"5043","DOI":"10.1002\/adma.201502239","volume":"27","author":"W-J Lee","year":"2015","unstructured":"Lee W-J, Park W-T, Park S, et al. Large-scale precise printing of ultrathin Sol-Gel oxide dielectrics for directly patterned solution-processed metal oxide transistor arrays. Adv Mater, 2015, 27: 5043\u20135048","journal-title":"Adv Mater"},{"key":"4078_CR17","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM)","author":"A Belmonte","year":"2020","unstructured":"Belmonte A, Oh H, Rassoul N, et al. Capacitor-less, long-retention (>400s) DRAM cell paving the way towards low-power and high-density monolithic 3D DRAM. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2020"},{"key":"4078_CR18","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM)","author":"J Guo","year":"2021","unstructured":"Guo J, Han K, Subhechha S, et al. A new surface potential and physics based compact model for \u03b1-IGZO TFTs at multi-nanoscale for high retention and low-power DRAM application. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2021"},{"key":"4078_CR19","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM)","author":"M Oota","year":"2019","unstructured":"Oota M, Ando Y, Tsuda K, et al. 3D-stacked CAAC-In-Ga-Zn oxide FETs with gate length of 72nm. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2019"},{"key":"4078_CR20","doi-asserted-by":"publisher","first-page":"200404","DOI":"10.1007\/s11432-023-3802-8","volume":"66","author":"S Z Yan","year":"2023","unstructured":"Yan S Z, Cong Z R, Lu N D, et al. Recent progress in InGaZnO FETs for high-density 2T0C DRAM applications. Sci China Inf Sci, 2023, 66: 200404","journal-title":"Sci China Inf Sci"},{"key":"4078_CR21","first-page":"751","volume-title":"Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems","author":"S C Lin","year":"2018","unstructured":"Lin S C, Zhang Y, Hsu C H, et al. The architectural implications of autonomous driving: constraints and acceleration. In: Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems, 2018. 751\u2013766"},{"key":"4078_CR22","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3477006","volume":"20","author":"A Malawade","year":"2021","unstructured":"Malawade A, Odema M, Lajeunesse-degroot S, et al. SAGE: a split-architecture methodology for efficient end-to-end autonomous vehicle control. ACM Trans Embed Comput Syst, 2021, 20: 1\u201322","journal-title":"ACM Trans Embed Comput Syst"},{"key":"4078_CR23","first-page":"1","volume-title":"Proceedings of IEEE International Solid-State Circuits Conference (ISSCC)","author":"J-M Hung","year":"2022","unstructured":"Hung J-M, Huang Y-H, Huang S-P, et al. An 8-Mb DC-current-free binary-to-8b precision ReRAM nonvolatile computing- inmemory macro using time-space-readout with 1286.4\u201321.6 TOPS\/W for edge-AI devices. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2022. 1\u20133"},{"key":"4078_CR24","first-page":"1","volume-title":"Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)","author":"Z Wang","year":"2023","unstructured":"Wang Z, Yue J, He C, et al. A user-friendly fast and accurate simulation framework for non-ideal factors in computing-inmemory architecture. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2023. 1\u20135"},{"key":"4078_CR25","first-page":"161","volume-title":"Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","author":"N Lu","year":"2016","unstructured":"Lu N, Zong Z, Sun P, et al. Thermal effect and compact model in three-dimensional (3D) RRAM arrays. In: Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016. 161\u2013164"},{"key":"4078_CR26","volume-title":"Very deep convolutional networks for large-scale image recognition","author":"K Simonyan","year":"2014","unstructured":"Simonyan K, Zisserman A. Very deep convolutional networks for large-scale image recognition. 2014. ArXiv:1409.1556"},{"key":"4078_CR27","volume-title":"Learning multiple layers of features from tiny images","author":"A Krizhevsky","year":"2009","unstructured":"Krizhevsky A, Hinton G. Learning multiple layers of features from tiny images. 2009. doi: 10.1.1.222.9220"},{"key":"4078_CR28","first-page":"770","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition","author":"K He","year":"2016","unstructured":"He K, Zhang X, Ren S, et al. Deep residual learning for image recognition. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2016. 770\u2013778"},{"key":"4078_CR29","first-page":"976","volume-title":"Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition","author":"Z Liu","year":"2022","unstructured":"Liu Z, Mao H, Wu C-Y, et al. A ConvNet for the 2020s. In: Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition, 2022. 976\u2013986"},{"key":"4078_CR30","first-page":"248","volume-title":"Proceedings of IEEE Conference on Computer Vision and Pattern Recognition","author":"J Deng","year":"2009","unstructured":"Deng J, Dong W, Socher R, et al. ImageNet: a large-scale hierarchical image database. In: Proceedings of IEEE Conference on Computer Vision and Pattern Recognition, 2009. 248\u2013255"},{"key":"4078_CR31","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM)","author":"J Liu","year":"2021","unstructured":"Liu J, Sun C, Tang W, et al. Low-power and scalable retention-enhanced IGZO TFT eDRAM-based charge-domain computing. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2021"},{"key":"4078_CR32","first-page":"234","volume-title":"Proceedings of IEEE International Solid-State Circuits Conference-(ISSCC)","author":"J Yue","year":"2020","unstructured":"Yue J, Yuan Z, Feng X, et al. 14.3 A 65nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS\/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy-efficient inter\/intra-macro data reuse. In: Proceedings of IEEE International Solid-State Circuits Conference-(ISSCC), 2020. 234\u2013236"},{"key":"4078_CR33","doi-asserted-by":"publisher","first-page":"680","DOI":"10.1038\/s41928-023-01010-1","volume":"6","author":"M L Gallo","year":"2023","unstructured":"Gallo M L, Khaddam-Aljameh R, Stanisavljevic M, et al. A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. Nat Electron, 2023, 6: 680\u2013693","journal-title":"Nat Electron"},{"key":"4078_CR34","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1145\/3007787.3001139","volume":"44","author":"A Shafiee","year":"2016","unstructured":"Shafiee A, Nag A, Muralimanohar N, et al. ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. SIGARCH Comput Archit News, 2016, 44: 14\u201326","journal-title":"SIGARCH Comput Archit News"},{"key":"4078_CR35","volume-title":"Proceedings of International Electron Devices Meeting (IEDM)","author":"A Ma","year":"2022","unstructured":"Ma A, Gao B, Liu Y, et al. Multi-scale thermal modeling of RRAM-based 3D monolithic-integrated computing-in-memory chips. In: Proceedings of International Electron Devices Meeting (IEDM), 2022"},{"key":"4078_CR36","volume-title":"Proceedings of IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","author":"Y Du","year":"2023","unstructured":"Du Y, Tang J, Li Y, et al. Monolithic 3D integration of FeFET, hybrid CMOS logic and analog RRAM array for energy-efficient reconfigurable computing-in-memory architecture. In: Proceedings of IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023"},{"key":"4078_CR37","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM)","author":"X Peng","year":"2020","unstructured":"Peng X, Chakraborty W, Kaul A, et al. Benchmarking monolithic 3D integration for compute-in-memory accelerators: overcoming ADC bottlenecks and maintaining scalability to 7nm or beyond. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2020"},{"key":"4078_CR38","volume-title":"Proceedings of IEEE International Electron Devices Meeting (IEDM)","author":"Y Luo","year":"2021","unstructured":"Luo Y, Dutta S, Kaul A, et al. Monolithic 3D compute-in-memory accelerator with BEOL transistor based reconfigurable interconnect. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2021"}],"container-title":["Science China Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-024-4078-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11432-024-4078-1","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-024-4078-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,22]],"date-time":"2026-03-22T20:27:47Z","timestamp":1774211267000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11432-024-4078-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1,15]]},"references-count":38,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2025,2]]}},"alternative-id":["4078"],"URL":"https:\/\/doi.org\/10.1007\/s11432-024-4078-1","relation":{},"ISSN":["1674-733X","1869-1919"],"issn-type":[{"value":"1674-733X","type":"print"},{"value":"1869-1919","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,1,15]]},"assertion":[{"value":"16 January 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 March 2024","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 June 2024","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 January 2025","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}],"article-number":"122404"}}