{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:30:21Z","timestamp":1763469021819,"version":"build-2065373602"},"reference-count":153,"publisher":"Springer Science and Business Media LLC","issue":"11","license":[{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Sci. China Inf. Sci."],"published-print":{"date-parts":[[2025,11]]},"DOI":"10.1007\/s11432-024-4522-8","type":"journal-article","created":{"date-parts":[[2025,11,8]],"date-time":"2025-11-08T09:36:46Z","timestamp":1762594606000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Model quantization for computing-in-memory: a survey"],"prefix":"10.1007","volume":"68","author":[{"given":"Sifan","family":"Sun","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinyu","family":"Bai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hanting","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaiwen","family":"Deng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiwei","family":"Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jingjing","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bin","family":"Cao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"He","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wang","family":"Kang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weisheng","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2025,11,5]]},"reference":[{"key":"4522_CR1","doi-asserted-by":"publisher","first-page":"84","DOI":"10.1145\/3065386","volume":"60","author":"A Krizhevsky","year":"2017","unstructured":"Krizhevsky A, Sutskever I, Hinton G E. ImageNet classification with deep convolutional neural networks. Commun ACM, 2017, 60: 84\u201390","journal-title":"Commun ACM"},{"key":"4522_CR2","unstructured":"Simonyan K, Zisserman A. Very deep convolutional networks for large-scale image recognition. 2014. ArXiv:1409.1556"},{"key":"4522_CR3","first-page":"770","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition","author":"K He","year":"2016","unstructured":"He K, Zhang X, Ren S, et al. Deep residual learning for image recognition. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2016. 770\u2013778"},{"key":"4522_CR4","first-page":"4700","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition","author":"G Huang","year":"2017","unstructured":"Huang G, Liu Z, Van Der Maaten L, et al. Densely connected convolutional networks. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2017. 4700\u20134708"},{"key":"4522_CR5","first-page":"3431","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition","author":"J Long","year":"2015","unstructured":"Long J, Shelhamer E, Darrell T. Fully convolutional networks for semantic segmentation. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2015. 3431\u20133440"},{"key":"4522_CR6","first-page":"234","volume-title":"Proceedings of the Medical Image Computing and Computer-Assisted Intervention","author":"O Ronneberger","year":"2015","unstructured":"Ronneberger O, Fischer P, Brox T. U-net: convolutional networks for biomedical image segmentation. In: Proceedings of the Medical Image Computing and Computer-Assisted Intervention, 2015. 234\u2013241"},{"key":"4522_CR7","doi-asserted-by":"publisher","first-page":"834","DOI":"10.1109\/TPAMI.2017.2699184","volume":"40","author":"L C Chen","year":"2017","unstructured":"Chen L C, Papandreou G, Kokkinos I, et al. DeepLab: semantic image segmentation with deep convolutional nets, atrous convolution, and fully connected CRFs. IEEE Trans Pattern Anal Mach Intell, 2017, 40: 834\u2013848","journal-title":"IEEE Trans Pattern Anal Mach Intell"},{"key":"4522_CR8","first-page":"1440","volume-title":"Proceedings of the IEEE International Conference on Computer Vision","author":"R Girshick","year":"2015","unstructured":"Girshick R. Fast R-CNN. In: Proceedings of the IEEE International Conference on Computer Vision, 2015. 1440\u20131448"},{"key":"4522_CR9","first-page":"779","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition","author":"J Redmon","year":"2016","unstructured":"Redmon J, Divvala S, Girshick R, et al. You only look once: unified, real-time object detection. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2016. 779\u2013788"},{"key":"4522_CR10","first-page":"21","volume-title":"Proceedings of the European Conference on Computer Vision","author":"W Liu","year":"2016","unstructured":"Liu W, Anguelov D, Erhan D, et al. SSD: single shot multibox detector. In: Proceedings of the European Conference on Computer Vision, 2016. 21\u201337"},{"key":"4522_CR11","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1007\/978-3-642-19400-9_14","volume-title":"Proceedings of the International Conference on Intelligent Text Processing and Computational Linguistics","author":"C D Manning","year":"2011","unstructured":"Manning C D. Part-of-speech tagging from 97% to 100%: is it time for some linguistics? In: Proceedings of the International Conference on Intelligent Text Processing and Computational Linguistics, 2011. 171\u2013189"},{"key":"4522_CR12","doi-asserted-by":"publisher","first-page":"55","DOI":"10.1109\/MCI.2018.2840738","volume":"13","author":"T Young","year":"2018","unstructured":"Young T, Hazarika D, Poria S, et al. Recent trends in deep learning based natural language processing. IEEE Comput Intell Mag, 2018, 13: 55\u201375","journal-title":"IEEE Comput Intell Mag"},{"key":"4522_CR13","doi-asserted-by":"publisher","first-page":"264","DOI":"10.1016\/j.eng.2020.01.007","volume":"6","author":"Y Chen","year":"2020","unstructured":"Chen Y, Xie Y, Song L, et al. A survey of accelerator architectures for deep neural networks. Engineering, 2020, 6: 264\u2013274","journal-title":"Engineering"},{"key":"4522_CR14","doi-asserted-by":"publisher","first-page":"5005","DOI":"10.1007\/s41939-024-00517-0","volume":"7","author":"P Jangra","year":"2024","unstructured":"Jangra P, Duhan M. In-memory computing: characteristics, spintronics, and neural network applications insights. Multiscale Multidiscip Model Exp Des, 2024, 7: 5005\u20135029","journal-title":"Multiscale Multidiscip Model Exp Des"},{"key":"4522_CR15","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1186\/s11671-020-03299-9","volume":"15","author":"F Zahoor","year":"2020","unstructured":"Zahoor F, Azni Zulkifli T Z, Khanday F A. Resistive random access memory (RRAM): an overview of materials, switching mechanism, performance, multilevel cell (MLC) storage, modeling, and applications. Nanoscale Res Lett, 2020, 15: 1\u201326","journal-title":"Nanoscale Res Lett"},{"key":"4522_CR16","first-page":"609","volume-title":"Proceedings of the IEEE International Conference on Computer Design","author":"D Fan","year":"2017","unstructured":"Fan D, Angizi S. Energy efficient in-memory binary deep neural network accelerator with dual-mode SOT-MRAM. In: Proceedings of the IEEE International Conference on Computer Design, 2017. 609\u2013612"},{"key":"4522_CR17","first-page":"89","volume-title":"Proceedings of the Great Lakes Symposium on VLSI","author":"S Bavikadi","year":"2020","unstructured":"Bavikadi S, Sutradhar P R, Khasawneh K N, et al. A review of in-memory computing architectures for machine learning applications. In: Proceedings of the Great Lakes Symposium on VLSI, 2020. 89\u201394"},{"key":"4522_CR18","doi-asserted-by":"publisher","first-page":"31","DOI":"10.1109\/MCAS.2021.3092533","volume":"21","author":"S Yu","year":"2021","unstructured":"Yu S, Jiang H, Huang S, et al. Compute-in-memory chips for deep learning: recent trends and prospects. IEEE Circuits Syst Mag, 2021, 21: 31\u201356","journal-title":"IEEE Circuits Syst Mag"},{"key":"4522_CR19","unstructured":"Zhou S, Wu Y, Ni Z, et al. Dorefa-net: training low bitwidth convolutional neural networks with low bitwidth gradients. 2016. ArXiv:1606.06160"},{"key":"4522_CR20","unstructured":"Choi J, Wang Z, Venkataramani S, et al. Pact: parameterized clipping activation for quantized neural networks. 2018. ArXiv:1805.06085"},{"key":"4522_CR21","unstructured":"Li Y, Gong R, Tan X, et al. Brecq: pushing the limit of post-training quantization by block reconstruction. 2021. ArXiv:2102.05426"},{"key":"4522_CR22","doi-asserted-by":"publisher","first-page":"649","DOI":"10.1109\/JETCAS.2021.3127129","volume":"11","author":"B Kang","year":"2021","unstructured":"Kang B, Lu A, Long Y, et al. Genetic algorithm-based energy-aware CNN quantization for processing-in-memory architecture. IEEE J Emerg Sel Top Circuits Syst, 2021, 11: 649\u2013662","journal-title":"IEEE J Emerg Sel Top Circuits Syst"},{"key":"4522_CR23","first-page":"325","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference","author":"H Sun","year":"2020","unstructured":"Sun H, Zhu Z, Cai Y, et al. An energy-efficient quantized and regularized training framework for processing-in-memory accelerators. In: Proceedings of the Asia and South Pacific Design Automation Conference, 2020. 325\u2013330"},{"key":"4522_CR24","first-page":"1","volume-title":"Proceedings of the IEEE Design Automation Conference","author":"Y Long","year":"2020","unstructured":"Long Y, Lee E, Kim D, et al. Q-pim: a genetic algorithm based flexible DNN quantization method and application to processing-in-memory platform. In: Proceedings of the IEEE Design Automation Conference, 2020. 1\u20136"},{"key":"4522_CR25","doi-asserted-by":"publisher","first-page":"189","DOI":"10.1109\/TCAD.2023.3298705","volume":"43","author":"J Bai","year":"2024","unstructured":"Bai J, Sun S, Zhao W, et al. CIMQ: a hardware-efficient quantization framework for computing-in-memory-based neural network accelerators. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2024, 43: 189\u2013202","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR26","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3623402","volume":"14","author":"B Rokh","year":"2023","unstructured":"Rokh B, Azarpeyvand A, Khanteymoori A. A comprehensive survey on model quantization for deep neural networks in image classification. ACM Trans Intell Syst Tech, 2023, 14: 1\u201350","journal-title":"ACM Trans Intell Syst Tech"},{"key":"4522_CR27","unstructured":"Gholami A, Kim S, Dong Z, et al. A survey of quantization methods for efficient neural network inference. 2021. ArXiv:2103.13630"},{"key":"4522_CR28","doi-asserted-by":"publisher","first-page":"107281","DOI":"10.1016\/j.patcog.2020.107281","volume":"105","author":"H Qin","year":"2020","unstructured":"Qin H, Gong R, Liu X, et al. Binary neural networks: a survey. Pattern Recognit, 2020, 105: 107281","journal-title":"Pattern Recognit"},{"key":"4522_CR29","unstructured":"Nagel M, Fournarakis M, Amjad R A, et al. A white paper on neural network quantization. 2021. ArXiv:2106.08295"},{"key":"4522_CR30","unstructured":"Mishra R, Gupta H P, Dutta T. A survey on deep neural network compression: challenges, overview, and solutions. 2020. ArXiv:2010.03954"},{"key":"4522_CR31","unstructured":"Weng O. Neural network quantization for efficient inference: a survey. 2021. ArXiv:2112.06126"},{"key":"4522_CR32","doi-asserted-by":"publisher","first-page":"485","DOI":"10.1109\/JPROC.2020.2976475","volume":"108","author":"B L Deng","year":"2020","unstructured":"Deng B L, Li G, Han S, et al. Model compression and hardware acceleration for neural networks: a comprehensive survey. Proc IEEE, 2020, 108: 485\u2013532","journal-title":"Proc IEEE"},{"key":"4522_CR33","doi-asserted-by":"publisher","first-page":"370","DOI":"10.1016\/j.neucom.2021.07.045","volume":"461","author":"T Liang","year":"2021","unstructured":"Liang T, Glossner J, Wang L, et al. Pruning and quantization for deep neural network acceleration: a survey. Neurocomputing, 2021, 461: 370\u2013403","journal-title":"Neurocomputing"},{"key":"4522_CR34","doi-asserted-by":"publisher","first-page":"945","DOI":"10.3390\/electronics11060945","volume":"11","author":"D Ghimire","year":"2022","unstructured":"Ghimire D, Kil D, Kim S. A survey on efficient convolutional neural networks and hardware acceleration. Electronics, 2022, 11: 945","journal-title":"Electronics"},{"key":"4522_CR35","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3527156","volume":"55","author":"G Armeniakos","year":"2022","unstructured":"Armeniakos G, Zervakis G, Soudris D, et al. Hardware approximate techniques for deep neural network accelerators: a survey. ACM Comput Surv, 2022, 55: 1\u201336","journal-title":"ACM Comput Surv"},{"key":"4522_CR36","doi-asserted-by":"publisher","first-page":"719","DOI":"10.1109\/T-C.1969.222754","volume":"100","author":"W H Kautz","year":"1969","unstructured":"Kautz W H. Cellular logic-in-memory arrays. IEEE Trans Comput, 1969, 100: 719\u2013727","journal-title":"IEEE Trans Comput"},{"key":"4522_CR37","doi-asserted-by":"publisher","first-page":"73","DOI":"10.1109\/TC.1970.5008902","volume":"100","author":"H S Stone","year":"1970","unstructured":"Stone H S. A logic-in-memory computer. IEEE Trans Comput, 1970, 100: 73\u201378","journal-title":"IEEE Trans Comput"},{"key":"4522_CR38","first-page":"224","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference","author":"D Patterson","year":"1997","unstructured":"Patterson D, Anderson T, Cardwell N, et al. Intelligent RAM (IRAM): chips that remember and compute. In: Proceedings of the IEEE International Solid-State Circuits Conference, 1997. 224\u2013225"},{"key":"4522_CR39","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1109\/54.748803","volume":"16","author":"D G Elliott","year":"1999","unstructured":"Elliott D G, Stumm M, Snelgrove W M, et al. Computational RAM: implementing processors in memory. IEEE Design Test Comput, 1999, 16: 32\u201341","journal-title":"IEEE Design Test Comput"},{"key":"4522_CR40","first-page":"57","volume-title":"Proceedings of the ACM\/IEEE Conference on Supercomputing","author":"M Hall","year":"1999","unstructured":"Hall M, Kogge P, Koller J, et al. Mapping irregular applications to DIVA, a PIM-based data-intensive architecture. In: Proceedings of the ACM\/IEEE Conference on Supercomputing, 1999. 57"},{"key":"4522_CR41","doi-asserted-by":"publisher","first-page":"27","DOI":"10.1145\/3007787.3001140","volume":"44","author":"P Chi","year":"2016","unstructured":"Chi P, Li S, Xu C, et al. Prime: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. SIGARCH Comput Archit News, 2016, 44: 27\u201339","journal-title":"SIGARCH Comput Archit News"},{"key":"4522_CR42","first-page":"696","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"S Li","year":"2018","unstructured":"Li S, Glova A O, Hu X, et al. Scope: a stochastic computing engine for DRAM-based in-situ accelerator. In: Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO), 2018. 696\u2013709"},{"key":"4522_CR43","doi-asserted-by":"publisher","first-page":"2668","DOI":"10.1109\/TVLSI.2019.2926984","volume":"27","author":"L Chang","year":"2019","unstructured":"Chang L, Ma X, Wang Z, et al. Pxnor-BNN: in\/with spin-orbit torque mram preset-xnor operation-based binary neural networks. IEEE Trans VLSI Syst, 2019, 27: 2668\u20132679","journal-title":"IEEE Trans VLSI Syst"},{"key":"4522_CR44","first-page":"1","volume-title":"Proceedings of the IEEE International Conference on ASIC (ASICON)","author":"J Kang","year":"2019","unstructured":"Kang J, Huang P, Han R, et al. Flash-based computing in-memory scheme for IoT. In: Proceedings of the IEEE International Conference on ASIC (ASICON), 2019. 1\u20134"},{"key":"4522_CR45","first-page":"4412","volume":"71","author":"Y Ling","year":"2024","unstructured":"Ling Y, Wang Z, Wu L, et al. An RRAM-based hierarchical computing-in-memory architecture with synchronous parallelism for 3d point cloud recognition. IEEE Trans Circuits Syst II Express Briefs, 2024, 71: 4412\u20134416","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"key":"4522_CR46","doi-asserted-by":"publisher","first-page":"273","DOI":"10.1145\/3123939.3124544","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture","author":"V Seshadri","year":"2017","unstructured":"Seshadri V, Lee D, Mullins T, et al. Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology. In: Proceedings of the IEEE\/ACM International Symposium on Microarchitecture, 2017. 273\u2013287"},{"key":"4522_CR47","first-page":"1","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference (DAC)","author":"K Lee","year":"2020","unstructured":"Lee K, Jeong J, Cheon S, et al. Bit parallel 6t SRAM in-memory computing with reconfigurable bit-precision. In: Proceedings of the ACM\/IEEE Design Automation Conference (DAC), 2020. 1\u20136"},{"key":"4522_CR48","first-page":"1","volume-title":"Proceedings of the IEEE International Electron Devices Meeting (IEDM)","author":"D Kau","year":"2009","unstructured":"Kau D, Tang S, Karpov I V, et al. A stackable cross point phase change memory. In: Proceedings of the IEEE International Electron Devices Meeting (IEDM), 2009. 1\u20134"},{"key":"4522_CR49","first-page":"373","volume-title":"Proceedings of the Great Lakes Symposium on VLSI","author":"A F Laguna","year":"2019","unstructured":"Laguna A F, Yin X, Reis D, et al. Ferroelectric FET-based in-memory computing for few-shot learning. In: Proceedings of the Great Lakes Symposium on VLSI, 2019. 373\u2013378"},{"key":"4522_CR50","doi-asserted-by":"publisher","first-page":"211","DOI":"10.1038\/s41586-021-04196-6","volume":"601","author":"S Jung","year":"2022","unstructured":"Jung S, Lee H, Myung S, et al. A crossbar array of magnetoresistive memory devices for in-memory computing. Nature, 2022, 601: 211\u2013216","journal-title":"Nature"},{"key":"4522_CR51","doi-asserted-by":"publisher","first-page":"162402","DOI":"10.1007\/s11432-021-3562-8","volume":"66","author":"Y Huang","year":"2023","unstructured":"Huang Y, Cao K, Zhang K, et al. Implementation of 16 Boolean logic operations based on one basic cell of spin-transfer-torque magnetic random access memory. Sci China Inf Sci, 2023, 66: 162402","journal-title":"Sci China Inf Sci"},{"key":"4522_CR52","doi-asserted-by":"publisher","first-page":"122406","DOI":"10.1007\/s11432-020-3189-x","volume":"65","author":"W Cai","year":"2022","unstructured":"Cai W, Wang M, Cao K, et al. Stateful implication logic based on perpendicular magnetic tunnel junctions. Sci China Inf Sci, 2022, 65: 122406","journal-title":"Sci China Inf Sci"},{"key":"4522_CR53","doi-asserted-by":"publisher","first-page":"119403","DOI":"10.1007\/s11432-023-3809-3","volume":"67","author":"S Lu","year":"2024","unstructured":"Lu S, Ning X, Zhang H, et al. Spin-orbit torque efficiency enhancement to tungsten-based SOT-MTJs by interface modification with an ultrathin MgO. Sci China Inf Sci, 2024, 67: 119403","journal-title":"Sci China Inf Sci"},{"key":"4522_CR54","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/s11432-024-4186-6","volume":"68","author":"Y Yao","year":"2025","unstructured":"Yao Y, Zhu D, Xia Q, et al. Orbitronics for energy-efficient magnetization switching. Sci China Inform Sci, 2025, 68: 1\u20132","journal-title":"Sci China Inform Sci"},{"key":"4522_CR55","doi-asserted-by":"publisher","first-page":"934","DOI":"10.1109\/JETCAS.2022.3214334","volume":"12","author":"T Cao","year":"2022","unstructured":"Cao T, Liu C, Wang W, et al. A non-idealities aware software-Hardware co-design framework for edge-ai deep neural network implemented on memristive crossbar. IEEE J Emerg Sel Top Circuits Syst, 2022, 12: 934\u2013943","journal-title":"IEEE J Emerg Sel Top Circuits Syst"},{"key":"4522_CR56","doi-asserted-by":"publisher","first-page":"5282","DOI":"10.1038\/s41467-023-40770-4","volume":"14","author":"M J Rasch","year":"2023","unstructured":"Rasch M J, Mackin C, Le Gallo M, et al. Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators. Nat Commun, 2023, 14: 5282","journal-title":"Nat Commun"},{"key":"4522_CR57","doi-asserted-by":"publisher","first-page":"142401","DOI":"10.1007\/s11432-021-3472-9","volume":"66","author":"Y Zhao","year":"2023","unstructured":"Zhao Y, Yang J, Li B, et al. NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. Sci China Inf Sci, 2023, 66: 142401","journal-title":"Sci China Inf Sci"},{"key":"4522_CR58","unstructured":"Li Y, Shen M, Ma J, et al. Mqbench: towards reproducible and deployable model quantization benchmark. 2021. ArXiv:2111.03759"},{"key":"4522_CR59","first-page":"2704","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition","author":"B Jacob","year":"2018","unstructured":"Jacob B, Kligys S, Chen B, et al. Quantization and training of neural networks for efficient integer-arithmetic-only inference. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2018. 2704\u20132713"},{"key":"4522_CR60","first-page":"448","volume-title":"Proceedings of the International Conference on Machine Learning","author":"S Ioffe","year":"2015","unstructured":"Ioffe S, Szegedy C. Batch normalization: accelerating deep network training by reducing internal covariate shift. In: Proceedings of the International Conference on Machine Learning, 2015. 448\u2013456"},{"key":"4522_CR61","first-page":"32","volume-title":"Advances in Neural Information Processing Systems","author":"A Paszke","year":"2019","unstructured":"Paszke A, Gross S, Massa F, et al. Pytorch: an imperative style, high-performance deep learning library. Advances in Neural Information Processing Systems, 2019. 32"},{"key":"4522_CR62","doi-asserted-by":"publisher","first-page":"4996","DOI":"10.1109\/TCSI.2024.3412151","volume":"71","author":"Y Fu","year":"2024","unstructured":"Fu Y, Li J, Yu W H, et al. CLUT-CIM: a capacitance lookup table-based analog compute-in-memory macro with signed-channel training and weight updating for nonuniform quantization. IEEE Trans Circuits Syst I Regul Pap, 2024, 71: 4996\u20135004","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"key":"4522_CR63","first-page":"3049","volume":"70","author":"J Bai","year":"2023","unstructured":"Bai J, Xue W, Fan Y, et al. Partial sum quantization for computing-in-memory-based neural network accelerator. IEEE Trans Circuits Syst II Express Briefs, 2023, 70: 3049\u20133053","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"key":"4522_CR64","doi-asserted-by":"publisher","first-page":"3330","DOI":"10.1109\/JSSC.2024.3399706","volume":"59","author":"S Um","year":"2024","unstructured":"Um S, Kim S, Hong S, et al. Log-cim: an energy-efficient logarithmic quantization computing-in-memory processor with exponential parallel data mapping and zero-aware 6t dual-wl cell. IEEE J Solid-State Circuits, 2024, 59: 3330\u20133341","journal-title":"IEEE J Solid-State Circuits"},{"key":"4522_CR65","first-page":"1","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)","author":"U Saxena","year":"2023","unstructured":"Saxena U, Roy K. Partial-sum quantization for near ADC-less compute-in-memory accelerators. In: Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2023. 1\u20136"},{"key":"4522_CR66","doi-asserted-by":"crossref","unstructured":"Rogers E G, Mugdho S S, Gupte K K, et al. Stox-net: stochastic processing of partial sums for efficient in-memory computing DNN accelerators. 2024. ArXiv:2407.12378","DOI":"10.1109\/ICRC64395.2024.10937005"},{"key":"4522_CR67","doi-asserted-by":"publisher","first-page":"1888","DOI":"10.1109\/JSSC.2020.2992886","volume":"55","author":"Z Jiang","year":"2020","unstructured":"Jiang Z, Yin S, Seo J S, et al. C3sram: an in-memory-computing sram macro based on robust capacitive coupling computing mechanism. IEEE J Solid-State Circuits, 2020, 55: 1888\u20131897","journal-title":"IEEE J Solid-State Circuits"},{"key":"4522_CR68","doi-asserted-by":"crossref","unstructured":"Negi S, Saxena U, Sharma D, et al. Hcim: ADC-less hybrid analog-digital compute in memory accelerator for deep learning workloads. 2024. ArXiv:2403.13577","DOI":"10.1145\/3658617.3697572"},{"key":"4522_CR69","doi-asserted-by":"publisher","first-page":"1414","DOI":"10.1109\/TCAD.2019.2917852","volume":"39","author":"Y Cai","year":"2019","unstructured":"Cai Y, Tang T, Xia L, et al. Low bit-width convolutional neural network on RRAM. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2019, 39: 1414\u20131427","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR70","first-page":"32","volume-title":"Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","author":"J Bai","year":"2023","unstructured":"Bai J, Sun S, Kang W. Exploring bit-level sparsity for partial sum quantization in computing-in-memory accelerator. In: Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), 2023. 32\u201337"},{"key":"4522_CR71","doi-asserted-by":"publisher","first-page":"1550","DOI":"10.1109\/TCAD.2021.3082107","volume":"41","author":"S H Sie","year":"2021","unstructured":"Sie S H, Lee J L, Chen Y R, et al. Mars: multimacro architecture SRAM CIM-based accelerator with co-designed compressed neural networks. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2021, 41: 1550\u20131562","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR72","doi-asserted-by":"publisher","first-page":"538","DOI":"10.3389\/fnins.2017.00538","volume":"11","author":"T Gokmen","year":"2017","unstructured":"Gokmen T, Onen M, Haensch W. Training deep convolutional neural networks with resistive cross-point devices. Front Neurosci, 2017, 11: 538","journal-title":"Front Neurosci"},{"key":"4522_CR73","first-page":"2310","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)","author":"P Y Chen","year":"2016","unstructured":"Chen P Y, Yu S. Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing. In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2016. 2310\u20132313"},{"key":"4522_CR74","first-page":"1333","volume":"67","author":"X Peng","year":"2019","unstructured":"Peng X, Liu R, Yu S. Optimizing weight mapping and data flow for convolutional neural networks on processing-in-memory architectures. IEEE Trans Circuits Syst I, 2019, 67: 1333\u20131343","journal-title":"IEEE Trans Circuits Syst I"},{"key":"4522_CR75","doi-asserted-by":"publisher","first-page":"2306","DOI":"10.1109\/TCAD.2020.3043731","volume":"40","author":"X Peng","year":"2020","unstructured":"Peng X, Huang S, Jiang H, et al. Dnn+neurosim v2.0: an end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2020, 40: 2306\u20132319","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR76","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1145\/3007787.3001139","volume":"44","author":"A Shafiee","year":"2016","unstructured":"Shafiee A, Nag A, Muralimanohar N, et al. Isaac: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars. SIGARCH Comput Archit News, 2016, 44: 14\u201326","journal-title":"SIGARCH Comput Archit News"},{"key":"4522_CR77","doi-asserted-by":"publisher","first-page":"2276","DOI":"10.1109\/JPROC.2020.3003007","volume":"108","author":"I Chakraborty","year":"2020","unstructured":"Chakraborty I, Ali M, Ankit A, et al. Resistive crossbars as approximate hardware building blocks for machine learning: opportunities and challenges. Proc IEEE, 2020, 108: 2276\u20132310","journal-title":"Proc IEEE"},{"key":"4522_CR78","doi-asserted-by":"publisher","first-page":"4069","DOI":"10.1109\/TNNLS.2021.3055814","volume":"33","author":"W Huang","year":"2021","unstructured":"Huang W, Wu H, Chen Q, et al. FPGA-based high-throughput CNN hardware accelerator with high computing resource utilization ratio. IEEE Trans Neural Netw Learn Syst, 2021, 33: 4069\u20134083","journal-title":"IEEE Trans Neural Netw Learn Syst"},{"key":"4522_CR79","doi-asserted-by":"publisher","first-page":"45","DOI":"10.1109\/JXCDC.2020.2992306","volume":"6","author":"W C Wei","year":"2020","unstructured":"Wei W C, Jhang C J, Chen Y R, et al. A relaxed quantization training method for hardware limitations of resistive random access memory (ReRAM)-based computing-in-memory. IEEE J Explor Solid-State Comput Devices Circuits, 2020, 6: 45\u201352","journal-title":"IEEE J Explor Solid-State Comput Devices Circuits"},{"key":"4522_CR80","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3528104","volume":"18","author":"Y Kim","year":"2022","unstructured":"Kim Y, Kim H, Kim J J. Extreme partial-sum quantization for analog computing-in-memory neural network accelerators. J Emerg Technol Comput Syst, 2022, 18: 1\u201319","journal-title":"J Emerg Technol Comput Syst"},{"key":"4522_CR81","first-page":"30","volume-title":"Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","author":"H W Kuo","year":"2022","unstructured":"Kuo H W, Wang R H, Li Z, et al. A two-stage training framework for hardware constraints of computing-in-memory architecture. In: Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2022. 30\u201334"},{"key":"4522_CR82","doi-asserted-by":"publisher","first-page":"529","DOI":"10.1038\/s41565-020-0655-z","volume":"15","author":"A Sebastian","year":"2020","unstructured":"Sebastian A, Le Gallo M, Khaddam-Aljameh R, et al. Memory devices and applications for in-memory computing. Nat Nanotechnol, 2020, 15: 529\u2013544","journal-title":"Nat Nanotechnol"},{"key":"4522_CR83","unstructured":"Miyashita D, Lee E H, Murmann B. Convolutional neural networks using logarithmic data representation. 2016. ArXiv:1603.01025"},{"key":"4522_CR84","unstructured":"Zhou A, Yao A, Guo Y, et al. Incremental network quantization: towards lossless CNNs with low-precision weights. 2017. ArXiv:1702.03044"},{"key":"4522_CR85","first-page":"1","volume-title":"Proceedings of the IEEE Nordic Circuits and Systems Conference (NorCAS)","author":"A Gautier","year":"2023","unstructured":"Gautier A, Larras B, Martens O, et al. Evaluation of power-of-two quantization for multiplier-less near-memory and inmemory computing schemes for biomedical applications. In: Proceedings of the IEEE Nordic Circuits and Systems Conference (NorCAS), 2023. 1\u20135"},{"key":"4522_CR86","unstructured":"Li Y, Dong X, Wang W. Additive powers-of-two quantization: an efficient non-uniform discretization for neural networks. 2019. ArXiv:1909.13144"},{"key":"4522_CR87","doi-asserted-by":"publisher","first-page":"143","DOI":"10.1109\/JSSC.2023.3312615","volume":"59","author":"S Moon","year":"2024","unstructured":"Moon S, Mun H G, Son H, et al. Multipurpose deep-learning accelerator for arbitrary quantization with reduction of storage, logic, and latency waste. IEEE J Solid-State Circuits, 2024, 59: 143\u2013156","journal-title":"IEEE J Solid-State Circuits"},{"key":"4522_CR88","first-page":"525","volume-title":"Proceedings of the European Conference on Computer Vision","author":"M Rastegari","year":"2016","unstructured":"Rastegari M, Ordonez V, Redmon J, et al. Xnor-net: imagenet classification using binary convolutional neural networks. In: Proceedings of the European Conference on Computer Vision, 2016. 525\u2013542"},{"key":"4522_CR89","first-page":"3123","volume-title":"Proceedings of the International Conference on Neural Information Processing Systems-Volume 2","author":"M Courbariaux","year":"2015","unstructured":"Courbariaux M, Bengio Y, David J P. Binaryconnect: training deep neural networks with binary weights during propagations. In: Proceedings of the International Conference on Neural Information Processing Systems-Volume 2, 2015. 3123\u20133131"},{"key":"4522_CR90","doi-asserted-by":"publisher","first-page":"30039","DOI":"10.1038\/srep30039","volume":"6","author":"A Sengupta","year":"2016","unstructured":"Sengupta A, Panda P, Wijesinghe P, et al. Magnetic tunnel junction mimics stochastic cortical spiking neurons. Sci Rep, 2016, 6: 30039","journal-title":"Sci Rep"},{"key":"4522_CR91","first-page":"559","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference (DAC)","author":"S K Cherupally","year":"2021","unstructured":"Cherupally S K, Rakin A S, Yin S, et al. Leveraging noise and aggressive quantization of in-memory computing for robust DNN hardware against adversarial input and weight attacks. In: Proceedings of the ACM\/IEEE Design Automation Conference (DAC), 2021. 559\u2013564"},{"key":"4522_CR92","first-page":"4114","volume-title":"Proceedings of the International Conference on Neural Information Processing Systems","author":"I Hubara","year":"2016","unstructured":"Hubara I, Courbariaux M, Soudry D, et al. Binarized neural networks. In: Proceedings of the International Conference on Neural Information Processing Systems, 2016. 4114\u20134122"},{"key":"4522_CR93","first-page":"1423","volume-title":"Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"X Sun","year":"2018","unstructured":"Sun X, Yin S, Peng X, et al. Xnor-RRAM: a scalable and parallel resistive synaptic architecture for binary neural networks. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018. 1423\u20131428"},{"key":"4522_CR94","first-page":"574","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC)","author":"X Sun","year":"2018","unstructured":"Sun X, Peng X, Chen P Y, et al. Fully parallel RRAM synaptic array for implementing binary neural network with (+1, \u22121) weights and (+1, 0) neurons. In: Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2018. 574\u2013579"},{"key":"4522_CR95","first-page":"3064","volume":"66","author":"A Agrawal","year":"2019","unstructured":"Agrawal A, Jaiswal A, Roy D, et al. Xcel-RAM: accelerating binary neural networks in high-throughput SRAM compute arrays. IEEE Trans Circuits Syst I, 2019, 66: 3064\u20133076","journal-title":"IEEE Trans Circuits Syst I"},{"key":"4522_CR96","first-page":"1","volume-title":"Proceedings of the IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","author":"W Xu","year":"2024","unstructured":"Xu W, Luo J, Fu B, et al. A novel small-signal ferroelectric memcapacitor based capacitive computing-in-memory for area- and energy-efficient quantized neural networks. In: Proceedings of the IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2024. 1\u20133"},{"key":"4522_CR97","unstructured":"Li F, Liu B, Wang X, et al. Ternary weight networks. 2016. ArXiv:1605.04711"},{"key":"4522_CR98","first-page":"500","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC)","author":"Q Liu","year":"2020","unstructured":"Liu Q, Gao B, Yao P, et al. A fully integrated analog ReRAM based 78.4 tops\/w compute-in-memory chip with fully parallel MAC computing. In: Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), 2020. 500\u2013502"},{"key":"4522_CR99","doi-asserted-by":"publisher","first-page":"781","DOI":"10.1109\/TCAD.2022.3184276","volume":"42","author":"S Zhu","year":"2022","unstructured":"Zhu S, Duong L H K, Chen H, et al. Fat: an in-memory accelerator with fast addition for ternary weight neural networks. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2022, 42: 781\u2013794","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR100","first-page":"1733","volume":"55","author":"S Yin","year":"2020","unstructured":"Yin S, Jiang Z, Seo J S, et al. XNOR-SRAM: in-memory computing SRAM macro for binary\/ternary deep neural networks. IEEE J Solid-State Circuits, 2020, 55: 1733\u20131743","journal-title":"IEEE J Solid-State Circuits"},{"key":"4522_CR101","first-page":"421","volume":"4","author":"L Luo","year":"2022","unstructured":"Luo L, Liu D, Zhang H, et al. Spincim: spin orbit torque memory for ternary neural networks based on the computing-inmemory architecture. CCF Trans High Performance Comput, 2022, 4: 421\u2013434","journal-title":"CCF Trans High Performance Comput"},{"key":"4522_CR102","doi-asserted-by":"publisher","first-page":"102787","DOI":"10.1016\/j.sysarc.2022.102787","volume":"134","author":"Y S Lee","year":"2023","unstructured":"Lee Y S, Gong Y H, Chung S W. Scale-cim: precision-scalable computing-in-memory for energy-efficient quantized neural networks. J Syst Architecture, 2023, 134: 102787","journal-title":"J Syst Architecture"},{"key":"4522_CR103","doi-asserted-by":"publisher","first-page":"4112","DOI":"10.1109\/TCAD.2023.3251696","volume":"42","author":"Z Zhu","year":"2023","unstructured":"Zhu Z, Sun H, Xie T, et al. Mnsim 2.0: a behavior-level modeling tool for processing-in-memory architectures. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2023, 42: 4112\u20134125","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR104","first-page":"1","volume-title":"Proceedings of the Design Automation Conference","author":"Z Zhu","year":"2019","unstructured":"Zhu Z, Sun H, Lin Y, et al. A configurable multi-precision CNN computing framework based on single bit RRAM. In: Proceedings of the Design Automation Conference, 2019. 1\u20136"},{"key":"4522_CR105","doi-asserted-by":"publisher","unstructured":"Chen X J, Yang C L. CIMNet: joint search for neural network and computing-in-memory architecture. IEEE Micro, 2024, doi: https:\/\/doi.org\/10.1109\/MM.2024.3409068","DOI":"10.1109\/MM.2024.3409068"},{"key":"4522_CR106","first-page":"372","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference","author":"S Huang","year":"2021","unstructured":"Huang S, Ankit A, Silveira P, et al. Mixed precision quantization for ReRAM-based DNN inference accelerators. In: Proceedings of the Asia and South Pacific Design Automation Conference, 2021. 372\u2013377"},{"key":"4522_CR107","first-page":"38","volume-title":"Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","author":"S Sun","year":"2023","unstructured":"Sun S, Ge J, Bai J, et al. Es-mpq: evolutionary search enabled mixed precision quantization framework for computingin-memory. In: Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), 2023. 38\u201343"},{"key":"4522_CR108","doi-asserted-by":"publisher","first-page":"2084","DOI":"10.1109\/TCAD.2024.3358609","volume":"43","author":"S Sun","year":"2024","unstructured":"Sun S, Bai J, Shi Z, et al. Cim2pq: an arraywise and hardware-friendly mixed precision quantization method for analog computing-in-memory. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2024, 43: 2084\u20132097","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR109","first-page":"867","volume-title":"Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"H Sun","year":"2022","unstructured":"Sun H, Wang C, Zhu Z, et al. Gibbon: efficient co-exploration of nn model and processing-in-memory architecture. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022. 867\u2013872"},{"key":"4522_CR110","first-page":"537","volume-title":"Proceedings of the Great Lakes Symposium on VLSI","author":"J Bai","year":"2024","unstructured":"Bai J, Zhang H, Kang W. Mixmixq: quantization with mixed bit-sparsity and mixed bit-width for cim accelerators. In: Proceedings of the Great Lakes Symposium on VLSI, 2024. 537\u2013540"},{"key":"4522_CR111","doi-asserted-by":"publisher","first-page":"577","DOI":"10.1109\/TEVC.2013.2281535","volume":"18","author":"K Deb","year":"2013","unstructured":"Deb K, Jain H. An evolutionary many-objective optimization algorithm using reference-point-based nondominated sorting approach, part I: solving problems with box constraints. IEEE Trans Evol Computat, 2013, 18: 577\u2013601","journal-title":"IEEE Trans Evol Computat"},{"key":"4522_CR112","first-page":"8612","volume-title":"Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition","author":"K Wang","year":"2019","unstructured":"Wang K, Liu Z, Lin Y, et al. Haq: hardware-aware automated quantization with mixed precision. In: Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition, 2019. 8612\u20138620"},{"key":"4522_CR113","doi-asserted-by":"publisher","first-page":"583","DOI":"10.1109\/TCAD.2021.3061521","volume":"41","author":"B Li","year":"2021","unstructured":"Li B, Qu S, Wang Y. An automated quantization framework for high-utilization RRAM-based PIM. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2021, 41: 583\u2013596","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR114","doi-asserted-by":"publisher","first-page":"595","DOI":"10.1109\/TC.2020.2991575","volume":"70","author":"W Jiang","year":"2020","unstructured":"Jiang W, Lou Q, Yan Z, et al. Device-circuit-architecture co-exploration for computing-in-memory neural accelerators. IEEE Trans Comput, 2020, 70: 595\u2013605","journal-title":"IEEE Trans Comput"},{"key":"4522_CR115","unstructured":"Wu B, Wang Y, Zhang P, et al. Mixed precision quantization of convnets via differentiable neural architecture search. 2018. ArXiv:1812.00090"},{"key":"4522_CR116","doi-asserted-by":"publisher","first-page":"2163","DOI":"10.1109\/TCAD.2024.3358583","volume":"43","author":"Y W Chen","year":"2024","unstructured":"Chen Y W, Wang R H, Cheng Y H, et al. Sun: dynamic hybrid-precision SRAM-based CIM accelerator with high macro utilization using structured pruning mixed-precision networks. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2024, 43: 2163\u20132176","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR117","doi-asserted-by":"publisher","first-page":"4124","DOI":"10.1109\/TCAD.2022.3197495","volume":"41","author":"J Peng","year":"2022","unstructured":"Peng J, Liu H, Zhao Z, et al. Cmq: crossbar-aware neural network mixed-precision quantization via differentiable architecture search. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2022, 41: 4124\u20134133","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR118","doi-asserted-by":"publisher","first-page":"1057","DOI":"10.1145\/3512290.3528692","volume-title":"Proceedings of the Genetic and Evolutionary Computation Conference","author":"S Miret","year":"2022","unstructured":"Miret S, Chua V S, Marder M, et al. Neuroevolution-enhanced multi-objective optimization for mixed-precision quantization. In: Proceedings of the Genetic and Evolutionary Computation Conference, 2022. 1057\u20131065"},{"key":"4522_CR119","first-page":"4322","volume-title":"Proceedings of the International Joint Conference on Artificial Intelligence","author":"H Benmeziane","year":"2021","unstructured":"Benmeziane H, El Maghraoui K, Ouarnoughi H, et al. Hardware-aware neural architecture search: survey and taxonomy. In: Proceedings of the International Joint Conference on Artificial Intelligence, 2021. 4322\u20134329"},{"key":"4522_CR120","doi-asserted-by":"publisher","first-page":"374","DOI":"10.1038\/s44287-024-00052-7","volume":"1","author":"O Krestinskaya","year":"2024","unstructured":"Krestinskaya O, Fouda M E, Benmeziane H, et al. Neural architecture search for in-memory computing-based deep learning accelerators. Nat Rev Electr Eng, 2024, 1: 374\u2013390","journal-title":"Nat Rev Electr Eng"},{"key":"4522_CR121","first-page":"2820","volume-title":"Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition","author":"M Tan","year":"2019","unstructured":"Tan M, Chen B, Pang R, et al. Mnasnet: platform-aware neural architecture search for mobile. In: Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition, 2019. 2820\u20132828"},{"key":"4522_CR122","first-page":"2078","volume-title":"Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition","author":"T Wang","year":"2020","unstructured":"Wang T, Wang K, Cai H, et al. Apq: joint search for network architecture, pruning and quantization policy. In: Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition, 2020. 2078\u20132087"},{"key":"4522_CR123","doi-asserted-by":"publisher","first-page":"182","DOI":"10.1109\/4235.996017","volume":"6","author":"K Deb","year":"2002","unstructured":"Deb K, Pratap A, Agarwal S, et al. A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Trans Evol Comput, 2002, 6: 182\u2013197","journal-title":"IEEE Trans Evol Comput"},{"key":"4522_CR124","unstructured":"Bengio Y, Leonard N, Courville A. Estimating or propagating gradients through stochastic neurons for conditional computation. 2013. ArXiv:1308.3432"},{"key":"4522_CR125","doi-asserted-by":"publisher","first-page":"1729","DOI":"10.1109\/TCAD.2024.3349502","volume":"43","author":"T Bai","year":"2024","unstructured":"Bai T, Mao W, Wang G, et al. An end-to-end in-memory computing system based on a 40-nm eFlash-based IMC SOC: circuits, toolchains, and systems co-design framework. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2024, 43: 1729\u20131740","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"4522_CR126","unstructured":"Jin Q, Chen Z, Ren J, et al. Pim-qat: neural network quantization for processing-in-memory (PIM) systems. 2022. ArXiv:2209.08617"},{"key":"4522_CR127","doi-asserted-by":"publisher","first-page":"7798","DOI":"10.1109\/JSEN.2024.3382479","volume":"25","author":"S Sharma","year":"2025","unstructured":"Sharma S, Kang B, Kidambi N V, et al. HamQ: hamming weight-based energy aware quantization for analog compute-in-memory accelerator in intelligent sensors. IEEE Sensors J, 2025, 25: 7798\u20137808","journal-title":"IEEE Sensors J"},{"key":"4522_CR128","first-page":"4350","volume-title":"Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition","author":"S Jung","year":"2019","unstructured":"Jung S, Son C, Lee S, et al. Learning to quantize deep networks by optimizing quantization intervals with task loss. In: Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition, 2019. 4350\u20134359"},{"key":"4522_CR129","unstructured":"Esser S K, McKinstry J L, Bablani D, et al. Learned step size quantization. 2019. ArXiv:1902.08153"},{"key":"4522_CR130","first-page":"2998","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)","author":"C T Huang","year":"2022","unstructured":"Huang C T, Chuang Y C, Lin M G, et al. Automated quantization range mapping for DAC\/ADC non-linearity in computingin-memory. In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2022. 2998\u20133002"},{"key":"4522_CR131","doi-asserted-by":"publisher","first-page":"38765","DOI":"10.1109\/ACCESS.2024.3369889","volume":"12","author":"J Yang","year":"2024","unstructured":"Yang J, Wang X, Jiang Y. Canet: quantized neural network inference with 8-bit carry-aware accumulator. IEEE Access, 2024, 12: 38765\u201338772","journal-title":"IEEE Access"},{"key":"4522_CR132","first-page":"712","volume-title":"Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Z Deng","year":"2022","unstructured":"Deng Z, Orshansky M. Variability-aware training and self-tuning of highly quantized DNNs for analog PIM. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022. 712\u2013717"},{"key":"4522_CR133","unstructured":"Finkelstein A, Almog U, Grobman M. Fighting quantization bias with bias. 2019. ArXiv:1906.03193"},{"key":"4522_CR134","first-page":"4486","volume-title":"Proceedings of the International Conference on Machine Learning","author":"E Meller","year":"2019","unstructured":"Meller E, Finkelstein A, Almog U, et al. Same, same but different: recovering neural network quantization error through weight factorization. In: Proceedings of the International Conference on Machine Learning, 2019. 4486\u20134495"},{"key":"4522_CR135","unstructured":"Sung W, Shin S, Hwang K. Resiliency of deep neural networks under quantization. 2015. ArXiv:1511.06488"},{"key":"4522_CR136","first-page":"7950","volume-title":"Proceedings of the International Conference on Neural Information Processing Systems","author":"R Banner","year":"2019","unstructured":"Banner R, Nahshan Y, Soudry D. Post training 4-bit quantization of convolutional networks for rapid-deployment. In: Proceedings of the International Conference on Neural Information Processing Systems, 2019. 7950\u20137958"},{"key":"4522_CR137","first-page":"7197","volume-title":"Proceedings of the International Conference on Machine Learning","author":"M Nagel","year":"2020","unstructured":"Nagel M, Amjad R A, Van Baalen M, et al. Up or down? Adaptive rounding for post-training quantization. In: Proceedings of the International Conference on Machine Learning, 2020. 7197\u20137206"},{"key":"4522_CR138","unstructured":"Hubara I, Nahshan Y, Hanani Y, et al. Improving post training neural quantization: layer-wise calibration and integer programming. 2020. ArXiv:2006.10518"},{"key":"4522_CR139","unstructured":"Yuan Z, Chen Y, Xue C, et al. PTQ-SL: exploring the sub-layerwise post-training quantization. 2021. ArXiv:2110.07809"},{"key":"4522_CR140","first-page":"1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)","author":"C Lammie","year":"2024","unstructured":"Lammie C, Vasilopoulos A, B\u00fcchel J, et al. Improving the accuracy of analog-based in-memory computing accelerators post-training. In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2024. 1\u20135"},{"key":"4522_CR141","unstructured":"Yang H, Duan L, Chen Y, et al. Bsq: exploring bit-level sparsity for mixed-precision neural network quantization. 2021. ArXiv:2102.10462"},{"key":"4522_CR142","first-page":"17737","volume":"34","author":"G Shomron","year":"2021","unstructured":"Shomron G, Gabbay F, Kurzum S, et al. Post-training sparsity-aware quantization. Adv Neural Inform Proc Syst, 2021, 34: 17737\u201317748","journal-title":"Adv Neural Inform Proc Syst"},{"key":"4522_CR143","doi-asserted-by":"publisher","first-page":"259","DOI":"10.1145\/3489517.3530660","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference","author":"F Liu","year":"2022","unstructured":"Liu F, Zhao W, Wang Z, et al. EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks. In: Proceedings of the ACM\/IEEE Design Automation Conference, 2022. 259\u2013264"},{"key":"4522_CR144","first-page":"1","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"P Judd","year":"2016","unstructured":"Judd P, Albericio J, Hetherington T, et al. Stripes: bit-serial deep neural network computing. In: Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO), 2016. 1\u201312"},{"key":"4522_CR145","doi-asserted-by":"publisher","first-page":"152","DOI":"10.1109\/TC.2023.3324477","volume":"73","author":"W Sun","year":"2024","unstructured":"Sun W, Zou Z, Liu D, et al. Bit-balance: model-hardware codesign for accelerating NNS by exploiting bit-level sparsity. IEEE Trans Comput, 2024, 73: 152\u2013163","journal-title":"IEEE Trans Comput"},{"key":"4522_CR146","first-page":"732","volume-title":"Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)","author":"M Shi","year":"2024","unstructured":"Shi M, Jain V, Joseph A, et al. Bitwave: exploiting column-based bit-level sparsity for deep learning acceleration. In: Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024. 732\u2013746"},{"key":"4522_CR147","first-page":"745","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference (DAC)","author":"S Qu","year":"2021","unstructured":"Qu S, Li B, Wang Y, et al. Asbp: automatic structured bit-pruning for RRAM-based NN accelerator. In: Proceedings of the ACM\/IEEE Design Automation Conference (DAC), 2021. 745\u2013750"},{"key":"4522_CR148","doi-asserted-by":"publisher","first-page":"852","DOI":"10.1109\/JSSC.2022.3198413","volume":"58","author":"R Guo","year":"2022","unstructured":"Guo R, Yue Z, Si X, et al. TT@CIM: a tensor-train in-memory-computing processor using bit-level-sparsity optimization and variable precision quantization. IEEE J Solid-State Circuits, 2022, 58: 852\u2013866","journal-title":"IEEE J Solid-State Circuits"},{"key":"4522_CR149","first-page":"153","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC)","author":"Y Chen","year":"2024","unstructured":"Chen Y, Yin G, Zhong H, et al. Zebra: a zero-bit robust-accumulation compute-in-memory approach for neural network acceleration utilizing different bitwise patterns. In: Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2024. 153\u2013158"},{"key":"4522_CR150","first-page":"234","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC)","author":"S Huai","year":"2023","unstructured":"Huai S, Liu D, Luo X, et al. Crossbar-aligned & integer-only neural network compression for efficient in-memory acceleration. In: Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2023. 234\u2013239"},{"key":"4522_CR151","first-page":"1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)","author":"B McDanel","year":"2021","unstructured":"McDanel B, Zhang S Q, Kung H. Saturation RRAM leveraging bit-level sparsity resulting from term quantization. In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2021. 1\u20135"},{"key":"4522_CR152","first-page":"1","volume-title":"Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"W Xue","year":"2023","unstructured":"Xue W, Bai J, Sun S, et al. Hierarchical non-structured pruning for computing-in-memory accelerators with reduced ADC resolution requirement. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023. 1\u20136"},{"key":"4522_CR153","doi-asserted-by":"publisher","first-page":"111","DOI":"10.1016\/j.aiopen.2022.10.001","volume":"3","author":"T Lin","year":"2022","unstructured":"Lin T, Wang Y, Liu X, et al. A survey of transformers. AI Open, 2022, 3: 111\u2013132","journal-title":"AI Open"}],"container-title":["Science China Information Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-024-4522-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11432-024-4522-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11432-024-4522-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,8]],"date-time":"2025-11-08T11:03:16Z","timestamp":1762599796000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11432-024-4522-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11]]},"references-count":153,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2025,11]]}},"alternative-id":["4522"],"URL":"https:\/\/doi.org\/10.1007\/s11432-024-4522-8","relation":{},"ISSN":["1674-733X","1869-1919"],"issn-type":[{"type":"print","value":"1674-733X"},{"type":"electronic","value":"1869-1919"}],"subject":[],"published":{"date-parts":[[2025,11]]},"assertion":[{"value":"12 November 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"28 April 2025","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 July 2025","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"5 November 2025","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}],"article-number":"211401"}}