{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T05:32:54Z","timestamp":1740461574475,"version":"3.37.3"},"reference-count":32,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2010,8,19]],"date-time":"2010-08-19T00:00:00Z","timestamp":1282176000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Real-Time Image Proc"],"published-print":{"date-parts":[[2012,3]]},"DOI":"10.1007\/s11554-010-0176-3","type":"journal-article","created":{"date-parts":[[2010,8,18]],"date-time":"2010-08-18T11:59:08Z","timestamp":1282132748000},"page":"3-19","source":"Crossref","is-referenced-by-count":0,"title":["Exploration of 3D grid caching strategies for ray-shooting"],"prefix":"10.1007","volume":"7","author":[{"given":"St\u00e9phane","family":"Mancini","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zahir","family":"Larabi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yves","family":"Mathieu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tomasz","family":"Toczek","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lionel","family":"Pierrefeu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2010,8,19]]},"reference":[{"key":"176_CR1","unstructured":"Amanatides, J., Woo, A.: A fast voxel traversal algorithm for ray tracing. In: Eurographics \u201987, pp. 3\u201310. Elsevier Science Publishers, Amsterdam (1987)"},{"key":"176_CR2","doi-asserted-by":"crossref","unstructured":"Balasubramonian, R., Albonesi, D., Buyuktosunoglu, A., Dwarkadas, S.: A dynamically tunable memory hierarchy. IEEE Trans. Comput. (2003)","DOI":"10.1109\/TC.2003.1234523"},{"key":"176_CR3","doi-asserted-by":"crossref","unstructured":"Catthoor, F., Danckart, K., Kulkarn, C., et\u00a0al.: Data Access and Storage Management for Embedded Programmable Processors. Kluwer, Dordrecht (2002)","DOI":"10.1007\/978-1-4757-4903-8"},{"key":"176_CR4","doi-asserted-by":"crossref","unstructured":"Cucchiara, R., Piccardi, M., Prati, A.: Neighbor cache prefetching for multimedia image and video processing. IEEE Trans. Multimedia (2004)","DOI":"10.1109\/TMM.2004.830806"},{"key":"176_CR5","unstructured":"Cunat, C., Gobert, J., Mathieu, Y.: A coprocessor for real-time mpeg4 facial animation on mobiles. In: Proceedings of ESTIMedia (2003)"},{"key":"176_CR6","doi-asserted-by":"crossref","unstructured":"Doweck, J.: Intel $$\\textregistered$$ smart memory access: minimizing latency on intel $$\\textregistered$$ coretm microarchitecture. Technology @Intel Magazine (2006)","DOI":"10.1109\/HOTCHIPS.2006.7477876"},{"key":"176_CR7","unstructured":"Dutta, H., Hannig, F., Teich, J.: Hierarchical partitioning for piecewise linear algorithms. In: IEEE PARELEC\u201906 (2006)"},{"key":"176_CR8","unstructured":"Fu, J., Patel, J., Janssens, B.: Stride directed prefetching in scalar processors. In: Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992. MICRO 25., pp. 102\u2013110 (1992)"},{"key":"176_CR9","doi-asserted-by":"crossref","unstructured":"Gac, N., Mancini, S., Desvignes, M., Houzet, D.: High speed 3D tomography on cpu, gpu and fpga. EURASIP J. Embedded Syst. (2008)","DOI":"10.1155\/2008\/930250"},{"key":"176_CR10","doi-asserted-by":"crossref","unstructured":"Guenther, T., Poliwoda, C., Reinhart, C., Hesser, J., Maenner, R., Meinzer, H., Baur, H.: Virim: A massively parallel processor for real-time volume visualization in medicine. Technical report, University of Mannheim (1995)","DOI":"10.1016\/0097-8493(95)00049-6"},{"key":"176_CR11","doi-asserted-by":"crossref","unstructured":"Igehy, H., Eldridge, M., Proudfoot, K.: Prefetching in a texture cache architecture. In: HWWS \u201998: Proceedings of the ACM SIGGRAPH\/EUROGRAPHICS Workshop on Graphics Hardware, pp. 133-ff. ACM, New York (1998)","DOI":"10.1145\/285305.285321"},{"key":"176_CR12","unstructured":"Kanus, U., Wetekam, G., Hirche, J.: Voxelcache: a cache-based memory architecture for volume graphics. In B. Mark, A. Schilling (eds.) Graphics Hardware, pp. 76\u201383. Eurographics Association (2003)"},{"key":"176_CR13","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1109\/AHS.2009.26","volume":"0","author":"P. Kaufmann","year":"2009","unstructured":"Kaufmann P., Plessl C., Platzner M.: Evocaches: application-specific adaptation of cache mappings. In: NASA\/ESA Conference on Adaptive Hardware and Systems, pp. 11\u201318 (2009)","journal-title":"Adaptive Hardware and Systems, NASA\/ESA Conference on"},{"key":"176_CR14","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1109\/40.946678","volume":"21","author":"D. Kim","year":"2001","unstructured":"Kim D., Managuli R., Kim Y.: Data cache and direct memory access in programming mediaprocessors. IEEE Micro. 21, 33\u201342 (2001)","journal-title":"Micro, IEEE"},{"key":"176_CR15","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/MM.2006.49","volume":"26","author":"M. Kistler","year":"2006","unstructured":"Kistler M., Perrone M., Petrini F.: Cell multiprocessor communication network: built for speed. IEEE Micro. 26, 10\u201323 (2006)","journal-title":"IEEE Micro"},{"issue":"7","key":"176_CR16","doi-asserted-by":"crossref","first-page":"943","DOI":"10.1016\/S0167-8191(97)00036-7","volume":"23","author":"C. K\u00f6se","year":"1997","unstructured":"K\u00f6se C., Chalmers A.: Profiling for efficient parallel volume visualisation. Parallel Comput. 23(7), 943\u2013952","journal-title":"Parallel Comput."},{"issue":"6","key":"176_CR17","doi-asserted-by":"crossref","first-page":"1013","DOI":"10.1109\/TMM.2008.2001385","volume":"10","author":"D. Kudithipudi","year":"2008","unstructured":"Kudithipudi D., Petko S., John E. (2008) Caches for multimedia workloads: power and energy tradeoffs. IEEE Trans. Multimedia 10(6), 1013\u20131021","journal-title":"IEEE Trans. Multim."},{"key":"176_CR18","doi-asserted-by":"crossref","unstructured":"Mancini, S., Desvignes, M.: Ray casting on a SoPC platform: algorithm and memory tradeoff. In: IEEE Conference on Computer Information Technology, Seoul, Korea (2006)","DOI":"10.1109\/CIT.2006.157"},{"key":"176_CR19","unstructured":"Mancini, S., Eveno, N.: An IIR based 2D adaptive and predictive cache for image processing. In: DCIS 2004, p. 85 (2004)"},{"key":"176_CR20","doi-asserted-by":"crossref","unstructured":"Mancini, S., Pierrefeu, L., Larabi, Z., Mathieu, Y.: Calibrating a predictive cache emulator for soc design. In: AHS\u20192010 Proceedings (2010)","DOI":"10.1109\/AHS.2010.5546246"},{"key":"176_CR21","unstructured":"NVIDIA. http:\/\/developer.download.nvidia.com\/"},{"key":"176_CR22","doi-asserted-by":"crossref","unstructured":"Osborne, R., Pfister, H., Lauer, H., McKenzie, N., Gibson, S., Hiatt, W., Ohkami, H.: Em-cube: an architecture for low-cost real-time volume rendering (1997)","DOI":"10.1145\/258694.258731"},{"key":"176_CR23","unstructured":"Patterson, D., Hennessy,J.: Computer Architecture: A Quantitative Approach, 2nd edn. Morgan Kaufmann, San Francisco (1996)"},{"key":"176_CR24","doi-asserted-by":"crossref","unstructured":"Pfister, H., Kaufman, A.: Cube-4: A scalable architecture for real-time volume rendering. In: Proceedings of the 1996 symposium on Volume visualization, pp. 47\u201354 (1996)","DOI":"10.1109\/SVV.1996.558042"},{"key":"176_CR25","doi-asserted-by":"crossref","unstructured":"Pfister, H., Kaufman, A., cker Chiueh, T.: Cube-3: A real-time architecture for high-resolution volume visualization. In: In ACM\/IEEE Symposium on Volume Visualization, pp. 75\u201383 (1994)","DOI":"10.1145\/197938.197969"},{"key":"176_CR26","doi-asserted-by":"crossref","unstructured":"Qadri, M.Y., McDonald-Maier, K.D.: Data cache-energy and throughput models: design exploration for embedded processors. EURASIP J. Embed. Syst. (2009)","DOI":"10.1155\/2009\/725438"},{"key":"176_CR27","doi-asserted-by":"crossref","unstructured":"Silpa, B.V.N., Patney, A., Krishna, T., Panda, P.R., Visweswaran, G.S.: Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. In: ICCAD \u201908: Proceedings of the 2008 IEEE\/ACM International Conference on Computer-Aided Design, pp. 559\u2013564. IEEE Press, Piscataway (2008)","DOI":"10.1109\/ICCAD.2008.4681631"},{"key":"176_CR28","doi-asserted-by":"crossref","first-page":"473","DOI":"10.1145\/356887.356892","volume":"14","author":"A.J. Smith","year":"1982","unstructured":"Smith A.J.: Caches memories. Comput. Surv. 14, 473\u2013530 (1982)","journal-title":"Comput. Surv."},{"key":"176_CR29","doi-asserted-by":"crossref","unstructured":"Toczek, T., Mancini, S.: Efficient memory management for uniform and recursive grid traversal. In: Algorithm-Architecture Matching for Signal and Image Processing. Springer, Berlin (2010) (Accepted)","DOI":"10.1007\/978-90-481-9965-5_2"},{"key":"176_CR30","unstructured":"Wechsler, O.: Inside Intel $$\\textregistered$$ Core Microarchitecture, Setting New Standards for Energy-Efficient Performance. Technical report, http:\/\/www.intel.com , 2010"},{"key":"176_CR31","doi-asserted-by":"crossref","unstructured":"Wetekam, G., Staneker, D., Kanus, U., Wand, M.: A hardware architecture for multi-resolution volume rendering. In: HWWS \u201905: Proceedings of the ACM SIGGRAPH\/EUROGRAPHICS Conference on Graphics hardware, pp. 45\u201351. ACM, New York (2005)","DOI":"10.1145\/1071866.1071874"},{"key":"176_CR32","unstructured":"Xilinx. Virtex-5 fpga user guide. http:\/\/www.xilinx.com\/"}],"container-title":["Journal of Real-Time Image Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11554-010-0176-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11554-010-0176-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11554-010-0176-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,24]],"date-time":"2025-02-24T19:23:52Z","timestamp":1740425032000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11554-010-0176-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,8,19]]},"references-count":32,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,3]]}},"alternative-id":["176"],"URL":"https:\/\/doi.org\/10.1007\/s11554-010-0176-3","relation":{},"ISSN":["1861-8200","1861-8219"],"issn-type":[{"type":"print","value":"1861-8200"},{"type":"electronic","value":"1861-8219"}],"subject":[],"published":{"date-parts":[[2010,8,19]]}}}