{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T13:39:13Z","timestamp":1740145153692,"version":"3.37.3"},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2016,4,5]],"date-time":"2016-04-05T00:00:00Z","timestamp":1459814400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft (DE)","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Real-Time Image Proc"],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1007\/s11554-016-0587-x","type":"journal-article","created":{"date-parts":[[2016,4,5]],"date-time":"2016-04-05T08:32:20Z","timestamp":1459845140000},"page":"549-564","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures"],"prefix":"10.1007","volume":"14","author":[{"given":"C.","family":"Hartmann","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"H\u00e4ublein","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Reichenbach","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Fey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2016,4,5]]},"reference":[{"key":"587_CR1","doi-asserted-by":"crossref","unstructured":"Bailey, D.G.: Design for embedded image processing on FPGAs. Wiley, Singapore. ISBN 978-0470828498 (2011)","DOI":"10.1002\/9780470828519"},{"key":"587_CR2","unstructured":"Berschneider, S., Herglotz, C., Reichenbach, M., Fey, D., Kaup, A.: Estimating video decoding energies and processing times utilizing virtual hardware. In: Proceedings of 3PMCES workshop. Design, automation and test in Europe (DATE), pp. 1\u20132, Dresden, Germany. EDAA (2014)"},{"key":"587_CR3","doi-asserted-by":"crossref","unstructured":"Chang, C., Lu, C., Yang, W.P., Chu, W.C., Yang, C., Hsiung, P.: A sysml based requirement modeling automatic transformation approach. In: 2014 IEEE 38th international computer software and applications conference workshops (COMPSACW), pp. 474\u2013479, Vasteras, Sweden. IEE (2015)","DOI":"10.1109\/COMPSACW.2014.80"},{"key":"587_CR4","doi-asserted-by":"publisher","first-page":"153","DOI":"10.1186\/1687-6180-2013-153","volume":"2013","author":"H Chenini","year":"2013","unstructured":"Chenini, H., Derutin, J. P., Aufrere, R., Chapuis, R.: Parallel embedded processor architecture for fpga-based image processing using parallel software skeletons. EURASIP J Adv Signal Process. 2013, 153 (2013). doi: 10.1186\/1687-6180-2013-153","journal-title":"EURASIP J Adv Signal Process."},{"key":"587_CR5","unstructured":"Hartmann, C., Reichenbach, M., Fey, D.: Ipol\u2014a domain specific language for image processing applications. In: Proceedings of the international symposium on international conference on systems, pp. 40\u201343, Barcelona, Spain. IARIA (2015)"},{"key":"587_CR6","doi-asserted-by":"crossref","unstructured":"Hegarty, J., Brunhaver, J., DeVito, Z., Ragan-Kelly, J., Cohen, N., Bell, S., Vasilyev, A., Horowitz, M., Hanrahan, P.: Darkroom: compiling high-level image processing code into hardware pipelines. Transactions on graphics (TOG)\u2014proceedings of ACM SIGGRAPH 2014, pp. 144:1\u2013144:11 (2014)","DOI":"10.1145\/2601097.2601174"},{"key":"587_CR7","unstructured":"Imperas: http:\/\/www.ovpworld.org . Accessed 31 Mar 2016"},{"key":"587_CR8","unstructured":"Intel: http:\/\/www.intel.de\/content\/www\/de\/de\/cofluent\/intel-cofluent-studio.html . Accessed 31 Mar 2016"},{"key":"587_CR9","doi-asserted-by":"crossref","unstructured":"Kerbyson, D. J., Atherton, T. J.: Circle detection using hough transform filters. In: Image processing and its applications, pp. 370\u2013374, Edinburgh, Scotland. IEEE (1995)","DOI":"10.1049\/cp:19950683"},{"key":"587_CR10","doi-asserted-by":"crossref","unstructured":"Milford, M., McAllister, J.: Valved dataflow for fpga memory hierarchy synthesis. In: Proceedings acoustics, speech and signal processing (ICASSP), pp. 1645\u20131648, Kyoto, Japan. IEEE (2012)","DOI":"10.1109\/ICASSP.2012.6288211"},{"key":"587_CR11","unstructured":"Patterson, D., Hennessy, J.: Computer organization and design. Morgan Kaufmann. Oxford, UK. ISBN 978-0124077263 (2014)"},{"key":"587_CR12","unstructured":"Reiche, O., H\u00e4ublein, K., Reichenbach, M., Hannig, F., Teich, J., Fey, D.: Automatic optimization of hardware accelerators for image processing. In: Proceedings of the DATE friday workshop on heterogeneous architectures and design methods for embedded image systems (HIS), pp. 10\u201315. Grenoble, France (2015)"},{"key":"587_CR13","unstructured":"Reiche, O., H\u00e4ublein, K., Reichenbach, M., Hannig, F., Teich, J., Fey, D.: Automatic optimization of hardware accelerators for image processing. In: Heterogeneous architectures and design methods for embedded image systems (HIS 2015), pp. 10\u201315. Grenoble, France (2015)"},{"key":"587_CR14","doi-asserted-by":"crossref","unstructured":"Reichenbach, M., Pfundt, B., Fey, D.: Framework for parameter analysis of fpga-based image processing architectures. In: Proceedings of international conference on systems, architectures, modeling and simulation (SAMOS), pp. 1\u20137, Samos, Greece. IEEE (2015)","DOI":"10.1109\/SAMOS.2015.7363664"},{"key":"587_CR15","doi-asserted-by":"crossref","unstructured":"Schmidt, M., Reichenbach, M., Fey, D.: A generic vhdl template for 2d stencil code applications on fpgas. In: International symposium on object\/component\/service-oriented real-Time distributed computing workshops (ISORCW), pp. 180\u2013187, Shenzen, China. IEEE (2012)","DOI":"10.1109\/ISORCW.2012.39"},{"key":"587_CR16","doi-asserted-by":"crossref","unstructured":"Schumacher, F., Holzer, M., Greiner, T., Rosenstiel, W.: Modeling and code generation of recursive algorithms with extended uml activity diagrams. In: Radioelektronika (RADIOELEKTRONIKA), 21st international conference, pp. 1\u20134, Brno, Czech. IEEE (2011)","DOI":"10.1109\/RADIOELEK.2011.5936437"},{"key":"587_CR17","doi-asserted-by":"crossref","unstructured":"Vidal, J., Lamotte, F., Gogniat, G., Soulard, P., Diguet, J.: A co-design approach for embedded system modeling and code generation with uml and marte. In: Proceedings of design, automation and test in Europe (DATE) conference and exhibition, pp. 226\u2013231, Nice, France. EDAA (2009)","DOI":"10.1109\/DATE.2009.5090662"},{"key":"587_CR18","doi-asserted-by":"crossref","unstructured":"Burge, M.J., Burger, W.: Principles of digital image processing: core algorithms. Springer, London, UK. ISBN 978-1848001947 (2009)","DOI":"10.1007\/978-1-84800-191-6"},{"key":"587_CR19","unstructured":"Burge, M.J., Burger, W.: Principles of digital image processing: fundamental techniques. Springer, London, UK. ISBN 978-1848001947 (2011)"},{"key":"587_CR20","doi-asserted-by":"publisher","first-page":"483","DOI":"10.1049\/iet-ipr.2011.0025","volume":"6","author":"J Yoo","year":"2012","unstructured":"Yoo, J., Ahn, C.: Image matching using peak signal-to-noise ratio based occlusion detection. IET Image Process. 6, 483\u2013495 (2012). doi: 10.1049\/iet-ipr.2011.0025","journal-title":"IET Image Process"},{"key":"587_CR21","doi-asserted-by":"publisher","first-page":"508","DOI":"10.1109\/TSMC.1987.4309068","volume":"17","author":"OA Zuniga","year":"1987","unstructured":"Zuniga, O.A., Haralick, R.M.: Integrated directional derivative gradient operator. IEEE Trans. Syst. Man Cybern. 17, 508\u2013517 (1987). doi: 10.1109\/TSMC.1987.4309068","journal-title":"IEEE Trans. Syst. Man Cybern."}],"container-title":["Journal of Real-Time Image Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11554-016-0587-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11554-016-0587-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11554-016-0587-x","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11554-016-0587-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,17]],"date-time":"2022-06-17T03:48:36Z","timestamp":1655437716000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11554-016-0587-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4,5]]},"references-count":21,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2018,3]]}},"alternative-id":["587"],"URL":"https:\/\/doi.org\/10.1007\/s11554-016-0587-x","relation":{},"ISSN":["1861-8200","1861-8219"],"issn-type":[{"type":"print","value":"1861-8200"},{"type":"electronic","value":"1861-8219"}],"subject":[],"published":{"date-parts":[[2016,4,5]]}}}