{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:46:45Z","timestamp":1765356405050},"reference-count":37,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2018,7,30]],"date-time":"2018-07-30T00:00:00Z","timestamp":1532908800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Real-Time Image Proc"],"published-print":{"date-parts":[[2019,2]]},"DOI":"10.1007\/s11554-018-0808-6","type":"journal-article","created":{"date-parts":[[2018,7,30]],"date-time":"2018-07-30T08:28:51Z","timestamp":1532939331000},"page":"143-160","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["A templated programmable architecture for highly constrained embedded HD video processing"],"prefix":"10.1007","volume":"16","author":[{"given":"Mathieu","family":"Thevenin","sequence":"first","affiliation":[]},{"given":"Michel","family":"Paindavoine","sequence":"additional","affiliation":[]},{"given":"Renaud","family":"Schmit","sequence":"additional","affiliation":[]},{"given":"Barthelemy","family":"Heyrman","sequence":"additional","affiliation":[]},{"given":"Laurent","family":"Letellier","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,7,30]]},"reference":[{"key":"808_CR1","doi-asserted-by":"publisher","unstructured":"Chalamalasetti, S.R., Purohit, S., Margala, M., Vanderbauwhede, W.: MORA\u2014an architecture and programming model for a resource efficient coarse grained reconfigurable processor. In: 2009 NASA\/ESA conference on adaptive hardware and systems, IEEE, pp 389\u2013396 (2009). \n                    https:\/\/doi.org\/10.1109\/AHS.2009.37","DOI":"10.1109\/AHS.2009.37"},{"issue":"11","key":"808_CR2","doi-asserted-by":"publisher","first-page":"1499","DOI":"10.1109\/TCSVT.2010.2077770","volume":"20","author":"WM Chao","year":"2010","unstructured":"Chao, W.M., Chen, L.G.: Pyramid architecture for 3840 x 2160 quad full high definition 30 frames\/s video acquisition. Circ Syst Video Technol IEEE Trans 20(11), 1499\u20131508 (2010). \n                    https:\/\/doi.org\/10.1109\/TCSVT.2010.2077770","journal-title":"Circ Syst Video Technol IEEE Trans"},{"issue":"9","key":"808_CR3","doi-asserted-by":"publisher","first-page":"1223","DOI":"10.1109\/TCSVT.2008.928529","volume":"18","author":"JC Chen","year":"2008","unstructured":"Chen, J.C., Chien, S.Y.: CRISP: coarse-grained reconfigurable image stream processor for digital still cameras and camcorders. IEEE Trans Circ Syst Video Technol 18(9), 1223\u20131236 (2008). \n                    https:\/\/doi.org\/10.1109\/TCSVT.2008.928529","journal-title":"IEEE Trans Circ Syst Video Technol"},{"key":"808_CR4","doi-asserted-by":"publisher","unstructured":"Chen, P.Y., Lien, C.Y., Lin, Y.M.: A real-time image denoising chip. In: Circuits and systems, 2008. ISCAS 2008. IEEE international symposium on, pp. 3390\u20133393 (2008). \n                    https:\/\/doi.org\/10.1109\/ISCAS.2008.4542186","DOI":"10.1109\/ISCAS.2008.4542186"},{"key":"808_CR5","doi-asserted-by":"publisher","unstructured":"Chen, T.H., Chen, J.C., Cheng, T.Y., Chien, S.Y.: CRISP-DS: dual-stream coarse-grained reconfigurable image stream processor for HD digital camcorders and digital still cameras. In: Solid-state circuits conference, 2009. A-SSCC 2009. IEEE Asian, IEEE, pp. 193\u2013196 (2009). \n                    https:\/\/doi.org\/10.1109\/asscc.2009.5357150","DOI":"10.1109\/asscc.2009.5357150"},{"issue":"9","key":"808_CR6","doi-asserted-by":"publisher","first-page":"2481","DOI":"10.1109\/TCSI.2017.2698019","volume":"64","author":"F Conti","year":"2017","unstructured":"Conti, F., Schilling, R., Schiavone, P.D., Pullini, A., Rossi, D., Gurkaynak, F.K., Muehlberghuber, M., Gautschi, M., Loi, I., Haugou, G., Mangard, S., Benini, L.: An iot endpoint system-on-chip for secure and energy-efficient near-sensor analytics. IEEE Trans Circ Syst I Regular Papers 64(9), 2481\u20132494 (2017). \n                    https:\/\/doi.org\/10.1109\/TCSI.2017.2698019","journal-title":"IEEE Trans Circ Syst I Regular Papers"},{"key":"808_CR7","doi-asserted-by":"publisher","unstructured":"David, R., Chillet, D., Pillement, S., Sentieys, O.: DART: a dynamically reconfigurable architecture dealing with future mobile telecommunications constr. In: Proceedings 16th international parallel and distributed processing symposium, IEEE Comput. Soc, pp. 156+ (2002). \n                    https:\/\/doi.org\/10.1109\/IPDPS.2002.1016554","DOI":"10.1109\/IPDPS.2002.1016554"},{"key":"808_CR8","doi-asserted-by":"publisher","unstructured":"Desoli, G., Chawla, N., Boesch, T., Singh, S.P., Guidetti, E., Ambroggi, F.D., Majo, T., Zambotti, P., Ayodhyawasi, M., Singh, H., Aggarwal, N.: 14.1 a 2.9tops\/w deep convolutional neural network soc in fd-soi 28nm for intelligent embedded systems. In: 2017 IEEE international solid-state circuits conference (ISSCC), pp. 238\u2013239 (2017). \n                    https:\/\/doi.org\/10.1109\/ISSCC.2017.7870349","DOI":"10.1109\/ISSCC.2017.7870349"},{"key":"808_CR9","doi-asserted-by":"publisher","unstructured":"Di\u00a0Carlo, S., Prinetto, P., Rolfo, D., Trotta, P.: AIdi: an adaptive image denoising FPGA-based IP-core for real-time applications. In: Adaptive hardware and systems (AHS), 2013 NASA\/ESA conference on, pp. 99\u2013106 (2013). \n                    https:\/\/doi.org\/10.1109\/AHS.2013.6604232","DOI":"10.1109\/AHS.2013.6604232"},{"key":"808_CR10","unstructured":"Du, Y., Du, L., Li, Y., Su, J., Chang, M.F.: A streaming accelerator for deep convolutional neural networks with image and feature decomposition for resource-limited system applications. CoRR abs\/1709.05116:1\u20135 (2017). \n                    http:\/\/arxiv.org\/abs\/1709.05116\n                    \n                  \n                           (1709.05116)"},{"key":"808_CR11","first-page":"4","volume":"1","author":"S Evain","year":"2006","unstructured":"Evain, S., Diguet, J.P.: Houzet D (2006) NoC design flow for TDMA and QoS management in a GALS context. EURASIP J Embedded Syst 1, 4\u20134 (2006)","journal-title":"EURASIP J Embedded Syst"},{"key":"808_CR12","unstructured":"Franzen, R.: Kodak lossless true color image suite (1999). \n                    http:\/\/r0k.us\/graphics\/kodak\/"},{"key":"808_CR13","doi-asserted-by":"publisher","unstructured":"Garcia-Lamont, J., Aleman-Arce, M., Waissman-Vilanova, J.: A digital real time image demosaicking implementation for high definition video cameras. In: Electronics, robotics and automotive mechanics conference, 2008. CERMA \u201908, pp. 565\u2013569 (2008). \n                    https:\/\/doi.org\/10.1109\/CERMA.2008.78","DOI":"10.1109\/CERMA.2008.78"},{"issue":"8","key":"808_CR14","doi-asserted-by":"publisher","first-page":"960","DOI":"10.1109\/TC.2004.48","volume":"53","author":"A Gentile","year":"2004","unstructured":"Gentile, A., Wills, D.S.: Portable video supercomputing. IEEE Trans Comput 53(8), 960\u2013973 (2004). \n                    https:\/\/doi.org\/10.1109\/TC.2004.48","journal-title":"IEEE Trans Comput"},{"key":"808_CR15","unstructured":"Global Sources: Mobile phone camera modules\u2014mobile phones spur output growth, r&d activities in camera modules segment. Glob Sour Part 1\u20134: NA (2009)"},{"issue":"2","key":"808_CR16","doi-asserted-by":"publisher","first-page":"60","DOI":"10.1109\/40.848473","volume":"20","author":"R Gonzalez","year":"2000","unstructured":"Gonzalez, R.: Xtensa: a configurable and extensible processor. Micro IEEE 20(2), 60\u201370 (2000). \n                    https:\/\/doi.org\/10.1109\/40.848473","journal-title":"Micro IEEE"},{"key":"808_CR17","doi-asserted-by":"publisher","unstructured":"Goossens, K., Hansson, A.: The aethereal network on chip after ten years: goals, evolution, lessons, and future. In: Proceedings of the 47th design automation conference, ACM, New York, NY, USA, DAC \u201910, pp. 306\u2013311 (2010). \n                    https:\/\/doi.org\/10.1145\/1837274.1837353","DOI":"10.1145\/1837274.1837353"},{"issue":"5","key":"808_CR18","doi-asserted-by":"publisher","first-page":"414","DOI":"10.1109\/MDT.2005.99","volume":"22","author":"K Goossens","year":"2005","unstructured":"Goossens, K., Dielissen, J., Radulescu, A.: Aethereal network on chip: concepts, architectures, and implementations. Design Test Comput IEEE 22(5), 414\u2013421 (2005). \n                    https:\/\/doi.org\/10.1109\/MDT.2005.99","journal-title":"Design Test Comput IEEE"},{"issue":"2","key":"808_CR19","doi-asserted-by":"publisher","first-page":"225","DOI":"10.1007\/s11265-008-0309-0","volume":"60","author":"M Hartmann","year":"2010","unstructured":"Hartmann, M., Pantazis, V., Vander Aa, T., Berekovic, M., Hochberger, C.: Still image processing on coarse-grained reconfigurable array architectures. J Signal Process Syst 60(2), 225\u2013237 (2010). \n                    https:\/\/doi.org\/10.1007\/s11265-008-0309-0","journal-title":"J Signal Process Syst"},{"key":"808_CR20","doi-asserted-by":"publisher","first-page":"206","DOI":"10.1016\/j.vlsi.2017.06.005","volume":"59","author":"W Jin","year":"2017","unstructured":"Jin, W., He, G., He, W., Mao, Z.: A 12-bit \n                    \n                      \n                    \n                    $$4928 \\times 3264$$\n                    \n                      \n                        \n                          4928\n                          \u00d7\n                          3264\n                        \n                      \n                    \n                   pixel cmos image signal processor for digital still cameras. Integr VLSI J 59, 206\u2013217 (2017). \n                    https:\/\/doi.org\/10.1016\/j.vlsi.2017.06.005","journal-title":"Integr VLSI J"},{"key":"808_CR21","unstructured":"Juan, E.S.S.: Optimizing VLIW architecture for multimedia application. PhD thesis, Universitat Polit\u00e8cnica de Catalunya (2007)"},{"issue":"8","key":"808_CR22","doi-asserted-by":"publisher","first-page":"54","DOI":"10.1109\/MC.2003.1220582","volume":"36","author":"U Kapasi","year":"2003","unstructured":"Kapasi, U., Rixner, S., Dally, W., Khailany, B., Ahn, J., Mattson, P., Owens, J.: Programmable stream processors. Computer 36(8), 54\u201362 (2003). \n                    https:\/\/doi.org\/10.1109\/MC.2003.1220582","journal-title":"Computer"},{"issue":"1","key":"808_CR23","doi-asserted-by":"publisher","first-page":"202","DOI":"10.1109\/JSSC.2007.909331","volume":"43","author":"BK Khailany","year":"2008","unstructured":"Khailany, B.K., Williams, J., Long, E.P., Rygh, M., Tovey, D.W., Dally, W.J.: A programmable 512 GOPS stream processor for signal, image, and video processing. Solid State Circ IEEE J 43(1), 202\u2013213 (2008). \n                    https:\/\/doi.org\/10.1109\/JSSC.2007.909331","journal-title":"Solid State Circ IEEE J"},{"issue":"1","key":"808_CR24","doi-asserted-by":"publisher","first-page":"75","DOI":"10.1109\/TVLSI.2007.912133","volume":"16","author":"S Khawam","year":"2008","unstructured":"Khawam, S., Nousias, I., Milward, M., Yi, Y., Muir, M., Arslan, T.: The reconfigurable instruction cell array. IEEE Trans Very Large Scale Integr (VLSI) Syst 16(1), 75\u201385 (2008). \n                    https:\/\/doi.org\/10.1109\/TVLSI.2007.912133","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"808_CR25","doi-asserted-by":"publisher","unstructured":"Lopez, D., Llosa, J., Valero, M., Ayguade, E.: Widening resources: a cost-effective technique for aggressive ILP architectures. In: Microarchitecture, 1998. MICRO-31. Proceedings. 31st annual ACM\/IEEE international symposium on, pp. 237\u2013246 (1998). \n                    https:\/\/doi.org\/10.1109\/MICRO.1998.742785","DOI":"10.1109\/MICRO.1998.742785"},{"key":"808_CR26","doi-asserted-by":"publisher","unstructured":"Millberg, M., Nilsson, E., Thid, R., Kumar, S., Jantsch, A.: The nostrum backbone-a communication protocol stack for networks on chip. In: VLSI design, 2004. Proceedings. 17th international conference on, pp. 693\u2013696 (2004). \n                    https:\/\/doi.org\/10.1109\/ICVD.2004.1261005","DOI":"10.1109\/ICVD.2004.1261005"},{"key":"808_CR27","doi-asserted-by":"publisher","unstructured":"Paindavoine, M., Boisard, O., Carbon, A., Philippe, J.M., Brousse, O.: Neurodsp accelerator for face detection application. In: Proceedings of the 25th edition on great lakes symposium on VLSI, ACM, New York, NY, USA, GLSVLSI \u201915, pp. 211\u2013215 (2015). \n                    https:\/\/doi.org\/10.1145\/2742060.2743769\n                    \n                  . \n                    http:\/\/doi.acm.org\/10.1145\/2742060.2743769","DOI":"10.1145\/2742060.2743769"},{"key":"808_CR28","unstructured":"Philippe, J.M., Carbon, A., Schmit, R.: Neurodsp: a multi-purpose energy-optimized accelerator for neural networks. In: Design, automation and test in Europe (DATE) 2016 conference, p. UB06.9 (2016). \n                    https:\/\/www.date-conference.com\/date16\/conference\/session\/UB06"},{"key":"808_CR29","unstructured":"Rixner, S., Dally, W.J., Khailany, B., Mattson, P., Kapasi, U.J., Owens, J.D.: Register organization for media processing. In: Sixth international symposium on high-performance computer architecture, 2000. HPCA-6, pp. 375\u2013386 (2000)"},{"key":"808_CR30","doi-asserted-by":"publisher","first-page":"170","DOI":"10.1016\/j.sse.2015.11.015","volume":"117","author":"D Rossi","year":"2016","unstructured":"Rossi, D., Pullini, A., Loi, I., Gautschi, M., G\u00fcrkaynak, F.K., Bartolini, A., Flatresse, P., Benini, L.: A 60 GOPS\/W, \n                    \n                      \n                    \n                    $$-1.8$$\n                    \n                      \n                        \n                          -\n                          1.8\n                        \n                      \n                    \n                  \u20130.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology. Solid State Electron 117, 170\u2013184 (2016). \n                    https:\/\/doi.org\/10.1016\/j.sse.2015.11.015","journal-title":"Solid State Electron"},{"key":"808_CR31","first-page":"177","volume":"3","author":"T Saidani","year":"2011","unstructured":"Saidani, T., Lacassagne, L., Falcou, J., Tadonki, C., Bouaziz, S.: Parallelization schemes for memory optimization on the cell processor: a case study on the harris corner detector. Transaction HiPEAC 3, 177\u2013200 (2011)","journal-title":"Transaction HiPEAC"},{"key":"808_CR32","doi-asserted-by":"publisher","unstructured":"Seo, S., Dreslinski, R.G., Woh, M., Chakrabarti, C., Mahlke, S., Mudge, T.: Diet soda: a power-efficient processor for digital cameras. In: 2010 ACM\/IEEE international symposium on low-power electronics and design (ISLPED), pp. 79\u201384 (2010). \n                    https:\/\/doi.org\/10.1145\/1840845.1840862","DOI":"10.1145\/1840845.1840862"},{"issue":"5","key":"808_CR33","doi-asserted-by":"publisher","first-page":"465","DOI":"10.1109\/12.859540","volume":"49","author":"H Singh","year":"2000","unstructured":"Singh, H., Lee, M.H., Lu, G., Kurdahi, F.J., Bagherzadeh, N., Chaves Filho, E.M.: MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Transactions on Computers 49(5), 465\u2013481 (2000). \n                    https:\/\/doi.org\/10.1109\/12.859540","journal-title":"IEEE Transactions on Computers"},{"key":"808_CR34","doi-asserted-by":"publisher","unstructured":"Sparsoe, J.: Design of networks-on-chip for real-time multi-processor systems-on-chip. In: Application of concurrency to system design (ACSD), 2012 12th international conference on, pp. 1\u20135 (2012). \n                    https:\/\/doi.org\/10.1109\/ACSD.2012.27","DOI":"10.1109\/ACSD.2012.27"},{"key":"808_CR35","doi-asserted-by":"publisher","unstructured":"Texier, M., Piriou, E., Thevenin, M., David, R.: Designing processors using mass, a modular and lightweight instruction-level exploration tool. In: Design and architectures for signal and image processing (DASIP), 2011 conference on, pp. 1\u20136 (2011). \n                    https:\/\/doi.org\/10.1109\/DASIP.2011.6136870","DOI":"10.1109\/DASIP.2011.6136870"},{"key":"808_CR36","unstructured":"Thevenin, M., Letellier, L.: Device for the parallel processing of a data stream. International Patent WO\/2010\/037570 PCT\/EP2009\/057033:1 (2008)"},{"key":"808_CR37","doi-asserted-by":"publisher","unstructured":"Thevenin, M., Paindavoine, M., Letellier, L., Heyrman, B.: Embedded processor extensions for image processing. In: Proc. SPIE 7001, photonics in multimedia II, vol 7001, pp. 70,010B\u201311 (2008). \n                    https:\/\/doi.org\/10.1117\/12.780852","DOI":"10.1117\/12.780852"}],"container-title":["Journal of Real-Time Image Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11554-018-0808-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11554-018-0808-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11554-018-0808-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,29]],"date-time":"2019-07-29T23:30:18Z","timestamp":1564443018000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11554-018-0808-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7,30]]},"references-count":37,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2019,2]]}},"alternative-id":["808"],"URL":"https:\/\/doi.org\/10.1007\/s11554-018-0808-6","relation":{},"ISSN":["1861-8200","1861-8219"],"issn-type":[{"value":"1861-8200","type":"print"},{"value":"1861-8219","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,7,30]]},"assertion":[{"value":"11 December 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"18 July 2018","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"30 July 2018","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}