{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T01:41:34Z","timestamp":1774662094745,"version":"3.50.1"},"reference-count":37,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2021,8,11]],"date-time":"2021-08-11T00:00:00Z","timestamp":1628640000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,8,11]],"date-time":"2021-08-11T00:00:00Z","timestamp":1628640000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100005145","name":"Basic Research Program of Jiangsu Province","doi-asserted-by":"publisher","award":["BK20201045"],"award-info":[{"award-number":["BK20201045"]}],"id":[{"id":"10.13039\/501100005145","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Real-Time Image Proc"],"published-print":{"date-parts":[[2022,2]]},"DOI":"10.1007\/s11554-021-01161-4","type":"journal-article","created":{"date-parts":[[2021,8,11]],"date-time":"2021-08-11T17:03:49Z","timestamp":1628701429000},"page":"61-71","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":19,"title":["Efficient binary 3D convolutional neural network and hardware accelerator"],"prefix":"10.1007","volume":"19","author":[{"given":"Guoqing","family":"Li","sequence":"first","affiliation":[]},{"given":"Meng","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Qianru","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Zhijian","family":"Lin","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,8,11]]},"reference":[{"issue":"5","key":"1161_CR1","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/s11554-019-00938-y","volume":"17","author":"M Arredondo-Velazquez","year":"2020","unstructured":"Arredondo-Velazquez, M., Diaz-Carmona, J., Torres-Huitzil, C., Padilla-Medina, A., Prado-Olivarez, J.: A streaming architecture for Convolutional Neural Networks based on layer operations chaining. J. Real-Time Image Process. 17(5), 1\u201319 (2020)","journal-title":"J. Real-Time Image Process."},{"key":"1161_CR2","unstructured":"Courbariaux, M., Bengio, Y., David, J.P.: BinaryConnect: Training Deep Neural Networks with binary weights during propagations. Adv. Neural Inf. Process. Syst. (NeurIPS) pp. 3123\u20133131 (2015)"},{"key":"1161_CR3","unstructured":"Courbariaux, M., Hubara, I., Soudry, D., El-Yaniv, R., Bengio, Y.: Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to + 1 or \u2013 1. arXiv preprint arXiv: 1602.02830 (2016)"},{"key":"1161_CR4","doi-asserted-by":"crossref","unstructured":"Cui, Y., Shi, Y., Sun, X., Yin, W.: S-Net: A Lightweight Convolutional Neural Network for N-Dimensional Signals. In: IEEE International Conference on Multimedia and Expo Workshops (ICMEW), pp. 1\u20134 (2018)","DOI":"10.1109\/ICMEW.2018.8551506"},{"key":"1161_CR5","doi-asserted-by":"crossref","unstructured":"Fan, H., Niu, X., Liu, Q., Luk, W.: F-C3D: FPGA-based 3-dimensional convolutional neural network. In: IEEE International Conference on Multimedia and Expo Workshops, pp. 1\u20134 (2017)","DOI":"10.23919\/FPL.2017.8056779"},{"key":"1161_CR6","doi-asserted-by":"crossref","unstructured":"Gagliardi, A., de Gioia, F., Saponara, S.: A real-time video smoke detection algorithm based on Kalman filter and CNN. J. Real-Time Image Process. 1\u201311 (2021)","DOI":"10.1007\/s11554-021-01094-y"},{"issue":"2","key":"1161_CR7","doi-asserted-by":"publisher","first-page":"652","DOI":"10.1109\/TPAMI.2019.2938758","volume":"43","author":"S Gao","year":"2021","unstructured":"Gao, S., Cheng, M., Zhao, K., Zhang, X., Yang, M., Torr, P.H.S.: Res2net: a new multi-scale backbone architecture. IEEE Trans. Pattern Anal. Mach. Intell. 43(2), 652\u2013662 (2021)","journal-title":"IEEE Trans. Pattern Anal. Mach. Intell."},{"key":"1161_CR8","doi-asserted-by":"crossref","unstructured":"Guo, P., Ma, H., Chen, R., Li, P., Xie, S., Wang, D.: FBNA: A Fully Binarized Neural Network Accelerator. In: 28th International Conference on Field Programmable Logic and Applications, (FPL), pp. 51\u201354 (2018)","DOI":"10.1109\/FPL.2018.00016"},{"key":"1161_CR9","doi-asserted-by":"crossref","unstructured":"He, K., Zhang, X., Ren, S., Sun, J.: Deep Residual Learning for Image Recognition. In: IEEE Conference on Computer Vision and Pattern Recognition (CVPR), pp. 770\u2013778 (2016)","DOI":"10.1109\/CVPR.2016.90"},{"issue":"1","key":"1161_CR10","doi-asserted-by":"publisher","first-page":"221","DOI":"10.1109\/TPAMI.2012.59","volume":"35","author":"S Ji","year":"2012","unstructured":"Ji, S., Xu, W., Yang, M., Yu, K.: 3D convolutional neural networks for human action recognition. IEEE Trans. Pattern Anal. Mach. Intell. 35(1), 221\u2013231 (2012)","journal-title":"IEEE Trans. Pattern Anal. Mach. Intell."},{"issue":"1","key":"1161_CR11","doi-asserted-by":"publisher","first-page":"47","DOI":"10.26555\/ijain.v3i1.89","volume":"3","author":"M Latah","year":"2017","unstructured":"Latah, M.: Human action recognition using support vector machines and 3D convolutional neural networks. Int. Jo. Adv. Intell. Inform. 3(1), 47\u201355 (2017)","journal-title":"Int. Jo. Adv. Intell. Inform."},{"key":"1161_CR12","doi-asserted-by":"crossref","unstructured":"Li, G., Zhang, M., Duan, B., Zhang, Q., Tong, G.: Kernel Sharing in the Channel Dimension to Improve Parameters Efficiency. In: 2019 International Conference on Computing, Electronics Communications Engineering (iCCECE), pp. 78\u201382 (2019)","DOI":"10.1109\/iCCECE46942.2019.8941818"},{"key":"1161_CR13","doi-asserted-by":"publisher","first-page":"107610","DOI":"10.1016\/j.patcog.2020.107610","volume":"109","author":"G Li","year":"2021","unstructured":"Li, G., Zhang, M., Li, J., Lv, F., Tong, G.: Efficient densely connected convolutional neural networks. Pattern Recognit. 109, 107610 (2021)","journal-title":"Pattern Recognit."},{"issue":"5","key":"1161_CR14","doi-asserted-by":"publisher","first-page":"1703","DOI":"10.1007\/s11554-019-00931-5","volume":"17","author":"J Li","year":"2020","unstructured":"Li, J., Long, X., Hu, S., Hu, Y., Gu, Q., Xu, D.: A novel hardware-oriented ultra-high-speed object detection algorithm based on convolutional neural network. J. Real-Time Image Process. 17(5), 1703\u20131714 (2020)","journal-title":"J. Real-Time Image Process."},{"key":"1161_CR15","doi-asserted-by":"publisher","unstructured":"Li, J., Wang, T., Zhou, Y., Wang, Z., Snoussi, H.: Using Gabor filter in 3D convolutional neural networks for human action recognition. In: Chinese Control Conference (CCC), pp. 11139\u201311144 (2017). https:\/\/doi.org\/10.23919\/ChiCC.2017.8029134","DOI":"10.23919\/ChiCC.2017.8029134"},{"issue":"2","key":"1161_CR16","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1145\/3154839","volume":"14","author":"Y Li","year":"2018","unstructured":"Li, Y., Liu, Z., Xu, K., Yu, H., Ren, F.: A GPU-outperforming FPGA accelerator architecture for binary convolutional neural networks. ACM J. Emerg. Technol. Comput. Syst. 14(2), 18 (2018)","journal-title":"ACM J. Emerg. Technol. Comput. Syst."},{"key":"1161_CR17","doi-asserted-by":"publisher","first-page":"1072","DOI":"10.1016\/j.neucom.2017.09.046","volume":"275","author":"S Liang","year":"2018","unstructured":"Liang, S., Yin, S., Liu, L., Luk, W., Wei, S.: FP-BNN: Binarized neural network on FPGA. Neurocomputing 275, 1072\u20131086 (2018)","journal-title":"Neurocomputing"},{"issue":"2","key":"1161_CR18","doi-asserted-by":"publisher","first-page":"574","DOI":"10.1109\/TNNLS.2019.2906563","volume":"31","author":"S Lin","year":"2020","unstructured":"Lin, S., Ji, R., Li, Y., Deng, C., Li, X.: Toward compact ConvNets via structure-sparsity regularized filter pruning. IEEE Trans. Neural Networks Learn. Syst. 31(2), 574\u2013588 (2020)","journal-title":"IEEE Trans. Neural Networks Learn. Syst."},{"key":"1161_CR19","unstructured":"Lin, X., Zhao, C., Pan, W.: Towards accurate binary convolutional neural network. Adv. Neural Inf. Process. Syst. (NeurIPS) 345\u2013353 (2017)"},{"issue":"1","key":"1161_CR20","doi-asserted-by":"publisher","first-page":"65","DOI":"10.3390\/electronics8010065","volume":"8","author":"Z Liu","year":"2019","unstructured":"Liu, Z., Chow, P., Xu, J., Jiang, J., Dou, Y., Zhou, J.: A uniform architecture design for accelerating 2D and 3D CNNs on FPGAs. Electronics 8(1), 65 (2019)","journal-title":"Electronics"},{"key":"1161_CR21","first-page":"143","volume":"14","author":"Z Liu","year":"2020","unstructured":"Liu, Z., Shen, Z., Savvides, M., Cheng, K.: ReActNet: towards precise binary neural network with generalized activation functions. Comput. Vis. Eur. Conf. (ECCV) 14, 143\u2013159 (2020)","journal-title":"Comput. Vis. Eur. Conf. (ECCV)"},{"issue":"7","key":"1161_CR22","doi-asserted-by":"publisher","first-page":"1354","DOI":"10.1109\/TVLSI.2018.2815603","volume":"26","author":"Y Ma","year":"2018","unstructured":"Ma, Y., Cao, Y., Vrudhula, S., Seo, J.: Optimizing the convolution operation to accelerate deep neural networks on FPGA. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(7), 1354\u20131367 (2018)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"2","key":"1161_CR23","doi-asserted-by":"publisher","first-page":"333","DOI":"10.1007\/s11554-021-01083-1","volume":"18","author":"B Meng","year":"2021","unstructured":"Meng, B., Wang, L., He, Z., Jeon, G., Dou, Q., Yang, X.: Gradient information distillation network for real-time single-image super-resolution. J. Real-Time Image Process. 18(2), 333\u2013344 (2021)","journal-title":"J. Real-Time Image Process."},{"key":"1161_CR24","doi-asserted-by":"crossref","unstructured":"Rastegari, M., Ordonez, V., Redmon, J., Farhadi, A.: XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks. In: European Conference on Computer Vision (ECCV), pp. 525\u2013542 (2016)","DOI":"10.1007\/978-3-319-46493-0_32"},{"key":"1161_CR25","doi-asserted-by":"crossref","unstructured":"Sandler, M., Howard, A.G., Zhu, M., Zhmoginov, A., Chen, L.: MobileNetV2: Inverted Residuals and Linear Bottlenecks. In: IEEE Conference on Computer Vision and Pattern Recognition, (CVPR), pp. 4510\u20134520 (2018)","DOI":"10.1109\/CVPR.2018.00474"},{"key":"1161_CR26","doi-asserted-by":"crossref","unstructured":"Shen, J., Huang, Y., Wang, Z., Qiao, Y., Wen, M., Zhang, C.: Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. In: ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 97\u2013106 (2018)","DOI":"10.1145\/3174243.3174257"},{"key":"1161_CR27","unstructured":"Simonyan, K., Zisserman, A.: Very Deep Convolutional Networks for Large-Scale Image Recognition. In: International Conference on Learning Representations (ICLR) (2015)"},{"key":"1161_CR28","doi-asserted-by":"crossref","unstructured":"Tran, D., Bourdev, L., Fergus, R., Torresani, L., Paluri, M.: Learning Spatiotemporal Features with 3D Convolutional Networks. In: IEEE International Conference on Computer Vision (ICCV), pp. 4489\u20134497 (2015)","DOI":"10.1109\/ICCV.2015.510"},{"issue":"8","key":"1161_CR29","doi-asserted-by":"publisher","first-page":"2220","DOI":"10.1109\/TVLSI.2017.2688340","volume":"25","author":"F Tu","year":"2017","unstructured":"Tu, F., Yin, S., Ouyang, P., Tang, S., Liu, L., Wei, S.: Deep convolutional neural network architecture with reconfigurable computation patterns. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(8), 2220\u20132233 (2017)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"1161_CR30","doi-asserted-by":"crossref","unstructured":"Umuroglu, Y., Fraser, N.J., Gambardella, G., Blott, M., Leong, P., Jahre, M., Vissers, K.: FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. In: ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 65\u201374. ACM (2017)","DOI":"10.1145\/3020078.3021744"},{"key":"1161_CR31","doi-asserted-by":"publisher","first-page":"6909","DOI":"10.1109\/ACCESS.2017.2699229","volume":"5","author":"H Wang","year":"2017","unstructured":"Wang, H., Shao, M., Liu, Y., Zhao, W.: Enhanced efficiency 3D convolution based on optimal FPGA accelerator. IEEE Access 5, 6909\u20136916 (2017)","journal-title":"IEEE Access"},{"issue":"3","key":"1161_CR32","first-page":"1","volume":"18","author":"K Xu","year":"2020","unstructured":"Xu, K., Wang, X., Liu, X., Cao, C., Li, H., Peng, H., Wang, D.: A dedicated hardware accelerator for real-time acceleration of YOLOv2. J. Real-Time Image Process. 18(3), 1\u201312 (2020)","journal-title":"J. Real-Time Image Process."},{"key":"1161_CR33","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1016\/j.patcog.2018.07.028","volume":"85","author":"H Yang","year":"2019","unstructured":"Yang, H., Yuan, C., Li, B., Du, Y., Xing, J., Hu, W., Maybank, S.J.: Asymmetric 3D convolutional neural networks for action recognition. Pattern Recognit. 85, 1\u201312 (2019)","journal-title":"Pattern Recognit."},{"key":"1161_CR34","doi-asserted-by":"crossref","unstructured":"Yang, L., He, Z., Fan, D.: A Fully Onchip Binarized Convolutional Neural Network FPGA Impelmentation with Accurate Inference. In: International Symposium on Low Power Electronics and Design (ISLPED), p. 50. ACM (2018)","DOI":"10.1145\/3218603.3218615"},{"key":"1161_CR35","doi-asserted-by":"publisher","first-page":"37","DOI":"10.1016\/j.neucom.2018.09.038","volume":"323","author":"Q Zhang","year":"2019","unstructured":"Zhang, Q., Zhang, M., Chen, T., Sun, Z., Ma, Y., Yu, B.: Recent advances in convolutional neural network acceleration. Neurocomputing 323, 37\u201351 (2019)","journal-title":"Neurocomputing"},{"key":"1161_CR36","doi-asserted-by":"crossref","unstructured":"Zhao, R., Song, W., Zhang, W., Xing, T., Lin, J.H., Srivastava, M., Zhang, R.G.Z.: Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs. In: ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 15\u201324 (2017)","DOI":"10.1145\/3020078.3021741"},{"key":"1161_CR37","unstructured":"Zhuang, B., Shen, C., Reid, I.: Training Compact Neural Networks with Binary Weights and Low Precision Activations. arXiv preprint arXiv:1808.02631 (2018)"}],"container-title":["Journal of Real-Time Image Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11554-021-01161-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11554-021-01161-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11554-021-01161-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,2,1]],"date-time":"2022-02-01T07:15:54Z","timestamp":1643699754000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11554-021-01161-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,8,11]]},"references-count":37,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2022,2]]}},"alternative-id":["1161"],"URL":"https:\/\/doi.org\/10.1007\/s11554-021-01161-4","relation":{},"ISSN":["1861-8200","1861-8219"],"issn-type":[{"value":"1861-8200","type":"print"},{"value":"1861-8219","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,8,11]]},"assertion":[{"value":"23 April 2021","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"31 July 2021","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 August 2021","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}