{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T11:53:27Z","timestamp":1648641207788},"reference-count":16,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T00:00:00Z","timestamp":1338508800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int. J. Autom. Comput."],"published-print":{"date-parts":[[2012,6]]},"DOI":"10.1007\/s11633-012-0645-1","type":"journal-article","created":{"date-parts":[[2012,7,6]],"date-time":"2012-07-06T02:10:05Z","timestamp":1341540605000},"page":"280-287","source":"Crossref","is-referenced-by-count":6,"title":["A partitioning methodology that optimizes the communication cost for reconfigurable computing systems"],"prefix":"10.1007","volume":"9","author":[{"given":"Ramzi","family":"Ayadi","sequence":"first","affiliation":[]},{"given":"Bouraoui","family":"Ouni","sequence":"additional","affiliation":[]},{"given":"Abdellatif","family":"Mtibaa","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2012,7,7]]},"reference":[{"key":"645_CR1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4020-6100-4","volume-title":"Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications","author":"C. Bobda","year":"2007","unstructured":"C. Bobda. Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications, Germany: Springer Publishers, 2007."},{"issue":"10","key":"645_CR2","doi-asserted-by":"crossref","first-page":"1362","DOI":"10.1109\/TC.2003.1234532","volume":"52","author":"J. M. P. Cardoso","year":"2003","unstructured":"J. M. P. Cardoso. On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures. IEEE Transactions on Computers, vol. 52, no. 10, pp. 1362\u20131375, 2003.","journal-title":"IEEE Transactions on Computers"},{"issue":"3","key":"645_CR3","doi-asserted-by":"crossref","first-page":"115","DOI":"10.1016\/S0141-9331(02)00102-3","volume":"27","author":"C. Tanougast","year":"2003","unstructured":"C. Tanougast, Y. Berviller, P. Brunet, S. Weber, H. Rabah. Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system. Microprocessors and Microsystems, vol. 27, no. 3, pp. 115\u2013130, 2003.","journal-title":"Microprocessors and Microsystems"},{"issue":"2","key":"645_CR4","doi-asserted-by":"crossref","first-page":"174","DOI":"10.1007\/s11633-008-0174-0","volume":"5","author":"A. D. Cabrol","year":"2008","unstructured":"A. D. Cabrol, T. Garcia, P. Bonnin, M. Chetto. A concept of dynamically reconfigurable real-time vision system for autonomous mobile robotics. International Journal of Automation and Computing, vol. 5, no. 2, pp. 174\u2013184, 2008.","journal-title":"International Journal of Automation and Computing"},{"issue":"1","key":"645_CR5","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1007\/s11633-005-0025-1","volume":"2","author":"W. Y. Wu","year":"2005","unstructured":"W. Y. Wu, Z. X. Zhao. Realization of reconfigurable virtual environments for virtual testing. International Journal of Automation and Computing, vol. 2, no. 1, pp. 25\u201336, 2005.","journal-title":"International Journal of Automation and Computing"},{"issue":"10","key":"645_CR6","first-page":"766","volume":"3","author":"B. Ouni","year":"2008","unstructured":"B. Ouni, R. Ayadi, M. Abid. Novel temporal partitioning algorithm for run time reconfigured systems. Journal of Engineering and Applied Sciences, vol. 3, no. 10, pp. 766\u2013773, 2008.","journal-title":"Journal of Engineering and Applied Sciences"},{"issue":"4","key":"645_CR7","first-page":"335","volume":"3","author":"B. Ouni","year":"2009","unstructured":"B. Ouni, A. Mtibaa, E. B. Bourennane. Scheduling approach for run time reconfigured systems. International Journal of Computer Sciences and Engineering Systems, vol. 3, no. 4, pp. 335\u2013340, 2009.","journal-title":"International Journal of Computer Sciences and Engineering Systems"},{"key":"645_CR8","doi-asserted-by":"crossref","first-page":"153","DOI":"10.1145\/275107.275135","volume-title":"Proceedings of the 1998 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","author":"S. Trimberger","year":"1998","unstructured":"S. Trimberger. Scheduling designs into a time-multiplexed FPGA. In Proceedings of the 1998 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, ACM, Monterey, USA, pp. 153\u2013160, 1998."},{"key":"645_CR9","first-page":"400","volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-aided Design","author":"H. Q. Liu","year":"1999","unstructured":"H. Q. Liu, D. F. Wong. A graph theoretic algorithm for schedule compression in time-multiplexed FPGA partitioning. In Proceedings of IEEE\/ACM International Conference on Computer-aided Design, IEEE, San Jose, USA, pp. 400\u2013405, 1999."},{"key":"645_CR10","doi-asserted-by":"crossref","unstructured":"H. Q. Liu, D. F. Wong. Network flow based circuit partitioning for time-multiplexed FPGAs. In Proceedings of IEEE\/ACM International Conference on Computer-aided Design, IEEE, pp. 497\u2013504, 1998.","DOI":"10.1145\/288548.289077"},{"issue":"1","key":"645_CR11","doi-asserted-by":"crossref","first-page":"50","DOI":"10.1109\/43.673632","volume":"17","author":"H. Q. Liu","year":"1998","unstructured":"H. Q. Liu, D. F. Wong. Network flow based multi-way partitioning with area and pin constraints. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 17, no. 1, pp. 50\u201359, 1998.","journal-title":"IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems"},{"issue":"7","key":"645_CR12","doi-asserted-by":"crossref","first-page":"952","DOI":"10.1109\/TCAD.2003.814237","volume":"22","author":"W. K. Mak","year":"2003","unstructured":"W. K. Mak, E. F. Y. Young. Temporal logic replication for dynamically reconfigurable FPGA partitioning. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 22, no. 7, pp. 952\u2013959, 2003.","journal-title":"IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems"},{"issue":"12","key":"645_CR13","doi-asserted-by":"crossref","first-page":"1351","DOI":"10.1109\/TVLSI.2007.909806","volume":"15","author":"Y. C. Jiang","year":"2007","unstructured":"Y. C. Jiang, J. F. Wang. Temporal partitioning data flow graphs for dynamically reconfigurable computing. IEEE Transactions on Very Large Scale Integration Systems, vol. 15, no. 12, pp. 1351\u20131361, 2007.","journal-title":"IEEE Transactions on Very Large Scale Integration Systems"},{"issue":"8","key":"645_CR14","doi-asserted-by":"crossref","first-page":"888","DOI":"10.1109\/34.868688","volume":"22","author":"J. Shi","year":"2000","unstructured":"J. Shi, J. Malik. Normalized cuts and image Segmentation. IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 22, no. 8, pp. 888\u2013905, 2000.","journal-title":"IEEE Transactions on Pattern Analysis and Machine Intelligence"},{"key":"645_CR15","doi-asserted-by":"crossref","first-page":"751","DOI":"10.1109\/FOCS.2008.78","volume-title":"Proceedings of the 49th IEEE Symposium on Foundations of Computer Science","author":"P. Biswal","year":"2008","unstructured":"P. Biswal, J. R. Lee, S. Rao. Eigenvalue bounds spectral partitioning and metrical deformations via flows. In Proceedings of the 49th IEEE Symposium on Foundations of Computer Science, IEEE, Philadelphia, USA, pp. 751\u2013760, 2008."},{"issue":"2","key":"645_CR16","doi-asserted-by":"crossref","first-page":"181","DOI":"10.1023\/A:1008193422345","volume":"24","author":"M. Kaul","year":"2000","unstructured":"M. Kaul, R. Vemuri. Design-space exploration for block-processing based temporal partitioning of run-time reconfigurable systems. Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, vol. 24, no. 2, pp. 181\u2013209, 2000.","journal-title":"Journal of VLSI Signal Processing Systems for Signal Image and Video Technology"}],"container-title":["International Journal of Automation and Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11633-012-0645-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11633-012-0645-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11633-012-0645-1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,30]],"date-time":"2019-06-30T12:01:35Z","timestamp":1561896095000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11633-012-0645-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6]]},"references-count":16,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2012,6]]}},"alternative-id":["645"],"URL":"https:\/\/doi.org\/10.1007\/s11633-012-0645-1","relation":{},"ISSN":["1476-8186","1751-8520"],"issn-type":[{"value":"1476-8186","type":"print"},{"value":"1751-8520","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,6]]}}}