{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T21:11:15Z","timestamp":1771535475853,"version":"3.50.1"},"reference-count":23,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2024,11,11]],"date-time":"2024-11-11T00:00:00Z","timestamp":1731283200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,11,11]],"date-time":"2024-11-11T00:00:00Z","timestamp":1731283200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Front. Comput. Sci."],"published-print":{"date-parts":[[2025,1]]},"DOI":"10.1007\/s11704-023-3239-x","type":"journal-article","created":{"date-parts":[[2024,11,11]],"date-time":"2024-11-11T05:00:10Z","timestamp":1731301210000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["RVAM16: a low-cost multiple-ISA processor based on RISC-V and ARM Thumb"],"prefix":"10.1007","volume":"19","author":[{"given":"Libo","family":"Huang","sequence":"first","affiliation":[]},{"given":"Jing","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Ling","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Sheng","family":"Ma","sequence":"additional","affiliation":[]},{"given":"Yongwen","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Yuanhu","family":"Cheng","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,11,11]]},"reference":[{"issue":"1","key":"3239_CR1","doi-asserted-by":"publisher","first-page":"7","DOI":"10.1109\/TCAD.2017.2717782","volume":"37","author":"T Adegbija","year":"2018","unstructured":"Adegbija T, Rogacs A, Patel C, Gordon-Ross A. Microprocessor optimizations for the internet of things: a survey. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(1): 7\u201320","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"3239_CR2","first-page":"1","volume-title":"Proceedings of the 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","author":"K Saso","year":"2018","unstructured":"Saso K, Hara-Azumi Y. Simple instruction-set computer for area and energy-sensitive IoT edge devices. In: Proceedings of the 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP). 2018, 1\u20134"},{"issue":"2","key":"3239_CR3","doi-asserted-by":"publisher","first-page":"45","DOI":"10.1109\/LES.2019.2949620","volume":"12","author":"K Saso","year":"2020","unstructured":"Saso K, Hara-Azumi Y. Revisiting simple and energy efficient embedded processor designs toward the edge computing. IEEE Embedded Systems Letters, 2020, 12(2): 45\u201349","journal-title":"IEEE Embedded Systems Letters"},{"issue":"2","key":"3239_CR4","doi-asserted-by":"publisher","first-page":"69","DOI":"10.1145\/151220.151227","volume":"36","author":"R L Sites","year":"1993","unstructured":"Sites R L, Chernoff A, Kirk M B, Marks M P, Robinson S G. Binary translation. Communications of the ACM, 1993, 36(2): 69\u201381","journal-title":"Communications of the ACM"},{"key":"3239_CR5","volume-title":"About the Rosetta translation environment","author":"Apple Inc.","year":"2023","unstructured":"Apple Inc. About the Rosetta translation environment. See developer.apple.com\/documentation\/apple-silicon\/about-the-rosetta-translation-environment website, Accessed: 2023"},{"key":"3239_CR6","first-page":"41","volume-title":"Proceedings of the USENIX Annual Technical Conference","author":"F Bellard","year":"2005","unstructured":"Bellard F. QEMU, a fast and portable dynamic translator. In: Proceedings of the USENIX Annual Technical Conference. 2005, 41\u201346"},{"key":"3239_CR7","first-page":"104","volume-title":"Proceedings of the 10th International Symposium on Code Generation and Optimization","author":"D Y Hong","year":"2012","unstructured":"Hong D Y, Hsu C C, Yew P C, Wu J J, Hsu W C, Liu P, Wang C M, Chung Y C. HQEMU: a multi-threaded and retargetable dynamic binary translator on multicores. In: Proceedings of the 10th International Symposium on Code Generation and Optimization. 2012, 104\u2013113"},{"key":"3239_CR8","volume-title":"Proceedings of the 3rd RISC-V Workshop","author":"B Ilbeyi","year":"2016","unstructured":"Ilbeyi B, Lockhart D, Batten C. Pydgin for RISC-V: a fast and productive instruction-set simulator. In: Proceedings of the 3rd RISC-V Workshop. 2016"},{"key":"3239_CR9","volume-title":"Proceedings of the 1st Workshop on Computer Architecture Research with RISC-V (CARRV)","author":"M Clark","year":"2017","unstructured":"Clark M, Hoult B. rv8: a high performance RISC-V to x86 binary translator. In: Proceedings of the 1st Workshop on Computer Architecture Research with RISC-V (CARRV). 2017"},{"key":"3239_CR10","first-page":"369","volume-title":"Proceedings of the 14th International Conference on Computer Systems and Applications (AICCSA)","author":"C Sabri","year":"2017","unstructured":"Sabri C, Kriaa L, Azzouz S L. Comparison of IoT constrained devices operating systems: a survey. In: Proceedings of the 14th International Conference on Computer Systems and Applications (AICCSA). 2017, 369\u2013375"},{"key":"3239_CR11","doi-asserted-by":"publisher","first-page":"51","DOI":"10.1145\/2380403.2380419","volume-title":"Proceedings of 2012 International Conference on Compilers, Architectures and Synthesis for Embedded Systems","author":"B Y Shen","year":"2012","unstructured":"Shen B Y, Chen J Y, Hsu W C, Yang W. LLBT: an LLVM-based static binary translator. In: Proceedings of 2012 International Conference on Compilers, Architectures and Synthesis for Embedded Systems. 2012, 51\u201360"},{"key":"3239_CR12","doi-asserted-by":"publisher","first-page":"213","DOI":"10.1109\/WSCAD.2018.00041","volume-title":"Proceedings of 2018 Symposium on High Performance Computing Systems (WSCAD)","author":"L Lupori","year":"2018","unstructured":"Lupori L, Rosario V, Borin E. Towards a high-performance RISC-V emulator. In: Proceedings of 2018 Symposium on High Performance Computing Systems (WSCAD). 2018, 213\u2013220"},{"key":"3239_CR13","first-page":"121","volume-title":"Proceedings of the 41st International Symposium on Computer Architecture (ISCA)","author":"A Venkat","year":"2014","unstructured":"Venkat A, Tullsen D M. Harnessing ISA diversity: design of a heterogeneous-ISA chip multiprocessor. In: Proceedings of the 41st International Symposium on Computer Architecture (ISCA). 2014, 121\u2013132"},{"key":"3239_CR14","doi-asserted-by":"publisher","first-page":"42","DOI":"10.1109\/HPCA.2019.00026","volume-title":"Proceedings of 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)","author":"A Venkat","year":"2019","unstructured":"Venkat A, Basavaraj H, Tullsen D M. Composite-ISA cores: enabling multi-ISA heterogeneity using a single ISA. In: Proceedings of 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). 2019, 42\u201355"},{"key":"3239_CR15","first-page":"699","volume-title":"Proceedings of the 25th International Conference on Architectural Support for Programming Languages and Operating Systems","author":"J Balkind","year":"2020","unstructured":"Balkind J, Lim K, Schaffner M, Gao F, Chirkov G, Li A, Lavrov A, Nguyen T M, Fu Y, Zaruba F, Gulati K, Benini L, Wentzlaff D. BYOC: a \u201cbring your own core\u201d framework for heterogeneous-ISA research. In: Proceedings of the 25th International Conference on Architectural Support for Programming Languages and Operating Systems. 2020, 699\u2013714"},{"issue":"10","key":"3239_CR16","doi-asserted-by":"publisher","first-page":"1872","DOI":"10.1109\/TCAD.2018.2864288","volume":"38","author":"S Rokicki","year":"2019","unstructured":"Rokicki S, Rohou E, Derrien S. Hybrid-DBT: hardware\/software dynamic binary translation targeting VLIW. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, 38(10): 1872\u20131885","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"4","key":"3239_CR17","doi-asserted-by":"publisher","first-page":"329","DOI":"10.1007\/s10617-015-9159-8","volume":"19","author":"F M Capella","year":"2015","unstructured":"Capella F M, Brandalero M, Carro L, Beck A C S. A multiple-ISA reconfigurable architecture. Design Automation for Embedded Systems, 2015, 19(4): 329\u2013344","journal-title":"Design Automation for Embedded Systems"},{"issue":"2","key":"3239_CR18","doi-asserted-by":"publisher","first-page":"103","DOI":"10.1016\/j.sysarc.2012.10.001","volume":"59","author":"J Fajardo","year":"2013","unstructured":"Fajardo J, Rutzig M B, Carro L, Beck A C S. Towards a multiple-ISA embedded system. Journal of Systems Architecture, 2013, 59(2): 103\u2013119","journal-title":"Journal of Systems Architecture"},{"key":"3239_CR19","first-page":"365","volume-title":"Proceedings of IEEE National Aerospace and Electronics Conference","author":"K Chai","year":"2021","unstructured":"Chai K, Wolff F, Papachristou C. XBT: FPGA accelerated binary translation. In: Proceedings of IEEE National Aerospace and Electronics Conference. 2021, 365\u2013372"},{"key":"3239_CR20","first-page":"1062","volume-title":"Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"S Rokicki","year":"2017","unstructured":"Rokicki S, Rohou E, Derrien S. Hardware-accelerated dynamic binary translation. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE). 2017, 1062\u20131067"},{"key":"3239_CR21","volume-title":"The RISC-V instruction set manual: volume I: unprivileged ISA","author":"A Waterman","year":"2019","unstructured":"Waterman A, Asanovic K. The RISC-V instruction set manual: volume I: unprivileged ISA. 2019"},{"key":"3239_CR22","volume-title":"ARM\u00ae Cortex\u00ae-M0 DesignStart\u2122 RTL Testbench: user guide","author":"ARM","year":"2015","unstructured":"ARM. ARM\u00ae Cortex\u00ae-M0 DesignStart\u2122 RTL Testbench: user guide. 2015"},{"key":"3239_CR23","first-page":"88","volume-title":"Proceedings of the 15th International Conference on Advanced Computer Theory and Engineering (ICACTE)","author":"W Wang","year":"2022","unstructured":"Wang W, Liu X, Yu J, Li J, Mao Z, Li Z, Ding C, Zhang C. The design and building of openKylin on RISC-V architecture. In: Proceedings of the 15th International Conference on Advanced Computer Theory and Engineering (ICACTE). 2022, 88\u201391"}],"container-title":["Frontiers of Computer Science"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11704-023-3239-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11704-023-3239-x","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11704-023-3239-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T20:27:53Z","timestamp":1771532873000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11704-023-3239-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,11,11]]},"references-count":23,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2025,1]]}},"alternative-id":["3239"],"URL":"https:\/\/doi.org\/10.1007\/s11704-023-3239-x","relation":{},"ISSN":["2095-2228","2095-2236"],"issn-type":[{"value":"2095-2228","type":"print"},{"value":"2095-2236","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,11,11]]},"assertion":[{"value":"23 March 2023","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"30 October 2023","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 November 2024","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"Competing interests\n                      The authors declare that they have no competing interests or financial conflicts to disclose.","order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethics"}}],"article-number":"191103"}}