{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,9]],"date-time":"2026-01-09T02:37:14Z","timestamp":1767926234058,"version":"3.49.0"},"reference-count":43,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2022,2,14]],"date-time":"2022-02-14T00:00:00Z","timestamp":1644796800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2022,2,14]],"date-time":"2022-02-14T00:00:00Z","timestamp":1644796800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100006115","name":"Institute for Research in Fundamental Sciences","doi-asserted-by":"publisher","award":["CS1400-2-03"],"award-info":[{"award-number":["CS1400-2-03"]}],"id":[{"id":"10.13039\/501100006115","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["SIViP"],"published-print":{"date-parts":[[2022,9]]},"DOI":"10.1007\/s11760-021-02097-9","type":"journal-article","created":{"date-parts":[[2022,2,14]],"date-time":"2022-02-14T19:02:57Z","timestamp":1644865377000},"page":"1443-1454","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set"],"prefix":"10.1007","volume":"16","author":[{"given":"Armin","family":"Belghadr","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ghassem","family":"Jaberipur","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2022,2,14]]},"reference":[{"key":"2097_CR1","volume-title":"Digital signal processing: fundamentals and applications","author":"L Tan","year":"2013","unstructured":"Tan, L., Jiang, J.: Digital signal processing: fundamentals and applications, 2nd edn. Academic Press, Cambridge (2013)","edition":"2"},{"key":"2097_CR2","unstructured":"Chueng, L., Womack, G., and Yuen, J.: Camera system for surgical applications. U.S. Patent No. 9,866,742, Issued January 9, (2018)"},{"key":"2097_CR3","unstructured":"Wilson, K.: Vehicle and vehicle tire monitoring system, apparatus and method. U.S. Patent No. 10\/143,312, Issued March 27, (2003)"},{"key":"2097_CR4","doi-asserted-by":"publisher","first-page":"181","DOI":"10.1007\/978-3-319-49742-6_8","volume-title":"Embedded Systems Design with Special Arithmetic and Number Systems","author":"GC Cardarilli","year":"2017","unstructured":"Cardarilli, G.C., Nannarelli, A., Re, M.: RNS applications in digital signal processing. In: Embedded Systems Design with Special Arithmetic and Number Systems, pp. 181\u2013215. Springer International Publishing, Berlin (2017)"},{"key":"2097_CR5","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1007\/978-1-4471-4950-7_2","volume-title":"Introduction to Image Processing Using R","author":"AC Frery","year":"2013","unstructured":"Frery, A.C., Perciano, T.: Image data formats and color representation. In: Introduction to Image Processing Using R, pp. 21\u201329. SpringerBriefs in Computer Science Springer, London (2013)"},{"issue":"1","key":"2097_CR6","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1109\/TCSII.2003.821524","volume":"51","author":"R Conway","year":"2004","unstructured":"Conway, R., Nelson, J.: Improved RNS FIR filter architectures. IEEE Trans. Circuits Syst. II: Express Briefs 51(1), 26\u201328 (2004)","journal-title":"IEEE Trans. Circuits Syst. II: Express Briefs"},{"issue":"4","key":"2097_CR7","doi-asserted-by":"publisher","first-page":"191","DOI":"10.1109\/TCS.1977.1084321","volume":"24","author":"W Jenkins","year":"1977","unstructured":"Jenkins, W., Leon, B.: The use of residue number systems in the design of finite impulse response digital filters. IEEE Trans. Circuits Syst. 24(4), 191\u2013201 (1977)","journal-title":"IEEE Trans. Circuits Syst."},{"issue":"1","key":"2097_CR8","doi-asserted-by":"publisher","first-page":"55","DOI":"10.1109\/89.736331","volume":"7","author":"DS Kim","year":"1999","unstructured":"Kim, D.S., Lee, S.Y., Kil, R.M.: Auditory processing of speech signals for robust speech recognition in real-world noisy environments. IEEE Trans. Speech Audio Process. 7(1), 55\u201369 (1999)","journal-title":"IEEE Trans. Speech Audio Process."},{"issue":"4","key":"2097_CR9","doi-asserted-by":"publisher","first-page":"354","DOI":"10.1109\/TAU.1973.1162497","volume":"21","author":"D Chan","year":"1973","unstructured":"Chan, D., Rabiner, L.: Analysis of quantization errors in the direct form for finite impulse response digital filters. IEEE Trans. Audio Electroacoust. 21(4), 354\u2013366 (1973)","journal-title":"IEEE Trans. Audio Electroacoust."},{"key":"2097_CR10","doi-asserted-by":"crossref","unstructured":"Garcia, A., Meyer-Base, U., Lloris, A., and Taylor, F. J.: RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic. In Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, vol. 1, pp. 486\u2013489 (1999)","DOI":"10.1109\/ISCAS.1999.777933"},{"key":"2097_CR11","unstructured":"Yates, R.: Practical considerations in fixed-point FIR filter implementations. Digital Signal Labs, Technical Reference, (2010)"},{"key":"2097_CR12","doi-asserted-by":"publisher","first-page":"425","DOI":"10.1016\/j.neucom.2018.10.029","volume":"330","author":"G Sanchez","year":"2019","unstructured":"Sanchez, G., Diaz, C., Avalos, J.G., Garcia, L., Vazquez, A., Toscano, K., Sanchez, J.C., Perez, H.: A highly scalable parallel spike-based digital neuromorphic architecture for high-order fir filters using LMS adaptive algorithm. Neurocomputing 330, 425\u2013436 (2019)","journal-title":"Neurocomputing"},{"key":"2097_CR13","doi-asserted-by":"crossref","unstructured":"Srinivasa Reddy, K., and Sahoo, S. K.: An approach for fixed coefficient RNS-based FIR filter. International Journal of Electronics, pp. 1\u201319 (2017)","DOI":"10.1080\/00207217.2017.1296593"},{"key":"2097_CR14","doi-asserted-by":"crossref","unstructured":"Bernocchi, G. L., Cardarilli, G. C., Del Re, A., Nannarelli, A., and Re, M.: Low-power adaptive filter based on RNS components. In IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3211\u20133214 (2007)","DOI":"10.1109\/ISCAS.2007.378155"},{"issue":"3","key":"2097_CR15","doi-asserted-by":"publisher","first-page":"201","DOI":"10.1007\/s11265-010-0537-y","volume":"63","author":"S Pontarelli","year":"2012","unstructured":"Pontarelli, S., Cardarilli, G.C., Re, M., Salsano, A.: Optimized implementation of RNS FIR filters based on FPGAs. J. Signal Process. Syst. 63(3), 201\u2013212 (2012)","journal-title":"J. Signal Process. Syst."},{"key":"2097_CR16","doi-asserted-by":"crossref","unstructured":"Petricca, M., Albicocco, P., Cardarilli, G. C., Nannarelli, A., and Re, M.: Power efficient design of parallel\/serial FIR filters in RNS. In Forty Sixth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), Pacific Grove, CA, pp. 1015\u20131019 (2012)","DOI":"10.1109\/ACSSC.2012.6489171"},{"key":"2097_CR17","doi-asserted-by":"crossref","unstructured":"Belghadr, A., and Jaberipur, G. L. (2018) FIR filter realization via deferred end-around carry modular addition. Ieee Transactions on Circuits and Systems\u2013I: Regular Papers, 65(9), 2878\u20132888","DOI":"10.1109\/TCSI.2018.2798595"},{"key":"2097_CR18","doi-asserted-by":"publisher","first-page":"278","DOI":"10.37394\/23203.2021.16.24","volume":"16","author":"CS Murthy","year":"2021","unstructured":"Murthy, C.S., Sridevi, K.: FPGA implementation of high speed-low energy RNS based reconfigurable-FIR filter for cognitive radio applications. WSEAS Trans. Syst. Control 16, 278\u2013293 (2021)","journal-title":"WSEAS Trans. Syst. Control"},{"key":"2097_CR19","doi-asserted-by":"publisher","first-page":"745","DOI":"10.1007\/978-981-16-1056-1_58","volume":"1317","author":"S Samyuktha","year":"2021","unstructured":"Samyuktha, S., Duggineni, C., Swetha, N., Valiveti, H.B.: An optimized area efficient implementation of fir filter using shift add multiplier with carry look ahead adder. Springer Cogn Informatics Soft Comput 1317, 745\u2013754 (2021)","journal-title":"Springer Cogn Informatics Soft Comput"},{"key":"2097_CR20","doi-asserted-by":"publisher","first-page":"259","DOI":"10.1007\/s10772-020-09683-1","volume":"23","author":"GN Jyothi","year":"2020","unstructured":"Jyothi, G.N., Sanapala, K., Vijayalakshmi, A.: ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems. Int. J. Speech Technol. 23, 259\u2013264 (2020)","journal-title":"Int. J. Speech Technol."},{"key":"2097_CR21","unstructured":"Carlo Cardarilli, G., Di Nunzio, L., Fazzolari, R., Nannarelli, A., Petricca. M., and Re, M.: Design space exploration based methodology for residue number system digital filters implementation. IEEE Transactions on Emerging Topics in Computing, (2020)"},{"key":"2097_CR22","doi-asserted-by":"crossref","first-page":"686","DOI":"10.1109\/DATE.2004.1268931","volume":"1","author":"A Del Re","year":"2004","unstructured":"Del Re, A., Nannarelli, A., Re, M.: A tool for automatic generation of RTL-level VHDL description of RNS FIR filters. Eur Conf. Exhibition Design, Autom. Test 1, 686\u2013687 (2004)","journal-title":"Eur Conf. Exhibition Design, Autom. Test"},{"key":"2097_CR23","unstructured":"Nannarelli, A., and Re, M.: Residue number systems: a Survey. D T U Compute., Kongens Lyngby, Kgs. Lyngby, Tech. Rep. 2008\u201304 (2008)"},{"key":"2097_CR24","doi-asserted-by":"crossref","unstructured":"Cardarilli, G. C., Del Re, A., Nannarelli, A., and Re, M.: Impact of RNS coding overhead on FIR filters performance. In Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, pp. 1426\u20131429 (2007)","DOI":"10.1109\/ACSSC.2007.4487464"},{"issue":"2","key":"2097_CR25","doi-asserted-by":"publisher","first-page":"123","DOI":"10.1007\/s10617-005-1186-4","volume":"9","author":"Y Liu","year":"2004","unstructured":"Liu, Y., Lai, E.M.K.: Moduli set selection and cost estimation for RNS-based FIR filter and filter bank design. Design Autom. Embed. Syst. 9(2), 123\u2013139 (2004)","journal-title":"Design Autom. Embed. Syst."},{"key":"2097_CR26","doi-asserted-by":"publisher","first-page":"95","DOI":"10.1016\/j.compeleceng.2017.06.019","volume":"61","author":"G Jaberipur","year":"2017","unstructured":"Jaberipur, G., Belghadr, A.: (5+2logn)\u0394G diminished-1 modulo-(2n+1) unified adder\/subtractor with full zero handling. Comput. Electr. Eng. 61, 95\u2013103 (2017)","journal-title":"Comput. Electr. Eng."},{"key":"2097_CR27","doi-asserted-by":"crossref","unstructured":"Jaberipur, G., and Langroudi, S.H.F.: (4 + logn)\u0394G parallel prefix modulo-(2n\u22123) Adder via Double Representation of Residues in [0,2]. IEEE Transactions on Circuits and Systems\u2013II, 62(6), 583\u2013587 (2015)","DOI":"10.1109\/TCSII.2015.2407772"},{"key":"2097_CR28","doi-asserted-by":"crossref","unstructured":"Langroudi, S. H. F., and Jaberipur, G., Modulo-(2n\u22122q\u22121) parallel prefix addition via excess-modulo encoding of residues. In ARITH, Lyon, pp. 121\u2013128 (2015)","DOI":"10.1109\/ARITH.2015.9"},{"key":"2097_CR29","doi-asserted-by":"crossref","unstructured":"Ma, S., Hu, J. H., and Wang, C. H.: A novel modulo-(2n\u22122k\u22121) adder for residue number system. IEEE Transactions on Circuits and Systems\u2013I: Regular Papers, 60(11), 2962\u20132972 (2013)","DOI":"10.1109\/TCSI.2013.2252639"},{"key":"2097_CR30","first-page":"789","volume":"204","author":"A Hiasat","year":"2021","unstructured":"Hiasat, A.: A modulo (2n\u22122n-2\u22121) adder design. Springer Commun. Intell. Syst. 204, 789\u2013802 (2021)","journal-title":"Springer Commun. Intell. Syst."},{"issue":"5","key":"2097_CR31","doi-asserted-by":"publisher","first-page":"965","DOI":"10.1142\/S0218126605002726","volume":"14","author":"HT Vergos","year":"2005","unstructured":"Vergos, H.T., Efstathiou, C.: On the design of efficient modular adders. J. Circuits Syst. Comput. 14(5), 965\u2013972 (2005)","journal-title":"J. Circuits Syst. Comput."},{"issue":"1","key":"2097_CR32","doi-asserted-by":"publisher","first-page":"93","DOI":"10.1093\/comjnl\/47.1.93","volume":"47","author":"AA Hiasat","year":"2004","unstructured":"Hiasat, A.A.: A suggestion for a fast residue multiplier for a family of moduli of the form 2n\u20132p\u00b11. Comput. J. 47(1), 93\u2013102 (2004)","journal-title":"Comput. J."},{"issue":"3","key":"2097_CR33","doi-asserted-by":"publisher","first-page":"193","DOI":"10.1587\/elex.9.193","volume":"9","author":"L Li","year":"2012","unstructured":"Li, L., Hu, J., Chen, Y.: An universal architecture for designing modulo 2n\u20132k\u22121 multiplier. IEICE Electron. Expr. 9(3), 193\u2013199 (2012)","journal-title":"IEICE Electron. Expr."},{"issue":"2","key":"2097_CR34","doi-asserted-by":"publisher","first-page":"170","DOI":"10.1109\/12.833113","volume":"49","author":"AA Hiasat","year":"2000","unstructured":"Hiasat, A.A.: New efficient structure for a modular multiplier for RNS. IEEE Trans. Comput. 49(2), 170\u2013174 (2000)","journal-title":"IEEE Trans. Comput."},{"key":"2097_CR35","doi-asserted-by":"crossref","unstructured":"Hiasat, A.A.: RNS arithmetic multiplier for medium and large moduli. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 47(9), 937\u2013940 (2000)","DOI":"10.1109\/82.868463"},{"key":"2097_CR36","doi-asserted-by":"crossref","unstructured":"Paliouras, V., Karaginni, K., and T. Stouraitis, T.: A low-complexity combinatorial RNS multiplier. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process., 48(7), 675\u2013683 (2001)","DOI":"10.1109\/82.958337"},{"issue":"2","key":"2097_CR37","doi-asserted-by":"publisher","first-page":"354","DOI":"10.1109\/TCSI.2003.820243","volume":"51","author":"G Dimitrakopoulos","year":"2004","unstructured":"Dimitrakopoulos, G., Paliouras, V.: A novel architecture and a systematic graph-based optimization methodology for modulo multiplication. IEEE Trans. Circuits Syst. I Regul. Pap. 51(2), 354\u2013370 (2004)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"10","key":"2097_CR38","doi-asserted-by":"publisher","first-page":"2263","DOI":"10.1109\/TCSI.2012.2185334","volume":"59","author":"R Muralidharan","year":"2012","unstructured":"Muralidharan, R., Chang, C.H.: Area-power efficient modulo 2n\u20131 and modulo 2n+1 multipliers for {2n\u20131, 2n, 2n+ 1} based RNS. IEEE Trans. Circuits Syst. I Regul. Pap. 59(10), 2263\u20132274 (2012)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"2097_CR39","unstructured":"Ahmadifar, A., and Jaberipur, G.: Improved modulo-(2n+3) multipliers. In Proceeding of the 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS2013), Tehran, Iran pp. 31\u201335 (2013)"},{"key":"2097_CR40","doi-asserted-by":"crossref","unstructured":"Matutino, P. M., Chavez, R., and Sousa, L.: Arithmetic units for RNS moduli {2n\u22123} and {2n+3} operations. In 13th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools \u2013 DSD, pp. 243\u2013246 (2010)","DOI":"10.1109\/DSD.2010.77"},{"key":"2097_CR41","unstructured":"Liao, Y., Hameenanttila, T. M., and Roberts, D. B.: Processing multiply-accumulate operations in a single cycle. U.S. Patent 6, 611, 856, Issued August 26 (2003)"},{"key":"2097_CR42","doi-asserted-by":"crossref","unstructured":"Wang, Y., Song, X., and Aboulhamid, M.: Adder based residue to binary number converters for (2n\u22121, 2n, 2n+1). IEEE Transaction on Signal Processing, 50(7), (2002)","DOI":"10.1109\/TSP.2002.1011216"},{"key":"2097_CR43","doi-asserted-by":"publisher","DOI":"10.1142\/p523","volume-title":"Residue Number Systems: Theory and Implementations","author":"A Omondi","year":"2007","unstructured":"Omondi, A., Premkumar, B.: Residue Number Systems: Theory and Implementations. Imperial College Press, London (2007)"}],"container-title":["Signal, Image and Video Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11760-021-02097-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11760-021-02097-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11760-021-02097-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,18]],"date-time":"2024-09-18T14:44:22Z","timestamp":1726670662000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11760-021-02097-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,2,14]]},"references-count":43,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2022,9]]}},"alternative-id":["2097"],"URL":"https:\/\/doi.org\/10.1007\/s11760-021-02097-9","relation":{},"ISSN":["1863-1703","1863-1711"],"issn-type":[{"value":"1863-1703","type":"print"},{"value":"1863-1711","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,2,14]]},"assertion":[{"value":"1 January 2021","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"16 September 2021","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 November 2021","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 February 2022","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}