{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T04:05:01Z","timestamp":1750997101744,"version":"3.41.0"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T00:00:00Z","timestamp":1747785600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T00:00:00Z","timestamp":1747785600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Int J Syst Assur Eng Manag"],"published-print":{"date-parts":[[2025,6]]},"DOI":"10.1007\/s13198-025-02800-w","type":"journal-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T15:08:05Z","timestamp":1747840085000},"page":"2078-2088","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Advanced arithmetic circuits realization using next generation logic gates"],"prefix":"10.1007","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5049-2985","authenticated-orcid":false,"given":"Sreevani","family":"Menda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sivaji","family":"Satrasupalli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rajeev Ratna","family":"Vallabhuni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S. China","family":"Venkateswarlu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2025,5,21]]},"reference":[{"issue":"12","key":"2800_CR1","doi-asserted-by":"publisher","first-page":"7335","DOI":"10.1007\/s00034-023-02445-9","volume":"42","author":"SJ Basha","year":"2023","unstructured":"Basha SJ, Venkatramana P (2023) Design of ternary logic circuits using GNRFET and RRAM. Circuits Syst Signal Process 42(12):7335\u20137356","journal-title":"Circuits Syst Signal Process"},{"issue":"46","key":"2800_CR2","doi-asserted-by":"publisher","first-page":"2103365","DOI":"10.1002\/smll.202103365","volume":"17","author":"L Chungryeol","year":"2021","unstructured":"Chungryeol L et al (2021) Systematic control of negative transconductance in organic heterojunction transistor for high-performance, low-power flexible ternary logic circuits. Small 17(46):2103365","journal-title":"Small"},{"key":"2800_CR3","first-page":"605","volume-title":"Innovations in Cyber Physical Systems: Select Proceedings of ICICPS 2020","author":"MB Divya","year":"2021","unstructured":"Divya MB, Sunithamani S (2021) Performance Analysis of Graphene-Based Field-Effect Transistors in Ternary Logic: a review. In: Singh J, Kumar S, Choudhury U (eds) Innovations in Cyber Physical Systems: Select Proceedings of ICICPS 2020. Springer, Singapore, pp 605\u2013616"},{"key":"2800_CR4","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1016\/j.vlsi.2022.09.002","volume":"88","author":"DR Florance","year":"2023","unstructured":"Florance DR, Prabhakar B (2023) Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies. Integration 88:32\u201342","journal-title":"Integration"},{"issue":"10","key":"2800_CR5","volume":"10","author":"HS Gharavi","year":"2021","unstructured":"Gharavi HS, Moaiyeri MH (2021) Crosstalk delay and noise optimization in nanoscale multi-line interconnects based on repeater staggering in ternary logic. ECS J Sol Sta Sci Tec 10(10):101003","journal-title":"ECS J Sol Sta Sci Tec"},{"key":"2800_CR6","doi-asserted-by":"crossref","unstructured":"Goel MK, Sharma K (2024) Design and Analysis of FinFET models based Ternary Half Subtractor. In 2024 3rd International Conference for Innovation in Technology (INOCON) (pp. 1\u20135). IEEE","DOI":"10.1109\/INOCON60754.2024.10511394"},{"key":"2800_CR7","doi-asserted-by":"publisher","first-page":"100118","DOI":"10.1016\/j.memori.2024.100118","volume":"8","author":"AG Goenka","year":"2024","unstructured":"Goenka AG, Mitra S, Maheshwari H, Das N (2024) Design and simulation of balanced ternary priority encoder. Memories-Mater Devices Circuits Syst. 8:100118","journal-title":"Memories-Mater Devices Circuits Syst."},{"issue":"1","key":"2800_CR8","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1038\/s41598-021-96555-6","volume":"11","author":"S-J Han","year":"2021","unstructured":"Han S-J et al (2021) Author Correction: Ternary logic decoder using independently controlled double-gate Si-NW MOSFETs. Sci Rep 11(1):1\u20131","journal-title":"Sci Rep"},{"issue":"3","key":"2800_CR9","doi-asserted-by":"publisher","first-page":"128","DOI":"10.1007\/s11107-023-00994-2","volume":"45","author":"S Hu","year":"2023","unstructured":"Hu S (2023) An optimized and area-efficient QCA-based subtractor with easy access to input and output: design and cost estimation. Photon Netw Commun 45(3):128\u2013135","journal-title":"Photon Netw Commun"},{"key":"2800_CR10","first-page":"1973","volume":"109","author":"R Katayoun","year":"2021","unstructured":"Katayoun R, Hosseini SA (2021) Design of ternary logic gates and buffer-based memory cell in nanoelectronics. Int J Electron 109:1973\u20131995","journal-title":"Int J Electron"},{"key":"2800_CR11","doi-asserted-by":"publisher","DOI":"10.1016\/j.orgel.2021.106157","volume":"93","author":"S-Y Kim","year":"2021","unstructured":"Kim S-Y et al (2021) Demonstration of programmable ternary graphene field-effect transistor using ferroelectric polymer doping. Org Ele 93:106157","journal-title":"Org Ele"},{"issue":"3","key":"2800_CR12","doi-asserted-by":"publisher","first-page":"315","DOI":"10.1108\/CW-05-2020-0096","volume":"49","author":"TNJ Kolanti","year":"2023","unstructured":"Kolanti TNJ, Patel KSV (2023) Design of ternary subtractor using multiplexers. Circuit World 49(3):315\u2013327","journal-title":"Circuit World"},{"key":"2800_CR13","doi-asserted-by":"publisher","first-page":"355","DOI":"10.1016\/j.matpr.2022.12.036","volume":"79","author":"S Kumar","year":"2023","unstructured":"Kumar S, Dubey AK, Gupta V, Ojha MK (2023) Low power based ternary half adder using fin type field effect transistor technology. Mater Today Proc 79:355\u2013361","journal-title":"Mater Today Proc"},{"issue":"3","key":"2800_CR14","doi-asserted-by":"publisher","first-page":"111","DOI":"10.1049\/cds2.12152","volume":"17","author":"S Nemati","year":"2023","unstructured":"Nemati S, Haghi Kashani M, Faghih Mirzaee R (2023) Comprehensive survey of ternary full adders: Statistics, corrections, and assessments. IET Circuits Devices Syst 17(3):111\u2013134","journal-title":"IET Circuits Devices Syst"},{"issue":"12","key":"2800_CR15","first-page":"1","volume":"53","author":"SM Pal","year":"2021","unstructured":"Pal SM et al (2021) Design of polarization conversion and rotation based ternary logic AND\/NAND, OR\/NOR, Ex-OR\/Ex-NOR gates using ring resonator. Opt qua Ele 53(12):1\u201322","journal-title":"Opt qua Ele"},{"issue":"9","key":"2800_CR16","doi-asserted-by":"publisher","first-page":"5634","DOI":"10.1007\/s00034-023-02380-9","volume":"42","author":"A Paul","year":"2023","unstructured":"Paul A, Pradhan B (2023) Design of CNTFET-based ternary and quaternary magnitude comparator. Circuits Syst Signal Process 42(9):5634\u20135662","journal-title":"Circuits Syst Signal Process"},{"key":"2800_CR17","doi-asserted-by":"crossref","unstructured":"CS Pittala, et al. (2021) Energy Efficient Decoder Circuit Using Source Biasing Technique in CNTFET Technology,\u201d 2021 Devices for Integrated Circuit (DevIC), Kalyani, India, pp. 610\u2013615.","DOI":"10.1109\/DevIC50843.2021.9455824"},{"key":"2800_CR18","doi-asserted-by":"publisher","DOI":"10.1007\/s12652-021-03017-y","author":"BMS Rani","year":"2021","unstructured":"Rani BMS et al (2021) Disease prediction based retinal segmentation using bi-directional ConvLSTMU-Net. J Ambient Intell Humanized Comput. https:\/\/doi.org\/10.1007\/s12652-021-03017-y","journal-title":"J Ambient Intell Humanized Comput"},{"key":"2800_CR19","doi-asserted-by":"publisher","first-page":"100285","DOI":"10.1016\/j.prime.2023.100285","volume":"6","author":"SV RatanKumar","year":"2023","unstructured":"RatanKumar SV, Rao LK, Kumar MK (2023) Design of ternary full-adder and full-subtractor using pseudo NCNTFETs. e-Prime-Adv Electrical Eng Electron Energ 6:100285","journal-title":"e-Prime-Adv Electrical Eng Electron Energ"},{"key":"2800_CR20","doi-asserted-by":"publisher","DOI":"10.1016\/j.memori.2024.100118","author":"S Swathi","year":"2021","unstructured":"Swathi S et al (2021) A hierarchical image matting model for blood vessel segmentation in retinal images. Int J Syst Assurance Eng Manag. https:\/\/doi.org\/10.1016\/j.memori.2024.100118","journal-title":"Int J Syst Assurance Eng Manag"},{"key":"2800_CR21","doi-asserted-by":"crossref","unstructured":"Tharuni S, Reddy BH, Mamatha B, Kumar UA, Ahmed SE, Veeramachaneni S (2023) Power Efficient Approximate Ternary Subtractor for Image Processing Applications. In 2023 IEEE International Symposium on Smart Electronic Systems (iSES) (pp. 127\u2013130). IEEE","DOI":"10.1109\/iSES58672.2023.00035"},{"key":"2800_CR22","unstructured":"Vijay V et al. (2011) Energy efficient CMOS Full-Adder Designed with TSMC 0.18\u03bcm Technology,\u201d International Conference on Technology and Management (ICTM-2011), Hyderabad, India, pp. 356\u2013361"},{"issue":"6","key":"2800_CR23","doi-asserted-by":"publisher","first-page":"1173","DOI":"10.1007\/s13198-021-01372-9","volume":"12","author":"V Vijay","year":"2021","unstructured":"Vijay V et al (2021) ECG performance validation using operational transconductance amplifier with bias current. Int J Syst Assurance Eng Manag 12(6):1173\u20131179","journal-title":"Int J Syst Assurance Eng Manag"},{"issue":"12","key":"2800_CR24","doi-asserted-by":"publisher","DOI":"10.1088\/1674-1056\/ac248b","volume":"30","author":"X-Y Wang","year":"2021","unstructured":"Wang X-Y et al (2021) A review on the design of ternary logic circuits. Chin Phy B 30(12):128402","journal-title":"Chin Phy B"}],"container-title":["International Journal of System Assurance Engineering and Management"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s13198-025-02800-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s13198-025-02800-w\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s13198-025-02800-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,26]],"date-time":"2025-06-26T08:45:47Z","timestamp":1750927547000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s13198-025-02800-w"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,21]]},"references-count":24,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2025,6]]}},"alternative-id":["2800"],"URL":"https:\/\/doi.org\/10.1007\/s13198-025-02800-w","relation":{},"ISSN":["0975-6809","0976-4348"],"issn-type":[{"type":"print","value":"0975-6809"},{"type":"electronic","value":"0976-4348"}],"subject":[],"published":{"date-parts":[[2025,5,21]]},"assertion":[{"value":"14 December 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 April 2025","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 May 2025","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors have no relevant financial or non-financial interests to disclose. The authors have no conflicts of interest to declare that are relevant to the content of this article. All authors certify that they have no affiliations with or involvement in any organization or entity with any financial interest or non-financial interest in the subject matter or materials discussed in this manuscript. The authors have no financial or proprietary interests in any material discussed in this article.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}},{"value":"The research not involving any human participants and\/or animals.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Human and\/or Animal rights"}}]}}