{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T14:40:02Z","timestamp":1747838402194,"version":"3.41.0"},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2015,3,25]],"date-time":"2015-03-25T00:00:00Z","timestamp":1427241600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Cryptogr Eng"],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1007\/s13389-013-0060-8","type":"journal-article","created":{"date-parts":[[2015,3,24]],"date-time":"2015-03-24T10:46:52Z","timestamp":1427194012000},"page":"1-11","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["A new power-aware FPGA design metric"],"prefix":"10.1007","volume":"5","author":[{"given":"Joshua R.","family":"Templin","sequence":"first","affiliation":[]},{"given":"Jason R.","family":"Hamlet","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2015,3,25]]},"reference":[{"key":"60_CR1","unstructured":"Federal Information Processing Standards Publication 197\u2014Announcing the ADVANCED ENCRYPTION STANDARD (AES), National Institute of Standards and Technology (NIST), November 2001 (2001)"},{"key":"60_CR2","doi-asserted-by":"crossref","unstructured":"Chodowiec, P., Gaj, K.: Very compact FPGA implementation of the aes algorithm. In: CHES, pp. 319\u2013333 (2003)","DOI":"10.1007\/978-3-540-45238-6_26"},{"key":"60_CR3","doi-asserted-by":"crossref","unstructured":"Rouvroy, G., Standaert, F.X., Quisquater, J.J., Legat, J.D.: Compact and efficient encryption\/decryption module for FPGA implementation of the aes rijndael very well suited for small embedded applications. In: International Conference on Information Technology: Coding and Computing, 2004. Proceedings of ITCC 2004, vol. 2, april 2004, pp. 583\u2013587 (2004)","DOI":"10.1109\/ITCC.2004.1286716"},{"key":"60_CR4","doi-asserted-by":"crossref","unstructured":"Standaert, F.X., Rouvroy, G., Quisquater, J.J., Legat, J.D.: Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs, pp. 334\u2013350 (2003)","DOI":"10.1007\/978-3-540-45238-6_27"},{"key":"60_CR5","doi-asserted-by":"crossref","unstructured":"Zambreno, J., Nguyen, D., Choudhary, A.: Exploring area\/delay tradeoffs in an aes FPGA implementation. In: Proceedings of the 14th Annual International Conference on Field-Programmable Logic and Applications (FPL 04), pp. 575\u2013585. Springer, Berlin (2004)","DOI":"10.1007\/978-3-540-30117-2_59"},{"key":"60_CR6","unstructured":"Oswald, E.: State of the art in hardware architectures. In: Technical Report, ECRYPTEuropean Network of Excellence in Cryptology (2005)"},{"key":"60_CR7","unstructured":"Chang, C.J., Huang, C.W., Chang, K.H., Chen, Y.C., Hsieh, C.C.: High throughput 32-bit aes implementation in FPGA. In: IEEE Asia Pacific Conference on Circuits and Systems, 2008. APCCAS 2008, 30 2008\u2013Dec. 3, pp. 1806\u20131809 (2008)"},{"key":"60_CR8","doi-asserted-by":"crossref","unstructured":"Fan C.P., Hwang, J.K.: Implementations of high throughput sequential and fully pipelined aes processors on FPGA. In: Intelligent Signal Processing and Communication Systems, 2007. ISPACS 2007. International Symposium on, 28 2007\u2013Dec. 1, pp. 353\u2013356 (2007)","DOI":"10.1109\/ISPACS.2007.4445896"},{"key":"60_CR9","unstructured":"Qu, S., Shou, G., Hu, Y., Guo, Z., Qian, Z.: High throughput, pipelined implementation of aes on FPGA. In: International Symposium on Information Engineering and Electronic Commerce, 2009. IEEC 09, May 2009, pp. 542\u2013545 (2009)"},{"key":"60_CR10","doi-asserted-by":"crossref","unstructured":"Rizk, M., Morsy, M.: Optimized area and optimized speed hardware implementations of AES on FPGA. In: 2nd International Design and Test Workshop, 2007. IDT 2007, Dec. 2007, pp. 207\u2013217","DOI":"10.1109\/IDT.2007.4437462"},{"key":"60_CR11","doi-asserted-by":"crossref","unstructured":"Verbauwhede, I., Schaumont, P., Kuo, H.: Design and performance testing of a 2.29-gb\/s rijndael processor. IEEE J. Solid-State Circuits 38(3); 569\u2013572 (2003)","DOI":"10.1109\/JSSC.2002.808300"},{"key":"60_CR12","unstructured":"Dongara, P., Vijaykumar, T.: Accelerating private-key cryptography via multithreading on symmetric multiprocessors. In: 2003 IEEE International Symposium on Performance Analysis of Systems and Software, 2003. ISPASS, March 2003, pp. 58\u201369 (2003)"},{"key":"60_CR13","unstructured":"Elbirt, A., Yip, W., Chetwynd, B., Paar, C.: An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists. In: The Third Advanced Encryption Standard Candidate Conference, 2000. AES3 2000 (2000)"},{"key":"60_CR14","unstructured":"Xilinx: Virtex-6 Family Overview, January 2012, dS150 (2012)"},{"key":"60_CR15","unstructured":"Xilinx: Virtex-4 Family Overview, August 2010, dS112 (2010)"},{"key":"60_CR16","doi-asserted-by":"crossref","unstructured":"Jarvinen, K., Tommiska, M., Skytta, J.: Comparative survey of high-performance cryptographic algorithm implementations on FPGAs. IEE Proc. Inf. Secur. 152(1), 3\u201312 (2005)","DOI":"10.1049\/ip-ifs:20055004"},{"key":"60_CR17","unstructured":"Saggese, G., Mazzeo, A., Mazzocca, N., Strollo, A.: An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm. In: Cheung, P.Y.K., Constantinides, G. (eds.) Field Programmable Logic and Application. Lecture Notes in Computer Science, vol. 2778, pp. 292\u2013302. Springer, Berlin (2003). doi: 10.1007\/978-3-540-45234-829"},{"key":"60_CR18","doi-asserted-by":"crossref","unstructured":"Good, T., Benaissa, M.: AES on FPGA from the fastest to the smallest. In: Rao, J., Sunar, B. (eds.) Cryptographic Hardware and Embedded Systems (CHES) 2005. Lecture Notes in Computer Science, vol. 3659, pp. 427\u2013440. Springer, Berlin (2005). doi: 10.1007\/11545262","DOI":"10.1007\/11545262"},{"key":"60_CR19","unstructured":"Huang, C.W., Chang, C.J., Lin, M.Y., Tai, H.Y.: The FPGA implementation of 128-bits aes algorithmbased on four 32-bits parallel operation. In: The First International Symposium on Data, Privacy, and E-Commerce, 2007. ISDPE 2007, Nov. 2007, pp. 462\u2013464 (2007)"},{"key":"60_CR20","unstructured":"Hodjat, A., Verbauwhede, I.: A 21.54 gbits\/s fully pipelined aes processor on FPGA. In: 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2004. FCCM 2004, April 2004, pp. 308\u2013309 (2004)"},{"key":"60_CR21","unstructured":"Horowitz, M., Indermaur, T., Gonzalez, R.: Low-power digital design. In: IEEE Symposium on Low Power Electronics, 1994. Digest of Technical Papers, Oct 1994, p. 811 (1994)"},{"key":"60_CR22","unstructured":"Didla, S., Ault, A., Bagchi, S.: Optimizing aes for embedded devices and wireless sensor networks. In: Proceedings of the 4th International Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities. TridentCom 08. ICST, Brussels, Belgium, Belgium: ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), 2008, pp. 4:14:10 (2008)"},{"key":"60_CR23","doi-asserted-by":"crossref","unstructured":"Gupta, A., Ahmad, A., Sharif, M., Amira, A.: Rapid prototyping of aes encryption for wireless communication system on FPGA. In: 2011 IEEE 15th International Symposium on Consumer Electronics (ISCE), June 2011, pp. 571\u2013575 (2011)","DOI":"10.1109\/ISCE.2011.5973895"},{"key":"60_CR24","unstructured":"Ghaznavi, S., Gebotys, C., Elbaz, R.: Efficient technique for the FPGA implementation of the aes mixcolumns transformation. In: International Conference on Reconfigurable Computing and FPGAs, 2009. ReConFig 09, Dec. 2009, pp. 219\u2013224 (2009)"},{"key":"60_CR25","unstructured":"Ruschival, T.: (2010, March) Avalon aes ecb-core (128, 192, 256 bit). OpenCores. http:\/\/opencores.org\/project,avs_aes"},{"key":"60_CR26","unstructured":"Gbur, J.: (2011, Nov) AES core modules. OpenCores. http:\/\/opencores.org\/project,aes128192256"}],"container-title":["Journal of Cryptographic Engineering"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s13389-013-0060-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s13389-013-0060-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s13389-013-0060-8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T13:59:21Z","timestamp":1747835961000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s13389-013-0060-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3,25]]},"references-count":26,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2015,4]]}},"alternative-id":["60"],"URL":"https:\/\/doi.org\/10.1007\/s13389-013-0060-8","relation":{},"ISSN":["2190-8508","2190-8516"],"issn-type":[{"type":"print","value":"2190-8508"},{"type":"electronic","value":"2190-8516"}],"subject":[],"published":{"date-parts":[[2015,3,25]]}}}