{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,15]],"date-time":"2026-06-15T06:12:09Z","timestamp":1781503929004,"version":"3.54.1"},"reference-count":75,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2026,1,4]],"date-time":"2026-01-04T00:00:00Z","timestamp":1767484800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2026,1,4]],"date-time":"2026-01-04T00:00:00Z","timestamp":1767484800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/501100004410","name":"The Scientific and Technological Research Council of T\u00fcrkiye","doi-asserted-by":"crossref","award":["123N546"],"award-info":[{"award-number":["123N546"]}],"id":[{"id":"10.13039\/501100004410","id-type":"DOI","asserted-by":"crossref"}]},{"name":"German Academic Exchange Service"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Cryptogr Eng"],"published-print":{"date-parts":[[2026,4]]},"DOI":"10.1007\/s13389-025-00388-2","type":"journal-article","created":{"date-parts":[[2026,1,4]],"date-time":"2026-01-04T08:34:42Z","timestamp":1767515682000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES"],"prefix":"10.1007","volume":"16","author":[{"given":"Ahmet","family":"Malal","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Cihangir","family":"Tezcan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2026,1,4]]},"reference":[{"key":"388_CR1","unstructured":"NIST: NIST Proposes to Standardize Wider Variant of AES. Accessed: 2025-02-09 (2024). https:\/\/csrc.nist.gov\/news\/2024\/nist-proposes-to-standardize-wider-variant-of-aes"},{"issue":"3","key":"388_CR2","doi-asserted-by":"publisher","first-page":"164","DOI":"10.1109\/LES.2024.3510365","volume":"17","author":"M El-Hadedy","year":"2025","unstructured":"El-Hadedy, M., Abelian, A., Lee, K., Cheng, B.N., Hwu, W.-M.: Anubis: hybrid fpaa-fpga architecture for entropy-based true random number generation in secure uav communication. IEEE Embed. Syst. Lett. 17(3), 164\u2013167 (2025). https:\/\/doi.org\/10.1109\/LES.2024.3510365","journal-title":"IEEE Embed. Syst. Lett."},{"key":"388_CR3","doi-asserted-by":"publisher","unstructured":"Canright, D.: A very compact s-box for AES. In: Rao, J.R., Sunar, B. (eds.) Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings. Lecture Notes in Computer Science, vol. 3659, pp. 441\u2013455. Springer, (2005). https:\/\/doi.org\/10.1007\/11545262_32","DOI":"10.1007\/11545262_32"},{"key":"388_CR4","doi-asserted-by":"publisher","DOI":"10.1016\/J.MICPRO.2024.105007","volume":"105","author":"A Malal","year":"2024","unstructured":"Malal, A., Tezcan, C.: Fpga-friendly compact and efficient aes-like 8 $$\\times $$ 8 s-box. Microprocess. Microsystems 105, 105007 (2024). https:\/\/doi.org\/10.1016\/J.MICPRO.2024.105007","journal-title":"Microprocess. Microsystems"},{"issue":"7","key":"388_CR5","doi-asserted-by":"publisher","first-page":"480","DOI":"10.1016\/J.MICPRO.2015.07.005","volume":"39","author":"A Soltani","year":"2015","unstructured":"Soltani, A., Sharifian, S.: An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA. Microprocess. Microsystems 39(7), 480\u2013493 (2015). https:\/\/doi.org\/10.1016\/J.MICPRO.2015.07.005","journal-title":"Microprocess. Microsystems"},{"key":"388_CR6","doi-asserted-by":"publisher","first-page":"67315","DOI":"10.1109\/ACCESS.2021.3077551","volume":"9","author":"C Tezcan","year":"2021","unstructured":"Tezcan, C.: Optimization of advanced encryption standard on graphics processing units. IEEE Access 9, 67315\u201367326 (2021). https:\/\/doi.org\/10.1109\/ACCESS.2021.3077551","journal-title":"IEEE Access"},{"key":"388_CR7","doi-asserted-by":"publisher","unstructured":"Biham, E., Shamir, A.: Differential cryptanalysis of des-like cryptosystems. In: Menezes, A., Vanstone, S.A. (eds.) Advances in Cryptology - CRYPTO \u201990, 10th Annual International Cryptology Conference, Santa Barbara, California, USA, August 11-15, 1990, Proceedings. Lecture Notes in Computer Science, vol. 537, pp. 2\u201321. Springer, (1990). https:\/\/doi.org\/10.1007\/3-540-38424-3_1","DOI":"10.1007\/3-540-38424-3_1"},{"key":"388_CR8","doi-asserted-by":"publisher","unstructured":"Matsui, M.: Linear cryptanalysis method for DES cipher. In: Helleseth, T. (ed.) Advances in Cryptology - EUROCRYPT \u201993, Workshop on the Theory and Application of of Cryptographic Techniques, Lofthus, Norway, May 23-27, 1993, Proceedings. Lecture Notes in Computer Science, vol. 765, pp. 386\u2013397. Springer, (1993). https:\/\/doi.org\/10.1007\/3-540-48285-7_33","DOI":"10.1007\/3-540-48285-7_33"},{"issue":"8","key":"388_CR9","doi-asserted-by":"publisher","first-page":"1014","DOI":"10.1016\/J.MEJO.2014.05.004","volume":"45","author":"RR Farashahi","year":"2014","unstructured":"Farashahi, R.R., Rashidi, B., Sayedi, S.M.: FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm. Microelectron. J. 45(8), 1014\u20131025 (2014). https:\/\/doi.org\/10.1016\/J.MEJO.2014.05.004","journal-title":"Microelectron. J."},{"issue":"8","key":"388_CR10","doi-asserted-by":"publisher","first-page":"1075","DOI":"10.1016\/J.JPDC.2011.04.006","volume":"71","author":"MI Soliman","year":"2011","unstructured":"Soliman, M.I., Abozaid, G.Y.: FPGA implementation and performance evaluation of a high throughput crypto coprocessor. J. Parallel Distributed Comput. 71(8), 1075\u20131084 (2011). https:\/\/doi.org\/10.1016\/J.JPDC.2011.04.006","journal-title":"J. Parallel Distributed Comput."},{"key":"388_CR11","doi-asserted-by":"crossref","unstructured":"Samiee, H., Atani, R.E., Amindavar, H.: A novel area-throughput optimized architecture for the aes algorithm. In: 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA), pp. 29\u201332 (2011). IEEE","DOI":"10.1109\/ICEDSA.2011.5959055"},{"key":"388_CR12","doi-asserted-by":"crossref","unstructured":"Fan, C.-P., Hwang, J.-K.: Implementations of high throughput sequential and fully pipelined aes processors on fpga. In: 2007 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 353\u2013356 (2007). IEEE","DOI":"10.1109\/ISPACS.2007.4445896"},{"key":"388_CR13","doi-asserted-by":"crossref","unstructured":"Iyer, N.C., Anandmohan, P., Poornaiah, D., Kulkarni, V.: High throughput, low cost, fully pipelined architecture for aes crypto chip. In: 2006 Annual IEEE India Conference, pp. 1\u20136 (2006). IEEE","DOI":"10.1109\/INDCON.2006.302814"},{"key":"388_CR14","doi-asserted-by":"crossref","unstructured":"Qu, S., Shou, G., Hu, Y., Guo, Z., Qian, Z.: High throughput, pipelined implementation of aes on fpga. In: 2009 International Symposium on Information Engineering and Electronic Commerce, pp. 542\u2013545 (2009). IEEE","DOI":"10.1109\/IEEC.2009.120"},{"key":"388_CR15","doi-asserted-by":"publisher","first-page":"87","DOI":"10.1016\/j.vlsi.2022.04.005","volume":"85","author":"X Guo","year":"2022","unstructured":"Guo, X., El-Hadedy, M., Mosanu, S., Wei, X., Skadron, K., Stan, M.R.: Agile-aes: implementation of configurable aes primitive with agile design approach. Integr. 85, 87\u201396 (2022)","journal-title":"Integr."},{"issue":"6","key":"388_CR16","doi-asserted-by":"publisher","first-page":"1160","DOI":"10.1016\/J.COMPELECENG.2011.06.003","volume":"37","author":"L Ali","year":"2011","unstructured":"Ali, L., Aris, I., Hossain, F.S., Roy, N.: Design of an ultra high speed AES processor for next generation IT security. Comput. Electr. Eng. 37(6), 1160\u20131170 (2011). https:\/\/doi.org\/10.1016\/J.COMPELECENG.2011.06.003","journal-title":"Comput. Electr. Eng."},{"issue":"D(3)","key":"388_CR17","doi-asserted-by":"publisher","first-page":"1139","DOI":"10.1093\/IETISY\/E89-D.3.1139","volume":"89","author":"H Qin","year":"2006","unstructured":"Qin, H., Sasao, T., Iguchi, Y.: A design of AES encryption circuit with 128-bit keys using look-up table ring on FPGA. IEICE Trans. Inf. Syst. 89(D(3)), 1139\u20131147 (2006). https:\/\/doi.org\/10.1093\/IETISY\/E89-D.3.1139","journal-title":"IEICE Trans. Inf. Syst."},{"key":"388_CR18","doi-asserted-by":"publisher","unstructured":"Rouvroy, G., Standaert, F., Quisquater, J., Legat, J.: Compact and efficient encryption\/decryption module for FPGA implementation of the AES rijndael very well suited for small embedded applications. In: International Conference on Information Technology: Coding and Computing (ITCC\u201904), Volume 2, April 5-7, 2004, Las Vegas, Nevada, USA, pp. 583\u2013587. IEEE Computer Society, (2004). https:\/\/doi.org\/10.1109\/ITCC.2004.1286716","DOI":"10.1109\/ITCC.2004.1286716"},{"issue":"11","key":"388_CR19","doi-asserted-by":"publisher","first-page":"2829","DOI":"10.1016\/J.MICROREL.2012.04.020","volume":"52","author":"H Li","year":"2012","unstructured":"Li, H., Ding, J., Pan, Y.: Cell array reconfigurable architecture for high-efficiency AES system. Microelectron. Reliab. 52(11), 2829\u20132836 (2012). https:\/\/doi.org\/10.1016\/J.MICROREL.2012.04.020","journal-title":"Microelectron. Reliab."},{"key":"388_CR20","doi-asserted-by":"publisher","unstructured":"Maraghy, M.E., Hesham, S., Ghany, M.A.A.E.: Real-time efficient FPGA implementation of aes algorithm. In: Schuhmann, N., Shi, K., Naganathan, N. (eds.) 2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013, pp. 203\u2013208. IEEE, (2013). https:\/\/doi.org\/10.1109\/SOCC.2013.6749688","DOI":"10.1109\/SOCC.2013.6749688"},{"key":"388_CR21","doi-asserted-by":"publisher","unstructured":"Rais, M.H., Qasim, S.M.: Fpga implementation of rijndael algorithm using reduced residue of prime numbers. In: 2009 4th International Design and Test Workshop (IDT), pp. 1\u20134 (2009). https:\/\/doi.org\/10.1109\/IDT.2009.5404130","DOI":"10.1109\/IDT.2009.5404130"},{"key":"388_CR22","doi-asserted-by":"publisher","unstructured":"Bulens, P., Standaert, F., Quisquater, J., Pellegrin, P., Rouvroy, G.: Implementation of the AES-128 on virtex-5 fpgas 5023, 16\u201326 (2008) https:\/\/doi.org\/10.1007\/978-3-540-68164-9_2","DOI":"10.1007\/978-3-540-68164-9_2"},{"key":"388_CR23","doi-asserted-by":"publisher","unstructured":"Standaert, F., Rouvroy, G., Quisquater, J., Legat, J.: A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL. In: Trimberger, S., Tessier, R. (eds.) Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 216\u2013224. ACM, (2003). https:\/\/doi.org\/10.1145\/611817.611849","DOI":"10.1145\/611817.611849"},{"issue":"3","key":"388_CR24","doi-asserted-by":"publisher","first-page":"261","DOI":"10.1023\/A:1023252403567","volume":"34","author":"M McLoone","year":"2003","unstructured":"McLoone, M., McCanny, J.V.: Rijndael FPGA implementations utilising look-up tables. J. VLSI Signal Process. 34(3), 261\u2013275 (2003). https:\/\/doi.org\/10.1023\/A:1023252403567","journal-title":"J. VLSI Signal Process."},{"key":"388_CR25","doi-asserted-by":"publisher","unstructured":"J\u00e4rvinen, K.U., Tommiska, M., Skytt\u00e4, J.: A fully pipelined memoryless 17.8 gbps AES-128 encryptor. In: Trimberger, S., Tessier, R. (eds.) Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 207\u2013215. ACM, (2003). https:\/\/doi.org\/10.1145\/611817.611848","DOI":"10.1145\/611817.611848"},{"key":"388_CR26","doi-asserted-by":"publisher","unstructured":"Lemsitzer, S., Wolkerstorfer, J., Felber, N., Braendli, M.: Multi-gigabit GCM-AES architecture optimized for fpgas. In: Paillier, P., Verbauwhede, I. (eds.) Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings. Lecture Notes in Computer Science, vol. 4727, pp. 227\u2013238. Springer, (2007). https:\/\/doi.org\/10.1007\/978-3-540-74735-2_16","DOI":"10.1007\/978-3-540-74735-2_16"},{"key":"388_CR27","doi-asserted-by":"publisher","unstructured":"Standaert, F., Rouvroy, G., Quisquater, J., Legat, J.: Efficient implementation of rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs. In: Walter, C.D., Ko\u00e7, \u00c7.K., Paar, C. (eds.) Cryptographic Hardware and Embedded Systems - CHES 2003, 5th International Workshop, Cologne, Germany, September 8-10, 2003, Proceedings. Lecture Notes in Computer Science, vol. 2779, pp. 334\u2013350. Springer, (2003). https:\/\/doi.org\/10.1007\/978-3-540-45238-6_27","DOI":"10.1007\/978-3-540-45238-6_27"},{"key":"388_CR28","doi-asserted-by":"publisher","unstructured":"Saggese, G.P., Mazzeo, A., Mazzocca, N., Strollo, A.G.M.: An fpga-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm. In: Cheung, P.Y.K., Constantinides, G.A., Sousa, J.T. (eds.) Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings. Lecture Notes in Computer Science, vol. 2778, pp. 292\u2013302. Springer, (2003). https:\/\/doi.org\/10.1007\/978-3-540-45234-8_29","DOI":"10.1007\/978-3-540-45234-8_29"},{"key":"388_CR29","doi-asserted-by":"crossref","unstructured":"Gielata, A., Russek, P., Wiatr, K.: Aes hardware implementation in fpga for algorithm acceleration purpose. In: 2008 International Conference on Signals and Electronic Systems, pp. 137\u2013140 (2008). IEEE","DOI":"10.1109\/ICSES.2008.4673377"},{"key":"388_CR30","doi-asserted-by":"publisher","unstructured":"Hodjat, A., Verbauwhede, I.: A 21.54 gbits\/s fully pipelined AES processor on FPGA. In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 308\u2013309. IEEE Computer Society, (2004). https:\/\/doi.org\/10.1109\/FCCM.2004.1","DOI":"10.1109\/FCCM.2004.1"},{"issue":"9","key":"388_CR31","doi-asserted-by":"publisher","first-page":"957","DOI":"10.1109\/TVLSI.2004.832943","volume":"12","author":"X Zhang","year":"2004","unstructured":"Zhang, X., Parhi, K.K.: High-speed VLSI architectures for the AES algorithm. IEEE Trans. Very Large Scale Integr. Syst. 12(9), 957\u2013967 (2004). https:\/\/doi.org\/10.1109\/TVLSI.2004.832943","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"388_CR32","doi-asserted-by":"publisher","unstructured":"Zambreno, J., Nguyen, D., Choudhary, A.N.: Exploring area\/delay tradeoffs in an AES FPGA implementation. In: Becker, J., Platzner, M., Vernalde, S. (eds.) Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings. Lecture Notes in Computer Science, vol. 3203, pp. 575\u2013585. Springer, (2004). https:\/\/doi.org\/10.1007\/978-3-540-30117-2_59","DOI":"10.1007\/978-3-540-30117-2_59"},{"issue":"1","key":"388_CR33","doi-asserted-by":"publisher","first-page":"72","DOI":"10.1016\/J.VLSI.2009.05.003","volume":"43","author":"JMG Criado","year":"2010","unstructured":"Criado, J.M.G., Vega-Rodr\u00edguez, M.A., S\u00e1nchez-P\u00e9rez, J.M., Pulido, J.A.G.: A new methodology to implement the AES algorithm using partial and dynamic reconfiguration. Integr. 43(1), 72\u201380 (2010). https:\/\/doi.org\/10.1016\/J.VLSI.2009.05.003","journal-title":"Integr."},{"key":"388_CR34","doi-asserted-by":"publisher","unstructured":"Good, T., Benaissa, M.: AES on FPGA from the fastest to the smallest. In: Rao, J.R., Sunar, B. (eds.) Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings. Lecture Notes in Computer Science, vol. 3659, pp. 427\u2013440. Springer, (2005). https:\/\/doi.org\/10.1007\/11545262_31","DOI":"10.1007\/11545262_31"},{"key":"388_CR35","doi-asserted-by":"crossref","unstructured":"Rizk, M., Morsy, M.: Optimized area and optimized speed hardware implementations of aes on fpga. In: 2007 2nd International Design and Test Workshop, pp. 207\u2013217 (2007). IEEE","DOI":"10.1109\/IDT.2007.4437462"},{"issue":"7","key":"388_CR36","doi-asserted-by":"publisher","first-page":"317","DOI":"10.1016\/J.MICPRO.2004.12.001","volume":"29","author":"S Yoo","year":"2005","unstructured":"Yoo, S., Kotturi, D., Pan, W.D., Blizzard, J.: An AES crypto chip using a high-speed parallel pipelined architecture. Microprocess. Microsystems 29(7), 317\u2013326 (2005). https:\/\/doi.org\/10.1016\/J.MICPRO.2004.12.001","journal-title":"Microprocess. Microsystems"},{"issue":"1","key":"388_CR37","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1049\/IET-IFS:20060059","volume":"1","author":"T Good","year":"2007","unstructured":"Good, T., Benaissa, M.: Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment). IET Inf. Secur. 1(1), 1\u201310 (2007). https:\/\/doi.org\/10.1049\/IET-IFS:20060059","journal-title":"IET Inf. Secur."},{"key":"388_CR38","doi-asserted-by":"crossref","unstructured":"Nalini, C., Anandmohan, P., Poornaiah, D., et al.: An fpga based performance analysis of pipelining and unrolling of aes algorithm. In: 2006 International Conference on Advanced Computing and Communications, pp. 477\u2013482 (2006). IEEE","DOI":"10.1109\/ADCOM.2006.4289939"},{"key":"388_CR39","doi-asserted-by":"crossref","unstructured":"Banu, J.S., Vanitha, M., Vaideeswaran, J., Subha, S.: Loop parallelization and pipelining implementation of aes algorithm using openmp and fpga. In: 2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN), pp. 481\u2013485 (2013). IEEE","DOI":"10.1109\/ICE-CCN.2013.6528547"},{"issue":"3","key":"388_CR40","first-page":"186","volume":"2","author":"A Kaur","year":"2013","unstructured":"Kaur, A., Bhardwaj, P., Kumar, N.: Fpga implementation of efficient hardware for the advanced encryption standard. Int. j. innov. technol. explor. eng. 2(3), 186\u2013189 (2013)","journal-title":"Int. j. innov. technol. explor. eng."},{"key":"388_CR41","doi-asserted-by":"crossref","unstructured":"Zhang, Y., Wang, X.: Pipelined implementation of aes encryption based on fpga. In: 2010 IEEE International Conference on Information Theory and Information Security, pp. 170\u2013173 (2010). IEEE","DOI":"10.1109\/ICITIS.2010.5688757"},{"issue":"3","key":"388_CR42","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1109\/LES.2010.2052401","volume":"2","author":"I Hammad","year":"2010","unstructured":"Hammad, I., El-Sankary, K., El-Masry, E.I.: High-speed AES encryptor with efficient merging techniques. IEEE Embed. Syst. Lett. 2(3), 67\u201371 (2010). https:\/\/doi.org\/10.1109\/LES.2010.2052401","journal-title":"IEEE Embed. Syst. Lett."},{"key":"388_CR43","unstructured":"Rais, M.H., Qasim, S.M.: @articleDBLP:journals\/cee\/AliAHR11, author = Liakot Ali and Ishak Aris and Fakir Sharif Hossain and Niranjan Roy, title = Design of an ultra high speed AES processor for next generation IT security, journal = Comput. Electr. Eng., volume = 37, number = 6, pages = 1160\u20131170, year = 2011, url = https:\/\/doi.org\/10.1016\/j.compeleceng.2011.06.003, doi = 10.1016\/J.COMPELECENG.2011.06.003, timestamp = Mon, 28 Aug 2023 21:33:14 +0200, biburl = https:\/\/dblp.org\/rec\/journals\/cee\/AliAHR11.bib, bibsource = dblp computer science bibliography, https:\/\/dblp.org . International journal of computer science and network security 9(9), 59\u201363 (2009)"},{"key":"388_CR44","doi-asserted-by":"crossref","unstructured":"Perez, O., Berviller, Y., Tanougast, C., Weber, S.: Comparison of various strategies of implementation of the algorithm of encryption aes on fpga. In: 2006 IEEE International Symposium on Industrial Electronics, vol. 4, pp. 3276\u20133280 (2006). IEEE","DOI":"10.1109\/ISIE.2006.296142"},{"issue":"2","key":"388_CR45","first-page":"53","volume":"1","author":"G Singh","year":"2011","unstructured":"Singh, G., Mehra, R.: Fpga based high speed and area efficient aes encryption for data security. Int.l J. Research and Innov. Comput. Eng. 1(2), 53\u201356 (2011)","journal-title":"Int.l J. Research and Innov. Comput. Eng."},{"key":"388_CR46","doi-asserted-by":"crossref","unstructured":"Iyer, N., Anandmohan, P., Poornaiah, D., Kulkarni, V.: Efficient hardware architectures for aes on fpga. In: International Conference on Computational Intelligence and Information Technology, pp. 249\u2013257 (2011). Springer","DOI":"10.1007\/978-3-642-25734-6_37"},{"key":"388_CR47","doi-asserted-by":"crossref","unstructured":"Fayed, M., El-Kharashi, M.W., Gebali, F.: A high-speed, fully-pipelined vlsi architecture for real-time aes. In: 2006 ITI 4th International Conference on Information & Communications Technology, pp. 1\u20132 (2006). IEEE","DOI":"10.1109\/ITICT.2006.358286"},{"key":"388_CR48","doi-asserted-by":"crossref","unstructured":"Naiem, G.F., Elramly, S., Hasan, B.E., Shehata, K.: An efficient implementation of cbc mode rijndeal aes on an fpga. In: 2008 National Radio Science Conference, pp. 1\u20138 (2008). IEEE","DOI":"10.1109\/NRSC.2008.4542373"},{"issue":"11","key":"388_CR49","doi-asserted-by":"publisher","first-page":"2225","DOI":"10.1002\/SEC.651","volume":"7","author":"K Rahimunnisa","year":"2014","unstructured":"Rahimunnisa, K., Karthigaikumar, P., Rasheed, S., Jayakumar, J., Kumar, S.S.: FPGA implementation of AES algorithm for high throughput using folded parallel architecture. Secur. Commun. Networks 7(11), 2225\u20132236 (2014). https:\/\/doi.org\/10.1002\/SEC.651","journal-title":"Secur. Commun. Networks"},{"key":"388_CR50","doi-asserted-by":"publisher","unstructured":"Anwar, H., Daneshtalab, M., Ebrahimi, M., Plosila, J., Tenhunen, H.: FPGA implementation of aes-based crypto processor. In: 20th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, UAE, December 8-11, 2013, pp. 369\u2013372. IEEE, (2013). https:\/\/doi.org\/10.1109\/ICECS.2013.6815431","DOI":"10.1109\/ICECS.2013.6815431"},{"issue":"4","key":"388_CR51","doi-asserted-by":"publisher","first-page":"173","DOI":"10.2478\/S13537-013-0112-2","volume":"3","author":"K Rahimunnisa","year":"2013","unstructured":"Rahimunnisa, K., Karthigaikumar, P., Christy, N.A., Kumar, S.S., Jayakumar, J.: PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC. Central Eur. J. Comput. Sci. 3(4), 173\u2013186 (2013). https:\/\/doi.org\/10.2478\/S13537-013-0112-2","journal-title":"Central Eur. J. Comput. Sci."},{"key":"388_CR52","doi-asserted-by":"crossref","unstructured":"Zhang, X., Li, M., Hu, J.: Optimization and implementation of aes algorithm based on fpga. 2018 IEEE 4th International Conference on Computer and Communications (ICCC), 2704\u20132709 (2018)","DOI":"10.1109\/CompComm.2018.8780921"},{"key":"388_CR53","doi-asserted-by":"publisher","unstructured":"Cowart, R., Coe, D., Kulick, J.H., Milenkovic, A.: An implementation and experimental evaluation of hardware accelerated ciphers in all-programmable socs. In: Proceedings of the 2017 ACM Southeast Regional Conference, Kennesaw, GA, USA, April 13-15, 2017, pp. 34\u201341. ACM, (2017). https:\/\/doi.org\/10.1145\/3077286.3077297","DOI":"10.1145\/3077286.3077297"},{"key":"388_CR54","unstructured":"Westman, Oskar: Electromagnetic analysis of AES-256 on Xilinx Artix-7. Student Paper (2018)"},{"issue":"2","key":"388_CR55","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1504\/IJES.2023.136378","volume":"16","author":"N Bisht","year":"2023","unstructured":"Bisht, N., Pandey, B., Budhani, S.K.: Real life implementation of an energy-efficient adaptive advance encryption design on FPGA. Int. J. Embed. Syst. 16(2), 105\u2013116 (2023). https:\/\/doi.org\/10.1504\/IJES.2023.136378","journal-title":"Int. J. Embed. Syst."},{"key":"388_CR56","doi-asserted-by":"publisher","unstructured":"Smekal, D., Hajny, J., Martinasek, Z.: Comparative analysis of different implementations of encryption algorithms on fpga network cards. IFAC-PapersOnLine 51(6), 312\u2013317 (2018) https:\/\/doi.org\/10.1016\/j.ifacol.2018.07.172 . 15th IFAC Conference on Programmable Devices and Embedded Systems PDeS 2018","DOI":"10.1016\/j.ifacol.2018.07.172"},{"key":"388_CR57","doi-asserted-by":"publisher","DOI":"10.1016\/j.mex.2023.102491","volume":"11","author":"SS Dhanda","year":"2023","unstructured":"Dhanda, S.S., Jindal, P., Singh, B., Panwar, D.: A compact and efficient aes-32gf for encryption in small iot devices. MethodsX 11, 102491 (2023). https:\/\/doi.org\/10.1016\/j.mex.2023.102491","journal-title":"MethodsX"},{"key":"388_CR58","doi-asserted-by":"publisher","unstructured":"Gunasekaran, M., Rahul, K., Yachareni, S.: Virtex 7 fpga implementation of 256 bit key aes algorithm with key schedule and sub bytes block optimization. In: 2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS), pp. 1\u20136 (2021). https:\/\/doi.org\/10.1109\/IEMTRONICS52119.2021.9422547","DOI":"10.1109\/IEMTRONICS52119.2021.9422547"},{"key":"388_CR59","doi-asserted-by":"publisher","first-page":"71","DOI":"10.37537\/rev.elektron.8.2.201.2024","volume":"8","author":"H Penagos","year":"2024","unstructured":"Penagos, H., Paipilla, A., Ni\u00f1o, M.: Low area implementation of the advanced encryption standard with counter mode for system-on-chip - fpga. Elektron 8, 71\u201376 (2024). https:\/\/doi.org\/10.37537\/rev.elektron.8.2.201.2024","journal-title":"Elektron"},{"key":"388_CR60","doi-asserted-by":"publisher","unstructured":"Chen, S., Hu, W., Li, Z.: High performance data encryption with aes implementation on fpga. In: 2019 IEEE 5th Intl Conference on Big Data Security on Cloud (BigDataSecurity), IEEE Intl Conference on High Performance and Smart Computing, (HPSC) and IEEE Intl Conference on Intelligent Data and Security (IDS), pp. 149\u2013153 (2019). https:\/\/doi.org\/10.1109\/BigDataSecurity-HPSC-IDS.2019.00036","DOI":"10.1109\/BigDataSecurity-HPSC-IDS.2019.00036"},{"key":"388_CR61","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2019.102972","volume":"73","author":"S Madhavapandian","year":"2020","unstructured":"Madhavapandian, S., MaruthuPandi, P.: Fpga implementation of highly scalable aes algorithm using modified mix column with gate replacement technique for security application in tcp\/ip. Microprocessors and Microsystems 73, 102972 (2020). https:\/\/doi.org\/10.1016\/j.micpro.2019.102972","journal-title":"Microprocessors and Microsystems"},{"key":"388_CR62","doi-asserted-by":"publisher","unstructured":"Hussain, U., Jamal, H.: An efficient high throughput FPGA implementation of AES for multi-gigabit protocols. In: 10th International Conference on Frontiers of Information Technology, FIT 2012, Islamabad, Pakistan, December 17-19, 2012, pp. 215\u2013218. IEEE Computer Society, (2012). https:\/\/doi.org\/10.1109\/FIT.2012.45","DOI":"10.1109\/FIT.2012.45"},{"key":"388_CR63","doi-asserted-by":"publisher","unstructured":"Abdul-Karim, M.S., Rahouma, K.H., Nasr, K.: High throughput and fully pipelined fpga implementation of aes-192 algorithm. In: 2020 International Conference on Innovative Trends in Communication and Computer Engineering (ITCE), pp. 137\u2013142 (2020). https:\/\/doi.org\/10.1109\/ITCE48509.2020.9047815","DOI":"10.1109\/ITCE48509.2020.9047815"},{"key":"388_CR64","doi-asserted-by":"publisher","unstructured":"Srinivas, N.S.S., Akramuddin, M.: Fpga based hardware implementation of aes rijndael algorithm for encryption and decryption. In: 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), pp. 1769\u20131776 (2016). https:\/\/doi.org\/10.1109\/ICEEOT.2016.7754990","DOI":"10.1109\/ICEEOT.2016.7754990"},{"key":"388_CR65","doi-asserted-by":"publisher","DOI":"10.1016\/J.SYSARC.2022.102402","volume":"124","author":"C Tezcan","year":"2022","unstructured":"Tezcan, C.: Key lengths revisited: gpu-based brute force cryptanalysis of des, 3des, and PRESENT. J. Syst. Archit. 124, 102402 (2022). https:\/\/doi.org\/10.1016\/J.SYSARC.2022.102402","journal-title":"J. Syst. Archit."},{"key":"388_CR66","doi-asserted-by":"publisher","unstructured":"Tezcan, C., Leander, G.: GPU assisted brute force cryptanalysis of gprs, gsm, rfid, and TETRA. IACR Trans. Symmetric Cryptol. 2025(1), 309\u2013327 (2025). https:\/\/doi.org\/10.46586\/TOSC.V2025.I1.309-327","DOI":"10.46586\/TOSC.V2025.I1.309-327"},{"key":"388_CR67","doi-asserted-by":"publisher","unstructured":"Civek, A.B., Tezcan, C.: Experimentally obtained differential-linear distinguishers for permutations of ASCON and drygascon. In: Mori, P., Lenzini, G., Furnell, S. (eds.) Information Systems Security and Privacy - 7th International Conference, ICISSP 2021, Virtual Event, February 11-13, 2021, and 8th International Conference, ICISSP 2022, Virtual Event, February 9-11, 2022, Revised Selected Papers. Communications in Computer and Information Science, vol. 1851, pp. 91\u2013103. Springer, (2022). https:\/\/doi.org\/10.1007\/978-3-031-37807-2_5","DOI":"10.1007\/978-3-031-37807-2_5"},{"key":"388_CR68","doi-asserted-by":"publisher","unstructured":"Nishikawa, N., Amano, H., Iwai, K.: Implementation of bitsliced AES encryption on cuda-enabled GPU. In: Yan, Z., Molva, R., Mazurczyk, W., Kantola, R. (eds.) Network and System Security - 11th International Conference, NSS 2017, Helsinki, Finland, August 21-23, 2017, Proceedings. Lecture Notes in Computer Science, vol. 10394, pp. 273\u2013287. Springer, (2017). https:\/\/doi.org\/10.1007\/978-3-319-64701-2_20","DOI":"10.1007\/978-3-319-64701-2_20"},{"issue":"11","key":"388_CR69","doi-asserted-by":"publisher","first-page":"3711","DOI":"10.3390\/app10113711","volume":"10","author":"S An","year":"2020","unstructured":"An, S., Seo, S.C.: Highly efficient implementation of block ciphers on graphic processing units for massively large data. Appl. Sci. 10(11), 3711 (2020). https:\/\/doi.org\/10.3390\/app10113711","journal-title":"Appl. Sci."},{"key":"388_CR70","doi-asserted-by":"publisher","unstructured":"Moh\u2019d, A., Jararweh, Y., Tawalbeh, L.A.: AES-512: 512-bit advanced encryption standard algorithm design and evaluation. In: 7th International Conference on Information Assurance and Security, IAS 2011, Melacca, Malaysia, December 5-8, 2011, pp. 292\u2013297. IEEE, (2011). https:\/\/doi.org\/10.1109\/ISIAS.2011.6122835","DOI":"10.1109\/ISIAS.2011.6122835"},{"key":"388_CR71","doi-asserted-by":"publisher","unstructured":"Harb, S., Ahmad, M.O., Swamy, M.N.S.: A high-speed fpga implementation of aes for large scale embedded systems and its applications. In: 2022 13th International Conference on Information and Communication Systems (ICICS), pp. 59\u201364 (2022). https:\/\/doi.org\/10.1109\/ICICS55353.2022.9811140","DOI":"10.1109\/ICICS55353.2022.9811140"},{"issue":"6 Part B","key":"388_CR72","doi-asserted-by":"publisher","first-page":"3878","DOI":"10.1016\/J.JKSUCI.2020.08.005","volume":"34","author":"K Kumar","year":"2022","unstructured":"Kumar, K., Ramkumar, K.R., Kaur, A.: A lightweight AES algorithm implementation for encrypting voice messages using field programmable gate arrays. J. King Saud Univ. Comput. Inf. Sci. 34(6 Part B), 3878\u20133885 (2022). https:\/\/doi.org\/10.1016\/J.JKSUCI.2020.08.005","journal-title":"J. King Saud Univ. Comput. Inf. Sci."},{"key":"388_CR73","doi-asserted-by":"crossref","unstructured":"Daemen, J., Rijmen, V.: The Design of Rijndael: AES - The Advanced Encryption Standard (Information Security and Cryptography), 1st edn. Springer, (2002)","DOI":"10.1007\/978-3-662-04722-4_1"},{"key":"388_CR74","unstructured":"Standards, N.I., (NIST), T.: Pre-Draft Call for Comments on the GCM and GMAC Block Cipher Modes of Operation. https:\/\/csrc.nist.gov\/News\/2025\/proposal-to-revise-sp-800-38b-and-sp-800-38c. Accessed: 2025-04-26 (2025)"},{"key":"388_CR75","unstructured":"Standards, N.I., (NIST), T.: Decision to Revise SP 800-38B, \u201cCMAC\u201d and SP 800-38C, \u201cCCM\u201d. https:\/\/csrc.nist.gov\/News\/2025\/decision-to-revise-sp-800-38b-and-38c. Accessed: 2025-04-26 (2025)"}],"container-title":["Journal of Cryptographic Engineering"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s13389-025-00388-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s13389-025-00388-2","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s13389-025-00388-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,16]],"date-time":"2026-05-16T14:13:45Z","timestamp":1778940825000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s13389-025-00388-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1,4]]},"references-count":75,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2026,4]]}},"alternative-id":["388"],"URL":"https:\/\/doi.org\/10.1007\/s13389-025-00388-2","relation":{"has-preprint":[{"id-type":"doi","id":"10.21203\/rs.3.rs-6941414\/v1","asserted-by":"object"}]},"ISSN":["2190-8508","2190-8516"],"issn-type":[{"value":"2190-8508","type":"print"},{"value":"2190-8516","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,1,4]]},"assertion":[{"value":"20 June 2025","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"5 December 2025","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"4 January 2026","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare no competing interests.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Competing interests"}}],"article-number":"1"}}