{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T15:05:58Z","timestamp":1773414358971,"version":"3.50.1"},"reference-count":59,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2020,11,10]],"date-time":"2020-11-10T00:00:00Z","timestamp":1604966400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,11,10]],"date-time":"2020-11-10T00:00:00Z","timestamp":1604966400000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100001381","name":"National Research Foundation Singapore","doi-asserted-by":"publisher","award":["NRF2018NCR-NCR002-0001"],"award-info":[{"award-number":["NRF2018NCR-NCR002-0001"]}],"id":[{"id":"10.13039\/501100001381","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Hardw Syst Secur"],"published-print":{"date-parts":[[2020,12]]},"DOI":"10.1007\/s41635-020-00108-8","type":"journal-article","created":{"date-parts":[[2020,11,10]],"date-time":"2020-11-10T05:15:24Z","timestamp":1604985324000},"page":"329-342","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":12,"title":["Towards Designing a Secure RISC-V System-on-Chip: ITUS"],"prefix":"10.1007","volume":"4","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8363-2852","authenticated-orcid":false,"given":"Vinay B. Y.","family":"Kumar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suman","family":"Deb","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Naina","family":"Gupta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shivam","family":"Bhasin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jawad","family":"Haj-Yahya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anupam","family":"Chattopadhyay","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Avi","family":"Mendelson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2020,11,10]]},"reference":[{"key":"108_CR1","doi-asserted-by":"crossref","unstructured":"Kim Y, Daly R, Kim J, Lee JH, Lee D, Wilkerson C, Lai K, Mutlu O (2014) Flipping bits in memory without accessing them: an experimental study of dram disturbance errors. In: Proceeding of the 41st Annual International Symposium on Computer Architecuture, ser. ISCA \u201914. IEEE Press, Piscataway, pp 361\u2013372","DOI":"10.1145\/2678373.2665726"},{"key":"108_CR2","unstructured":"Lipp M, Schwarz M, Gruss D, Prescher T, Haas W, Fogh A, Horn J, Mangard S, Kocher P, Genkin D, Yarom Y, Hamburg M (2018) Meltdown: reading kernel memory from user space. In: 27th USENIX Security Symposium (USENIX Security 18). Baltimore, MD: USENIX Association, pp 973\u2013990"},{"key":"108_CR3","unstructured":"Van Bulck J, Minkin M, Weisse O, Genkin D, Kasikci B, Piessens F, Silberstein M, Wenisch TF, Yarom Y, Strackx R Foreshadow: extracting the keys to the Intel SGX kingdom with transient out-of-order execution. In: Proceedings of the 27th USENIX Security Symposium. USENIX Association, August 2018, see also technical report Foreshadow-NG"},{"key":"108_CR4","doi-asserted-by":"crossref","unstructured":"Canella C, Pudukotai Dinakarrao SM, Gruss D, Khasawneh KN (2020) Evolution of defenses against transient-execution attacks. In: Proceedings of the 2020 on Great Lakes Symposium on VLSI, pp 169\u2013174","DOI":"10.1145\/3386263.3407584"},{"key":"108_CR5","doi-asserted-by":"publisher","unstructured":"Jang Y, Lee S, Kim T (2016) Breaking kernel address space layout randomization with intel tsx. In: Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, ser. CCS \u201916. ACM, New York, pp 380\u2013392. [Online]. Available: https:\/\/doi.org\/10.1145\/2976749.2978321","DOI":"10.1145\/2976749.2978321"},{"key":"108_CR6","unstructured":"McIlroy R, Sevc\u00edk J, Tebbi T, Titzer BL, Verwaest T (2019) Spectre is here to stay: an analysis of side-channels and speculative execution, CoRR, [Online]. Available: arXiv:1902.05178"},{"key":"108_CR7","unstructured":"Ravi P, Najm Z, Bhasin S, Khairallah M, Gupta SS, Chattopadhyay A (2019) Security is an architectural design constraint, Microprocessors and microsystems, vol 68, pp 17\u201327, [Online]. Available: http:\/\/www.sciencedirect.com\/science\/article\/pii\/S0141933118302229"},{"key":"108_CR8","doi-asserted-by":"crossref","unstructured":"Knechtel J, Kavun EB, Regazzoni F, Heuser A, Chattopadhyay A, Mukhopadhyay D, Fei Y, Belenky Y, Levi I, G\u00fcneysu T, Schaumont P, Polian I (2020) Towards secure composition of integrated circuits and electronic systems: on the role of eda","DOI":"10.23919\/DATE48585.2020.9116483"},{"key":"108_CR9","doi-asserted-by":"crossref","unstructured":"Suh GE, Clarke D, Gassend B, Van Dijk M, Devadas S (2003) Aegis: architecture for tamper-evident and tamper-resistant processing. In: Proceedings of the 17th annual international conference on Supercomputing. ACM, pp 160\u2013171","DOI":"10.1145\/782814.782838"},{"key":"108_CR10","unstructured":"Costan V, Lebedev I, Devadas S (2016) Sanctum: minimal hardware extensions for strong software isolation. In: USENIX Security Symposium, pp 857\u2013874"},{"key":"108_CR11","doi-asserted-by":"crossref","unstructured":"Lee D, Kohlbrenner D, Shinde S, Asanovic K, Song D (2020) Keystone: an open framework for architecting trusted execution environments. In: Proceedings of the Fifteenth European Conference on Computer Systems, ser. EuroSys \u201920","DOI":"10.1145\/3342195.3387532"},{"key":"108_CR12","doi-asserted-by":"crossref","unstructured":"Weiser S, Werner M, Brasser F, Malenko M, Mangard S, Sadeghi A-R (2019) Timber-v: Tag-isolated memory bringing fine-grained enclaves to risc-v. In: Proceedings 2019 - Network and Distributed System Security Symposium (NDSS). Internet Society","DOI":"10.14722\/ndss.2019.23068"},{"key":"108_CR13","doi-asserted-by":"publisher","unstructured":"Menon A, Murugan S, Rebeiro C, Gala N, Veezhinathan K (2017) Shakti-t: a risc-v processor with light weight security extensions. In: Proceedings of the Hardware and Architectural Support for Security and Privacy, ser. HASP \u201917. Association for Computing Machinery, New York. [Online]. Available: https:\/\/doi.org\/10.1145\/3092627.3092629","DOI":"10.1145\/3092627.3092629"},{"key":"108_CR14","doi-asserted-by":"crossref","unstructured":"Kumar VBY, Chattopadhyay A, Haj-Yahya J, Mendelson A (2019) Itus: a secure risc-v system-on-chip. In: 2019 32nd IEEE International System-on-Chip Conference (SOCC), p 418\u2013423","DOI":"10.1109\/SOCC46988.2019.1570564307"},{"key":"108_CR15","doi-asserted-by":"crossref","unstructured":"Haj-Yahya J, Wong MM, Pudi V, Bhasin S, Chattopadhyay A (2019) Lightweight secure-boot architecture for risc-v system-on-chip. In: 20th International Symposium on Quality Electronic Design (ISQED), pp 216\u2013223","DOI":"10.1109\/ISQED.2019.8697657"},{"key":"108_CR16","doi-asserted-by":"crossref","unstructured":"Kumar VBY, Gupta N, Chattopadhyay A, Kasper M, Krau\u00df C, Niederhagen R (2020) Post-quantum secure boot. In: Design, Automation & Test in Europe Conference & Exhibition. IEEE, Grenoble","DOI":"10.23919\/DATE48585.2020.9116252"},{"key":"108_CR17","doi-asserted-by":"crossref","unstructured":"Srinivasu B, Pudi V, Chattopadhyay A, Lam K (2018) CoLPUF : a novel configurable LFSR-based PUF. In: APCCAS. IEEE, pp 358\u2013361","DOI":"10.1109\/APCCAS.2018.8605643"},{"key":"108_CR18","doi-asserted-by":"publisher","unstructured":"Wong MM, Haj-Yahya J, Chattopadhyay A (2018) Smarts: Secure memory assurance of risc-v trusted soc. In: Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, ser. HASP \u201918. ACM, New York, pp 6:1\u20136:8. [Online]. Available: https:\/\/doi.org\/10.1145\/3214292.3214298","DOI":"10.1145\/3214292.3214298"},{"key":"108_CR19","unstructured":"Lipp M, Schwarz M, Gruss D, Prescher T, Haas W, Mangard S, Kocher P, Genkin D, Yarom Y, Hamburg M (2018) Meltdown, arXiv:1801.01207"},{"key":"108_CR20","unstructured":"Kocher P, Genkin D, Gruss D, Haas W, Hamburg M, Lipp M, Mangard S, Prescher T, Schwarz M, Yarom Y (2018) Spectre attacks: exploiting speculative execution, arXiv preprint:1801.01203"},{"key":"108_CR21","doi-asserted-by":"crossref","unstructured":"Bar-El H, Choukri H, Naccache D, Tunstall M, Whelan C (2006) The sorcerer\u2019s apprentice guide to fault attacks. Proc IEEE 94(2):370\u2013382","DOI":"10.1109\/JPROC.2005.862424"},{"key":"108_CR22","doi-asserted-by":"crossref","unstructured":"Murdock K, Oswald D, Garcia FD, Van Bulck J, Gruss D, Piessens F (2020) Plundervolt: software-based fault injection attacks against intel sgx. In: 2020 IEEE Symposium on Security and Privacy (SP)","DOI":"10.1109\/SP40000.2020.00057"},{"key":"108_CR23","doi-asserted-by":"crossref","unstructured":"Kocher P, Jaffe J, Jun B (1999) Differential power analysis. In: Annual International Cryptology Conference. Springer, pp 388\u2013397","DOI":"10.1007\/3-540-48405-1_25"},{"key":"108_CR24","unstructured":"Group TC (2011) TPM main specification level 2 version 1.2, revision 116"},{"key":"108_CR25","doi-asserted-by":"crossref","unstructured":"Ravi P, Bhasin S, Breier J, Chattopadhyay A (2018) Ppap and ippap: Pll-based protection against physical attacks. In: 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp 620\u2013625","DOI":"10.1109\/ISVLSI.2018.00118"},{"key":"108_CR26","unstructured":"Gupta N, Jati A, Chattopadhyay A, Sanadhya SK, Chang D (2017) Threshold implementations of gift: a trade-off analysis, Cryptology ePrint Archive, Report 2017\/1040, https:\/\/eprint.iacr.org\/2017\/1040"},{"key":"108_CR27","unstructured":"Genkin D, Shamir A, Tromer E (2013) Rsa key extraction via low-bandwidth acoustic cryptanalysis, Cryptology ePrint Archive, Report 2013\/857, https:\/\/eprint.iacr.org\/2013\/857"},{"key":"108_CR28","unstructured":"Bhattacharya S, Mukhopadhyay D (2016) Curious case of rowhammer: flipping secret exponent bits using timing analysis, Cryptology ePrint Archive, Report 2016\/618, https:\/\/eprint.iacr.org\/2016\/618"},{"key":"108_CR29","unstructured":"Niederhagen R et al Industrial use cases and requirements for the deployment of post-quantum cryptography, volume wp.1, Fraunhofer Institute for Secure Information Technology, Technical Report. [Online]. Available: https:\/\/quantumrisc.org\/results\/quantumrisc-wp1-report.pdf"},{"key":"108_CR30","doi-asserted-by":"crossref","unstructured":"Fritzmann T, Sharif U, M\u00fcller-Gritschneder D, Reinbrecht C, Schlichtmann U, Sepulveda J (2019) Towards reliable and secure post-quantum co-processors based on risc-v. In: 2019 Design, Automation Test in Europe Conference Exhibition (DATE), pp 1148\u20131153","DOI":"10.23919\/DATE.2019.8715173"},{"key":"108_CR31","doi-asserted-by":"publisher","unstructured":"Gassend B, Clarke D, van Dijk M, Devadas S (2002) Silicon physical random functions. In: Proceedings of the 9th ACM Conference on Computer and Communications Security, ser. CCS \u201902. ACM, New York, pp 148\u2013160. [Online]. Available: https:\/\/doi.org\/10.1145\/586110.586132","DOI":"10.1145\/586110.586132"},{"key":"108_CR32","unstructured":"Szefer J (2016) Survey of microarchitectural side and covert channels, attacks, and defenses, Cryptology ePrint Archive, Report 2016\/479, https:\/\/eprint.iacr.org\/2016\/479"},{"key":"108_CR33","unstructured":"Bourgeat T, Lebedev I, Wright A, Zhang S (2018) Arvind, and S. Devadas, MI6: secure enclaves in a speculative out-of-order processor, CoRR, [Online]. Available: arXiv:1812.09822"},{"key":"108_CR34","doi-asserted-by":"crossref","unstructured":"Austin TM (1999) Diva: a reliable substrate for deep submicron microarchitecture design. In: Proceedings of the 32nd Annual ACM\/IEEE International Symposium on Microarchitecture, ser. MICRO 32. IEEE Computer Society, USA, p 196\u2013207","DOI":"10.1109\/MICRO.1999.809458"},{"key":"108_CR35","doi-asserted-by":"crossref","unstructured":"Zhang H, Ghosh S, Fix J, Apostolakis S, Beard SR, Nagendra NP, Oh T, August DI (2019) Architectural support for containment-based security. In: Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS \u201919. Association for Computing Machinery, New York, pp 361\u2013377","DOI":"10.1145\/3297858.3304020"},{"key":"108_CR36","doi-asserted-by":"crossref","unstructured":"Jauernig P, Sadeghi A, Stapf E (2020) Trusted execution environments: properties, applications, and challenges. IEEE Secur Privacy 18(2):56\u201360","DOI":"10.1109\/MSEC.2019.2947124"},{"key":"108_CR37","doi-asserted-by":"crossref","unstructured":"Zhang S, Wright A, Bourgeat T (2019) Composable building blocks to open up processor design. IEEE Micro 39(3):47\u201355, https:\/\/github.com\/csail-csg\/riscy-OOO","DOI":"10.1109\/MM.2019.2910012"},{"key":"108_CR38","doi-asserted-by":"crossref","unstructured":"Sau S, Haj-Yahya J, Wong MM, Lam KY, Chattopadhyay A (2017) Survey of secure processors. In: 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp 253\u2013260","DOI":"10.1109\/SAMOS.2017.8344637"},{"key":"108_CR39","unstructured":"Sau S (2009) SHE: secure hardware extension version 1.1"},{"key":"108_CR40","unstructured":"Lebedev I, Hogan K, Devadas S (2018) Secure boot and remote attestation in the sanctum processor, Cryptology ePrint Archive, Report 2018\/427, https:\/\/eprint.iacr.org\/2018\/427"},{"key":"108_CR41","unstructured":"Timmers N, Spruyt A (2016) Bypassing secure boot using fault injection, Blackhat Europe 2016"},{"key":"108_CR42","unstructured":"de Haas J (2013) 20 ways past secure boot, Hack in the Box Security Conference"},{"key":"108_CR43","doi-asserted-by":"crossref","unstructured":"Wong MM, Haj-Yahya J, Sau S, Chattopadhyay A (2018) A new high throughput and area efficient sha-3 implementation. In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp 1\u20135","DOI":"10.1109\/ISCAS.2018.8351649"},{"key":"108_CR44","doi-asserted-by":"crossref","unstructured":"Wold K, Tan CH (2008) Analysis and enhancement of random number generator in fpga based on oscillator rings. In: 2008 International Conference on Reconfigurable Computing and FPGAs, pp 385\u2013390","DOI":"10.1109\/ReConFig.2008.17"},{"key":"108_CR45","doi-asserted-by":"crossref","unstructured":"Vermeulen B, Goossens K (2014) Debugging systems-on-chip: communication-centric and abstraction-based techniques. Springer","DOI":"10.1007\/978-3-319-06242-6"},{"key":"108_CR46","unstructured":"Orme W (2008) Debug and trace for multicore socs, ARM White paper"},{"key":"108_CR47","doi-asserted-by":"crossref","unstructured":"Rosenfeld K, Karri R (2010) Attacks and defenses for jtag. IEEE Des Test Comput 27(1):36\u201347","DOI":"10.1109\/MDT.2010.9"},{"key":"108_CR48","doi-asserted-by":"crossref","unstructured":"Yang B, Wu K, Karri R (2004) Scan based side channel attack on dedicated hardware implementations of data encryption standard. In: 2004 International Conferce on Test. IEEE, pp 339\u2013344","DOI":"10.1109\/TEST.2004.1386969"},{"key":"108_CR49","unstructured":"Chiu G-M, Li JC-M (2010) A secure test wrapper design against internal and boundary scan attacks for embedded cores. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(1):126\u2013134"},{"key":"108_CR50","unstructured":"Pierce L, Tragoudas S (2012) Enhanced secure architecture for joint action test group systems. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(7):1342\u20131345"},{"key":"108_CR51","doi-asserted-by":"crossref","unstructured":"Pierce L (2011) Multi-level secure jtag architecture. In: 2011 IEEE 17th International On-Line Testing Symposium. IEEE, pp 208\u2013209","DOI":"10.1109\/IOLTS.2011.5993845"},{"key":"108_CR52","doi-asserted-by":"crossref","unstructured":"Das A, Da Rolt J, Ghosh S, Seys S, Dupuis S, Di Natale G, Flottes M-L, Rouzeyre B, Verbauwhede I (2013) Secure jtag implementation using schnorr protocol. J Electron Test 29(2):193\u2013209","DOI":"10.1007\/s10836-013-5369-9"},{"key":"108_CR53","doi-asserted-by":"crossref","unstructured":"Kocher P, Horn J, Fogh A, Genkin D, Gruss D, Haas W, Hamburg M, Lipp M, Mangard S, Prescher T, Schwarz M, Yarom Y (2019) Spectre attacks: exploiting speculative execution. In: 2019 IEEE Symposium on Security and Privacy (SP), pp 1\u201319","DOI":"10.1109\/SP.2019.00002"},{"key":"108_CR54","unstructured":"Mcilroy R, Sevcik J, Tebbi T, Titzer BL, Verwaest T (2019) Spectre is here to stay: an analysis of side-channels and speculative execution"},{"key":"108_CR55","unstructured":"Maisuradze G, Rossow C (2018) Speculose: analyzing the security implications of speculative execution in cpus"},{"key":"108_CR56","doi-asserted-by":"crossref","unstructured":"Ge Q, Yarom Y, Cock D, Heiser G (2018) A survey of microarchitectural timing attacks and countermeasures on contemporary hardware. J Cryptogr Eng 8(1):1\u201327","DOI":"10.1007\/s13389-016-0141-6"},{"key":"108_CR57","doi-asserted-by":"crossref","unstructured":"Gueron S (2009) Intel\u2019s new aes instructions for enhanced performance and security. In: Fast software encryption, Dunkelman, O, Ed. Springer, Berlin, pp 51\u201366","DOI":"10.1007\/978-3-642-03317-9_4"},{"key":"108_CR58","doi-asserted-by":"crossref","unstructured":"Martin R, Demme J, Sethumadhavan S (2012) Timewarp: rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks. In: 2012 39th Annual International Symposium on Computer Architecture (ISCA). IEEE, pp 118\u2013129","DOI":"10.1109\/ISCA.2012.6237011"},{"key":"108_CR59","doi-asserted-by":"crossref","unstructured":"Yan M, Choi J, Skarlatos D, Morrison A, Fletcher CW, Torrellas J (2018) Invisispec: making speculative execution invisible in the cache hierarchy. In: Proceedings of the 51st Annual IEEE\/ACM International Symposium on Microarchitecture, ser. MICRO-51. IEEE Press, Piscataway, pp 428\u2013441","DOI":"10.1109\/MICRO.2018.00042"}],"container-title":["Journal of Hardware and Systems Security"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s41635-020-00108-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s41635-020-00108-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s41635-020-00108-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,27]],"date-time":"2022-11-27T12:34:19Z","timestamp":1669552459000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s41635-020-00108-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,10]]},"references-count":59,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2020,12]]}},"alternative-id":["108"],"URL":"https:\/\/doi.org\/10.1007\/s41635-020-00108-8","relation":{},"ISSN":["2509-3428","2509-3436"],"issn-type":[{"value":"2509-3428","type":"print"},{"value":"2509-3436","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,11,10]]},"assertion":[{"value":"16 June 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 October 2020","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"10 November 2020","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}