{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T20:51:35Z","timestamp":1790887895907,"version":"4.1.0"},"reference-count":29,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["CCF Trans. HPC"],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1007\/s42514-019-00002-y","type":"journal-article","created":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T15:04:46Z","timestamp":1554131086000},"page":"3-13","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":23,"title":["The international race towards Exascale in Europe"],"prefix":"10.1007","volume":"1","author":[{"given":"Fabrizio","family":"Gagliardi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Miquel","family":"Moreto","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0214-9904","authenticated-orcid":false,"given":"Mauro","family":"Olivieri","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2917-2482","authenticated-orcid":false,"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2019,4,1]]},"reference":[{"key":"2_CR1","unstructured":"Asanovic, K. (1998) Vector microprocessors. Ph.D. thesis, (1998)"},{"issue":"8","key":"2_CR2","doi-asserted-by":"publisher","first-page":"746","DOI":"10.1109\/TC.1968.229158","volume":"C-17","author":"GH Barnes","year":"1968","unstructured":"Barnes, G.H., Brown, R.M., Kato, M., Kuck, D.J., Slotnick, D.L., Stokes, R.A.: The ILLIAC IV Computer. IEEE Trans. Comput. C-17(8), 746\u2013757 (1968)","journal-title":"IEEE Trans. Comput."},{"key":"2_CR3","unstructured":"Callahan D, Dongarra J, Levine D (1988) Vectorizing compilers: a test suite and results. Proceedings of the 1988 ACM\/IEEE Conference on Supercomputing, pp. 98\u2013105, November 12\u201317, 1988, Orlando, Florida, United States.SC (1988)"},{"key":"2_CR4","doi-asserted-by":"publisher","first-page":"89","DOI":"10.1007\/978-3-319-93082-4_12","volume":"512","author":"A Cheikh","year":"2019","unstructured":"Cheikh, A., Cerutti, G., Mastrandrea, A., Menichelli, F., Olivieri, M.: The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. Lecture Notes Elect. Eng. 512, 89\u201397 (2019)","journal-title":"Lecture Notes Elect. Eng."},{"key":"2_CR5","unstructured":"Cray Research: Cray X-MP Series Model 48 Mainframe Reference Manual. (1984)"},{"issue":"3","key":"2_CR8","doi-asserted-by":"publisher","first-page":"122","DOI":"10.1109\/MM.2012.17","volume":"32","author":"H Esmaeilzadeh","year":"2012","unstructured":"Esmaeilzadeh, H., Blem, E., Amant, R.S., Amant, R.S., Sankaralingam, K., Burger, D.: Dark silicon and the end of multicore scaling. IEEE Micro 32(3), 122\u2013134 (2012)","journal-title":"IEEE Micro"},{"key":"2_CR9","unstructured":"Espasa, R., Valero, M., Smith, J. E.: Vector architectures: past, present and future. In Proceedings of the 12th International Conference on Supercomputing (ICS), pp. 425\u2013432, (1998)"},{"key":"2_CR6","unstructured":"European Open Science Cloud (EOSC): \n                    https:\/\/ec.europa.eu\/research\/openscience\/index.cfm?pg=open-science-cloud\n                    \n                  . (2018)"},{"key":"2_CR7","unstructured":"European Processor Initiative (2018): Consortium to develop Europe\u2019s microprocessors for future supercomputers. (\n                    https:\/\/ec.europa.eu\/digital-single-market\/en\/news\/european-processor-initiative-consortium-develop-europes-microprocessors-future-supercomputers\n                    \n                  ). (2018)"},{"key":"2_CR10","doi-asserted-by":"crossref","unstructured":"Flamand, E., Rossi, D., Conti, F., Loi, I., Pullini, A., Rotenberg, F., Benini, L.: GAP-8: a RISC-V SoC for AI at the edge of the IoT. In: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. IEEE, Piscataway (2018)","DOI":"10.1109\/ASAP.2018.8445101"},{"issue":"10","key":"2_CR11","doi-asserted-by":"publisher","first-page":"2700","DOI":"10.1109\/TVLSI.2017.2654506","volume":"25","author":"M Gautschi","year":"2017","unstructured":"Gautschi, M., Schiavone, P.D., Traber, A., Loi, I., Pullini, A., Rossi, D., Flamand, E., G\u00fcrkaynak, F.K., Benini, L.: Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(10), 2700\u20132713 (2017)","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"2_CR12","unstructured":"Hintz, R.G., Tate, D.P.: Control Data STAR-100 processor design. In Proc. COMPCON, pp. 1\u20134. IEEE, Piscataway (1972)"},{"issue":"7","key":"2_CR13","doi-asserted-by":"publisher","first-page":"1863","DOI":"10.1109\/JSSC.2017.2690859","volume":"52","author":"B Keller","year":"2017","unstructured":"Keller, B., Cochet, M., Zimmer, B., Kwak, J., Puggelli, A., Lee, Y., Blagojevi\u0107, M., Bailey, S., Chiu, P.-F., Dabbelt, P., Schmidt, C., Alon, E., Asanovi\u0107, K., Nikoli\u0107, B.: A RISC-V processor SoC with integrated power management at submicrosecond timescales in 28\u00a0nm FD-SOI. IEEE J. Solid-State Circuits 52(7), 1863\u20131875 (2017)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2_CR14","unstructured":"Lee, Y. et al.: A 45\u00a0nm 1.3\u00a0GHz 16.7 double-precision GFLOPS\/W RISC-V processor with vector accelerators. In: ESSCIRC 2014\u201440th European Solid State Circuits Conference (ESSCIRC), Venice Lido, pp. 199\u2013202, (2014)"},{"key":"2_CR15","doi-asserted-by":"crossref","unstructured":"Lee, Y., Zimmer, B., Waterman, A., Puggelli, A., Kwak, J., Jevtic, R., Keller, B., Bailey, S., Blagojevic, M., Chiu, P.-F., Cook, H., Avizienis, R., Richards, B., Alon, E., Nikolic, B., Asanovic, K.: Raven: A 28\u00a0nm RISC-V vector processor with integrated switched-capacitor DC\u2013DC converters and adaptive clocking, (2016). In: 2015 IEEE Hot Chips 27 Symposium, HCS (2015)","DOI":"10.1109\/HOTCHIPS.2015.7477469"},{"issue":"5","key":"2_CR16","doi-asserted-by":"publisher","first-page":"349","DOI":"10.1109\/TC.1982.1676013","volume":"C-31","author":"NR Lincoln","year":"1982","unstructured":"Lincoln, N.R.: Technology and design trade offs in the creation of a modern supercomputer. IEEE Trans. on Comput. C-31(5), 349\u2013362 (1982)","journal-title":"IEEE Trans. on Comput."},{"key":"2_CR17","doi-asserted-by":"crossref","unstructured":"Olivieri, M., Cheikh, A., Cerutti, G., Mastrandrea, A., Menichelli, F (2017) Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores. In: Proceedings\u20142017 1st New generation of CAS, NGCAS 2017, pp. 45\u201348 (2017)","DOI":"10.1109\/NGCAS.2017.61"},{"key":"2_CR18","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1016\/j.micpro.2018.05.007","volume":"61","author":"K Patsidis","year":"2018","unstructured":"Patsidis, K., Konstantinou, D., Nicopoulos, C., Dimitrakopoulos, G.: A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. Microprocess. Microsyst. 61, 1\u201310 (2018)","journal-title":"Microprocess. Microsyst."},{"key":"2_CR19","doi-asserted-by":"crossref","unstructured":"Patterson, D.: 50 years of computer architecture: from the mainframe CPU to the domain-specific tpu and the open RISC-V instruction set. In: Digest of Technical Papers\u2014IEEE International Solid-State Circuits Conference, 61, pp. 27\u201331 (2018)","DOI":"10.1109\/ISSCC.2018.8310168"},{"key":"2_CR20","doi-asserted-by":"crossref","unstructured":"Rajovic, N., Rico, A., Mantovani, F., Ruiz, D., Vilarrubi, J.O., Gomez, C., Backes, L., Nieto, D., Servat, H., Martorell, X., Labarta, J., Ayguad\u00e9, E., Adeniyi-Jones, C., Derradji S., Gloaguen, H., Lanucara, P., Sanna, N., M\u00e9haut, J.-F., Pouget, K., Videau, B., Boyer, E., Allalen, M., Auweter, A., Brayford, D., Tafani, D., Weinberg, V., Br\u00f6mmel, D., Halver, R., Meinke, J.H., Beivide, R., Benito, M., Vallejo, E., Valero, M., Ram\u00edrez, A.: The Mont-Blanc prototype: an alternative approach for HPC systems. In: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 444\u2013455, IEEE, Piscataway (2016)","DOI":"10.1109\/SC.2016.37"},{"key":"2_CR21","unstructured":"RISC-V Foundation home page. Online: \n                    http:\/\/riscv.org"},{"issue":"1","key":"2_CR22","doi-asserted-by":"publisher","first-page":"63","DOI":"10.1145\/359327.359336","volume":"21","author":"RM Russell","year":"1978","unstructured":"Russell, R.M.: The CRAY-1 computer system. Commun. ACM 21(1), 63\u201372 (1978)","journal-title":"Commun. ACM"},{"key":"2_CR23","unstructured":"Schiavone, P.D., Conti, F., Rossi, D., Gautschi, M., Pullini, A., Flamand, E., Benini, L.: Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for internet-of-things applications. In: 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, pp. 1\u20138 (2017)"},{"key":"2_CR24","unstructured":"The European declaration on High-Performance Computing (EuroHPC): \n                    https:\/\/ec.europa.eu\/digital-single-market\/en\/news\/european-declaration-high-performance-computing\n                    \n                  ). (2018)"},{"key":"2_CR25","unstructured":"The TOP500 List. Online: \n                    https:\/\/www.top500.org\/\n                    \n                  , June 2018"},{"key":"2_CR26","unstructured":"Watson, W.J.: The TI ASC: A highly modular and flexible super computer architecture. In Proceedings of the December 5\u20137, 1972, Fall Joint Computer Conference, Part I (AFIPS), pp. 221\u2013228, (1972)"},{"key":"2_CR27","doi-asserted-by":"crossref","unstructured":"Waterman, A., Lee, Y., Avizienis, R., Cook, H., Patterson, D., Asanovic, K.: The RISC-V instruction set. In: 2013 IEEE Hot Chips 25 Symposium, HCS (2016)","DOI":"10.1109\/HOTCHIPS.2013.7478332"},{"key":"2_CR28","unstructured":"Yoshida, T: Introduction of Fujitsu\u2019s HPC processor for the Post-K computer. In: Hot Chips. (2016)"},{"issue":"4","key":"2_CR29","doi-asserted-by":"publisher","first-page":"930","DOI":"10.1109\/JSSC.2016.2519386","volume":"51","author":"B Zimmer","year":"2016","unstructured":"Zimmer, B., Lee, Y., Puggelli, A., Kwak, J., Jevti\u0107, R., Keller, B., Bailey, S., Blagojevi\u0107, M., Chiu, P.-F., Le, H.-P., Chen, P.-H., Sutardja, N., Avizienis, R., Waterman, A., Richards, B., Flatresse, P., Alon, E., Asanovi\u0107, K., Nikoli\u0107, B.: A RISC-V vector processor with simultaneous-switching switched-CAPACITOR DC\u2013DC converters in 28\u00a0nm FDSOI. IEEE J. Solid-State Circuits 51(4), 930\u2013942 (2016)","journal-title":"IEEE J. Solid-State Circuits"}],"container-title":["CCF Transactions on High Performance Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s42514-019-00002-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s42514-019-00002-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s42514-019-00002-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,3,30]],"date-time":"2020-03-30T23:39:05Z","timestamp":1585611545000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s42514-019-00002-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4,1]]},"references-count":29,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2019,5]]}},"alternative-id":["2"],"URL":"https:\/\/doi.org\/10.1007\/s42514-019-00002-y","relation":{},"ISSN":["2524-4922","2524-4930"],"issn-type":[{"value":"2524-4922","type":"print"},{"value":"2524-4930","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,4,1]]},"assertion":[{"value":"4 January 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"18 February 2019","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"1 April 2019","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}