{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T23:42:14Z","timestamp":1740181334040,"version":"3.37.3"},"reference-count":101,"publisher":"Springer Science and Business Media LLC","issue":"3-4","license":[{"start":{"date-parts":[[2019,10,23]],"date-time":"2019-10-23T00:00:00Z","timestamp":1571788800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2019,10,23]],"date-time":"2019-10-23T00:00:00Z","timestamp":1571788800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["CCF Trans. HPC"],"published-print":{"date-parts":[[2019,12]]},"DOI":"10.1007\/s42514-019-00014-8","type":"journal-article","created":{"date-parts":[[2019,10,23]],"date-time":"2019-10-23T16:33:47Z","timestamp":1571848427000},"page":"196-208","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":11,"title":["ReBNN: in-situ acceleration of binarized neural networks in ReRAM using complementary resistive cell"],"prefix":"10.1007","volume":"1","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7450-2842","authenticated-orcid":false,"given":"Linghao","family":"Song","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"You","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuehai","family":"Qian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hai","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yiran","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,10,23]]},"reference":[{"key":"14_CR1","doi-asserted-by":"crossref","unstructured":"Akhlaghi, V., Yazdanbakhsh, A., Samadi, K., Gupta, R.K., Esmaeilzadeh, H.: Snapea: Predictive early activation for reducing computation in deep convolutional neural networks. In: 2018 ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), pp. 662\u2013673. IEEE (2018)","DOI":"10.1109\/ISCA.2018.00061"},{"issue":"7","key":"14_CR2","doi-asserted-by":"publisher","first-page":"075201","DOI":"10.1088\/0957-4484\/23\/7\/075201","volume":"23","author":"F Alibart","year":"2012","unstructured":"Alibart, F., Gao, L., Hoskins, B.D., Strukov, D.B.: High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology 23(7), 075201 (2012)","journal-title":"Nanotechnology"},{"key":"14_CR3","doi-asserted-by":"crossref","unstructured":"Andri, R., Cavigelli, L., Rossi, D., Benini, L.: Yodann: an ultra-low power convolutional neural network accelerator based on binary weights. In: 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 236\u2013241. IEEE (2016)","DOI":"10.1109\/ISVLSI.2016.111"},{"key":"14_CR4","doi-asserted-by":"publisher","first-page":"4308","DOI":"10.1038\/ncomms5308","volume":"5","author":"P Baldi","year":"2014","unstructured":"Baldi, P., Sadowski, P., Whiteson, D.: Searching for exotic particles in high-energy physics with deep learning. Nat. Commun. 5, 4308 (2014)","journal-title":"Nat. Commun."},{"issue":"3","key":"14_CR5","doi-asserted-by":"publisher","first-page":"878","DOI":"10.1109\/JSSC.2012.2230515","volume":"48","author":"Meng-Fan Chang","year":"2013","unstructured":"Chang, M.F., Sheu, S.S., Lin, K.F., Wu, C.W., Kuo, C.C., Chiu, P.F., Yang, Y.S., Chen, Y.S., Lee, H.Y., Lien, C.H., et al.: A high-speed 7.2-ns read-write random access 4-mb embedded resistive ram (ReRAM) macro using process-variation-tolerant current-mode read schemes. IEEE J. Solid State Circuits 48(3), 878\u2013891 (2012)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"14_CR12","doi-asserted-by":"crossref","unstructured":"Chen, T., Du, Z., Sun, N., Wang, J., Wu, C., Chen, Y., Temam, O.: Diannao: a small-footprint high-throughput accelerator for ubiquitous machine-learning. In: ACM Sigplan Notices, vol. 49, pp. 269\u2013284. ACM (2014a)","DOI":"10.1145\/2644865.2541967"},{"key":"14_CR13","doi-asserted-by":"crossref","unstructured":"Chen, Y., Luo, T., Liu, S., Zhang, S., He, L., Wang, J., Li, L., Chen, T., Xu, Z., Sun, N., et\u00a0al.: Dadiannao: a machine-learning supercomputer. In: Proceedings of the 47th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 609\u2013622. IEEE Computer Society (2014b)","DOI":"10.1109\/MICRO.2014.58"},{"issue":"1","key":"14_CR14","doi-asserted-by":"publisher","first-page":"127","DOI":"10.1109\/JSSC.2016.2616357","volume":"52","author":"YH Chen","year":"2016","unstructured":"Chen, Y.H., Krishna, T., Emer, J.S., Sze, V.: Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE J. Solid State Circuits 52(1), 127\u2013138 (2016)","journal-title":"IEEE J. Solid State Circuits"},{"key":"14_CR6","doi-asserted-by":"crossref","unstructured":"Chen, F., Li, H.: Emat: an efficient multi-task architecture for transfer learning using ReRAM. In: Proceedings of the International Conference on Computer-Aided Design, p. 33. ACM (2018a)","DOI":"10.1145\/3240765.3240805"},{"key":"14_CR7","doi-asserted-by":"crossref","unstructured":"Chen, F., Song, L., Chen, Y.: Regan: A pipelined ReRAM-based accelerator for generative adversarial networks. In: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 178\u2014183. IEEE (2018b)","DOI":"10.1109\/ASPDAC.2018.8297302"},{"issue":"12","key":"14_CR11","doi-asserted-by":"publisher","first-page":"3067","DOI":"10.1109\/TCAD.2018.2789723","volume":"37","author":"PY Chen","year":"2018","unstructured":"Chen, P.Y., Peng, X., Yu, S.: Neurosim: a circuit-level macro model for benchmarking neuro-inspired architectures in online learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12), 3067\u20133080 (2018c)","journal-title":"Comput. Aided Des. Integr. Circuits Syst"},{"key":"14_CR8","doi-asserted-by":"crossref","unstructured":"Chen, F., Song, L., Li, H.: Efficient process-in-memory architecture design for unsupervised GAN-based deep learning using ReRAM. In: Proceedings of the 2019 on Great Lakes Symposium on VLSI, pp. 423\u2013428. ACM (2019a)","DOI":"10.1145\/3299874.3319482"},{"key":"14_CR10","doi-asserted-by":"crossref","unstructured":"Chen, F., Song, L., Li, H.H., Chen, Y.: Zara: a novel zero-free dataflow accelerator for generative adversarial networks in 3d ReRAM. In: Proceedings of the 56th Annual Design Automation Conference 2019, p. 133. ACM (2019b)","DOI":"10.1145\/3316781.3317936"},{"key":"14_CR9","doi-asserted-by":"crossref","unstructured":"Chen, F., Song, L., Li, H., Chen, Y.: Parc: a processing-in-cam architecture for genomic long read pairwise alignment using ReRAM. In: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC). ACM (2020)","DOI":"10.1109\/ASP-DAC47756.2020.9045555"},{"key":"14_CR15","doi-asserted-by":"crossref","unstructured":"Cheng, M., Xia, L., Zhu, Z., Cai, Y., Xie, Y., Wang, Y., Yang, H.: Time: a training-in-memory architecture for memristor-based deep neural networks. In: Proceedings of the 54th Annual Design Automation Conference 2017, p.\u00a026. ACM (2017)","DOI":"10.1145\/3061639.3062326"},{"key":"14_CR16","unstructured":"Chetlur, S., Woolley, C., Vandermersch, P., Cohen, J., Tran, J., Catanzaro, B., Shelhamer, E.: CUDNN: efficient primitives for deep learning. \narXiv:1410.0759\n\n (2014)"},{"key":"14_CR17","doi-asserted-by":"crossref","unstructured":"Chi, P., Li, S., Xu, C., Zhang, T., Zhao, J., Liu, Y., Wang, Y., Xie, Y.: Prime: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In: ACM SIGARCH Computer Architecture News, vol.\u00a044, pp. 27\u201339. IEEE Press (2016)","DOI":"10.1145\/3007787.3001140"},{"issue":"141","key":"14_CR18","doi-asserted-by":"publisher","first-page":"20170387","DOI":"10.1098\/rsif.2017.0387","volume":"15","author":"T Ching","year":"2018","unstructured":"Ching, T., Himmelstein, D.S., Beaulieu-Jones, B.K., Kalinin, A.A., Do, B.T., Way, G.P., Ferrero, E., Agapow, P.M., Zietz, M., Hoffman, M.M., et al.: Opportunities and obstacles for deep learning in biology and medicine. J. R. Soc. Interface 15(141), 20170387 (2018)","journal-title":"J. R. Soc. Interface"},{"key":"14_CR19","unstructured":"Collobert, R., Kavukcuoglu, K., Farabet, C.: Torch7: a matlab-like environment for machine learning. Tech. rep. (2011)"},{"key":"14_CR20","doi-asserted-by":"crossref","unstructured":"Dai, G., Huang, T., Wang, Y., Yang, H., Wawrzynek, J.: Graphsar: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp. 120\u2013126. ACM (2019)","DOI":"10.1145\/3287624.3287637"},{"issue":"7","key":"14_CR21","doi-asserted-by":"publisher","first-page":"994","DOI":"10.1109\/TCAD.2012.2185930","volume":"31","author":"Xiangyu Dong","year":"2012","unstructured":"Dong, X., Xu, C., Xie, Y., Jouppi, N.P.: Nvsim: a circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7), 994\u20131007 (2012)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"3","key":"14_CR22","doi-asserted-by":"publisher","first-page":"92","DOI":"10.1145\/2872887.2750389","volume":"43","author":"Zidong Du","year":"2015","unstructured":"Du, Z., Fasthuber, R., Chen, T., Ienne, P., Li, L., Luo, T., Feng, X., Chen, Y., Temam, O.: Shidiannao: shifting vision processing closer to the sensor. In: ACM SIGARCH Computer Architecture News, vol. 43, pp. 92\u2013104. ACM (2015)","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"14_CR23","doi-asserted-by":"crossref","unstructured":"Esmaeilzadeh, H., Sampson, A., Ceze, L., Burger, D.: Neural acceleration for general-purpose approximate programs. In: Proceedings of the 2012 45th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 449\u2013460. IEEE Computer Society (2012)","DOI":"10.1109\/MICRO.2012.48"},{"key":"14_CR24","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1016\/j.cmpb.2018.04.005","volume":"161","author":"O Faust","year":"2018","unstructured":"Faust, O., Hagiwara, Y., Hong, T.J., Lih, O.S., Acharya, U.R.: Deep learning for healthcare applications based on physiological signals: a review. Comput. Methods Programs Biomed. 161, 1\u201313 (2018)","journal-title":"Comput. Methods Programs Biomed."},{"issue":"16","key":"14_CR25","doi-asserted-by":"publisher","first-page":"1291","DOI":"10.1002\/jcc.24764","volume":"38","author":"GB Goh","year":"2017","unstructured":"Goh, G.B., Hodas, N.O., Vishnu, A.: Deep learning for computational chemistry. J. Comput. Chem. 38(16), 1291\u20131307 (2017)","journal-title":"J. Comput. Chem."},{"key":"14_CR26","doi-asserted-by":"crossref","unstructured":"Guan, Y., Liang, H., Xu, N., Wang, W., Shi, S., Chen, X., Sun, G., Zhang, W., Cong, J.: FP-DNN: an automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates. In: 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 152\u2013159. IEEE (2017a)","DOI":"10.1109\/FCCM.2017.25"},{"key":"14_CR27","doi-asserted-by":"crossref","unstructured":"Guan, Y., Yuan, Z., Sun, G., Cong, J.: FPGA-based accelerator for long short-term memory recurrent neural networks. In: 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 629\u2013634. IEEE (2017b)","DOI":"10.1109\/ASPDAC.2017.7858394"},{"key":"14_CR28","unstructured":"Han, S., Kang, J., Mao, H., Hu, Y., Li, X., Li, Y., Xie, D., Luo, H., Yao, S., Wang, Y., et\u00a0al.: ESE: efficient speech recognition engine with sparse LSTM on FPGA. In: Proceedings of the 2017 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 75\u201384. ACM (2017)"},{"key":"14_CR29","doi-asserted-by":"crossref","unstructured":"Hu, M., Strachan, J.P., Li, Z., Grafals, E.M., Davila, N., Graves, C., Lam, S., Ge, N., Yang, J.J., Williams, R.S.: Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication. In: Proceedings of the 53rd annual design automation conference, p.\u00a019. ACM (2016)","DOI":"10.1145\/2897937.2898010"},{"key":"14_CR30","doi-asserted-by":"crossref","unstructured":"Huangfu, W., Li, S., Hu, X., Xie, Y.: Radar: a 3D-ReRAM based DNA alignment accelerator architecture. In: 2018 55th ACM\/ESDA\/IEEE Design Automation Conference (DAC), pp. 1\u20136. IEEE (2018)","DOI":"10.1109\/DAC.2018.8465882"},{"key":"14_CR31","unstructured":"Hubara, I., Courbariaux, M., Soudry, D., El-Yaniv, R., Bengio, Y.: Binarized neural networks. In: Advances in Neural Information Processing Systems, pp. 4107\u20134115 (2016)"},{"key":"14_CR35","doi-asserted-by":"crossref","unstructured":"Ji, Y., Zhang, Y., Li, S., Chi, P., Jiang, C., Qu, P., Xie, Y., Chen, W.: Neutrams: neural network transformation and co-design under neuromorphic hardware constraints. In: The 49th Annual IEEE\/ACM International Symposium on Microarchitecture, p.\u00a021. IEEE Press (2016)","DOI":"10.1109\/MICRO.2016.7783724"},{"key":"14_CR33","doi-asserted-by":"crossref","unstructured":"Ji, H., Song, L., Jiang, L., Li, H.H., Chen, Y.: ReCom: an efficient resistive accelerator for compressed deep neural networks. In: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 237\u2013240. IEEE (2018a)","DOI":"10.23919\/DATE.2018.8342009"},{"issue":"2","key":"14_CR34","doi-asserted-by":"publisher","first-page":"448","DOI":"10.1145\/3296957.3173205","volume":"53","author":"Yu Ji","year":"2018","unstructured":"Ji, Y., Zhang, Y., Chen, W., Xie, Y.: Bridge the gap between neural networks and neuromorphic hardware with a neural network compiler. In: ACM SIGPLAN Notices, vol.\u00a053, pp. 448\u2013460. ACM (2018b)","journal-title":"ACM SIGPLAN Notices"},{"key":"14_CR32","doi-asserted-by":"crossref","unstructured":"Ji, H., Jiang, L., Li, T., Jing, N., Ke, J., Liang, X.: HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp. 249\u2013254. ACM (2019)","DOI":"10.1145\/3287624.3287674"},{"key":"14_CR36","doi-asserted-by":"crossref","unstructured":"Jiang, L., Kim, M., Wen, W., Wang, D.: XNOR-pop: a processing-in-memory architecture for binary convolutional neural networks in wide-IO2 drams. In: 2017 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 1\u20136. IEEE (2017)","DOI":"10.1109\/ISLPED.2017.8009163"},{"key":"14_CR37","unstructured":"Jouppi, N.P., Young, C., Patil, N., Patterson, D., Agrawal, G., Bajwa, R., Bates, S., Bhatia, S., Boden, N., Borchers, A., et\u00a0al.: In-datacenter performance analysis of a tensor processing unit. In: 2017 ACM\/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), pp. 1\u201312. IEEE (2017)"},{"key":"14_CR38","doi-asserted-by":"crossref","unstructured":"Kim, D., Kung, J., Chai, S., Yalamanchili, S., Mukhopadhyay, S.: Neurocube: a programmable digital neuromorphic architecture with high-density 3D memory. In: 2016 ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), pp. 380\u2013392. IEEE (2016)","DOI":"10.1109\/ISCA.2016.41"},{"key":"14_CR39","unstructured":"Krizhevsky, A., Hinton, G.: Learning multiple layers of features from tiny images. Tech. rep, Citeseer (2009)"},{"key":"14_CR40","unstructured":"Krizhevsky, A., Sutskever, I., Hinton, G.E.: Imagenet classification with deep convolutional neural networks. In: Advances in neural information processing systems, pp. 1097\u20131105 (2012)"},{"issue":"38","key":"14_CR41","doi-asserted-by":"publisher","first-page":"382001","DOI":"10.1088\/0957-4484\/24\/38\/382001","volume":"24","author":"D Kuzum","year":"2013","unstructured":"Kuzum, D., Yu, S., Wong, H.P.: Synaptic electronics: materials, devices and applications. Nanotechnology 24(38), 382001 (2013)","journal-title":"Nanotechnology"},{"issue":"2","key":"14_CR42","doi-asserted-by":"publisher","first-page":"461","DOI":"10.1145\/3296957.3173176","volume":"53","author":"Hyoukjun Kwon","year":"2018","unstructured":"Kwon, H., Samajdar, A., Krishna, T.: MAERI: enabling flexible dataflow mapping over DNN accelerators via reconfigurable interconnects. In: ACM SIGPLAN Notices, vol.\u00a053, pp. 461\u2013475. ACM (2018)","journal-title":"ACM SIGPLAN Notices"},{"key":"14_CR43","unstructured":"LeCun, Y.: The mnist database of handwritten digits. \nhttp:\/\/yann.lecun.com\/exdb\/mnist\/\n\n (1998)"},{"issue":"7","key":"14_CR44","doi-asserted-by":"publisher","first-page":"964","DOI":"10.1109\/LED.2011.2148689","volume":"32","author":"D Lee","year":"2011","unstructured":"Lee, D., Lee, J., Jo, M., Park, J., Siddik, M., Hwang, H.: Noise-analysis-based model of filamentary switching ReRAM with $$\\text{ ZrO }_{x}\/\\text{ HfO }_{x}$$ stacks. IEEE Electron Device Lett. 32(7), 964\u2013966 (2011)","journal-title":"IEEE Electron Device Lett."},{"key":"14_CR46","doi-asserted-by":"crossref","unstructured":"Li, Y., Liu, Z., Xu, K., Yu, H., Ren, F.: A 7.663-tops 8.2-w energy-efficient FPGA accelerator for binary convolutional neural networks. In: FPGA, pp. 290\u2013291 (2017)","DOI":"10.1145\/3020078.3021786"},{"key":"14_CR45","doi-asserted-by":"crossref","unstructured":"Li, B., Song, L., Chen, F., Qian, X., Chen, Y., Li, H.H.: ReRAM-based accelerator for deep learning. In: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 815\u2013820. IEEE (2018)","DOI":"10.23919\/DATE.2018.8342118"},{"key":"14_CR47","doi-asserted-by":"crossref","unstructured":"Lin, J., Li, S., Hu, X., Deng, L., Xie, Y.: CNNWIRE: Boosting convolutional neural network with winograd on ReRAM based accelerators. In: Proceedings of the 2019 on Great Lakes Symposium on VLSI, pp. 283\u2013286. ACM (2019a)","DOI":"10.1145\/3299874.3318018"},{"key":"14_CR48","doi-asserted-by":"crossref","unstructured":"Lin, J., Zhu, Z., Wang, Y., Xie, Y.: Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp. 639\u2013644. ACM (2019b)","DOI":"10.1145\/3287624.3287715"},{"key":"14_CR55","doi-asserted-by":"crossref","unstructured":"Liu, X., Mao, M., Liu, B., Li, H., Chen, Y., Li, B., Wang, Y., Jiang, H., Barnell, M., Wu, Q., et\u00a0al.: Reno: a high-efficient reconfigurable neuromorphic computing accelerator design. In: 2015 52nd ACM\/EDAC\/IEEE Design Automation Conference (DAC), pp. 1\u20136. IEEE (2015)","DOI":"10.1145\/2744769.2744900"},{"key":"14_CR54","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1007\/978-3-319-46448-0_2","volume-title":"Computer vision \u2013 ECCV 2016","author":"W Liu","year":"2016","unstructured":"Liu, W., Anguelov, D., Erhan, D., Szegedy, C., Reed, S., Fu, C.Y., Berg, A.C.: SSD: single shot multibox detector. In: Leibe B, Matas J, Sebe N, Welling M (eds) Computer vision \u2013 ECCV 2016. Springer, Cham, pp. 21\u201337 (2016)"},{"key":"14_CR49","doi-asserted-by":"crossref","unstructured":"Liu, M., Xia, L., Wang, Y., Chakrabarty, K.: Design of fault-tolerant neuromorphic computing systems. In: 2018 IEEE 23rd European Test Symposium (ETS), pp. 1\u20139. IEEE (2018a)","DOI":"10.1109\/ETS.2018.8400693"},{"key":"14_CR50","doi-asserted-by":"crossref","unstructured":"Liu, M., Xia, L., Wang, Y., Chakrabarty, K.: Fault tolerance for RRAM-based matrix operations. In: 2018 IEEE International Test Conference (ITC), pp. 1\u201310. IEEE (2018b)","DOI":"10.1109\/TEST.2018.8624687"},{"key":"14_CR52","doi-asserted-by":"crossref","unstructured":"Liu, R., Peng, X., Sun, X., Khwa, W.S., Si, X., Chen, J.J., Li, J.F., Chang, M.F., Yu, S.: Parallelizing SRAM arrays with customized bit-cell for binary neural networks. In: Proceedings of the 55th Annual Design Automation Conference, p.\u00a021. ACM (2018c)","DOI":"10.1145\/3195970.3196089"},{"key":"14_CR56","unstructured":"Liu, X., Yang, H., Liu, Z., Song, L., Li, H., Chen, Y.: DPATCH: an adversarial patch attack on object detectors. \narXiv:1806.02299\n\n (2018d)"},{"key":"14_CR51","doi-asserted-by":"crossref","unstructured":"Liu, M., Xia, L., Wang, Y., Chakrabarty, K.: Fault tolerance in neuromorphic computing systems. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp. 216\u2013223. ACM (2019a)","DOI":"10.1145\/3287624.3288743"},{"key":"14_CR53","doi-asserted-by":"publisher","unstructured":"Liu, T., Wen, W., Jiang, L., Wang, Y., Yang, C., Quan, G.: A fault-tolerant neural network architecture. In: Proceedings of the 56th Annual Design Automation Conference 2019, DAC \u201919, pp. 55:1\u201355:6. ACM, New York (2019b). \nhttps:\/\/doi.org\/10.1145\/3316781.3317742","DOI":"10.1145\/3316781.3317742"},{"key":"14_CR57","doi-asserted-by":"crossref","unstructured":"Mahajan, D., Park, J., Amaro, E., Sharma, H., Yazdanbakhsh, A., Kim, J.K., Esmaeilzadeh, H.: Tabla: a unified template-based framework for accelerating statistical machine learning. In: 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 14\u201326. IEEE (2016)","DOI":"10.1109\/HPCA.2016.7446050"},{"key":"14_CR58","doi-asserted-by":"crossref","unstructured":"Mao, M., Cao, Y., Yu, S., Chakrabarti, C.: Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. In: 2015 33rd IEEE International Conference on Computer Design (ICCD), pp. 359\u2013366. IEEE (2015)","DOI":"10.1109\/ICCD.2015.7357125"},{"issue":"5","key":"14_CR59","doi-asserted-by":"publisher","first-page":"1611","DOI":"10.1109\/TVLSI.2017.2651647","volume":"25","author":"Manqing Mao","year":"2017","unstructured":"Mao, M., Chen, P.Y., Yu, S., Chakrabarti, C.: A multilayer approach to designing energy-efficient and reliable ReRAM cross-point array system. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(5), 1611\u20131621 (2017)","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"14_CR61","doi-asserted-by":"crossref","unstructured":"Mao, M., Sun, X., Peng, X., Yu, S., Chakrabarti, C.: A versatile ReRAM-based accelerator for convolutional neural networks. In: 2018 IEEE International Workshop on Signal Processing Systems (SiPS), pp. 211\u2013216. IEEE (2018a)","DOI":"10.1109\/SiPS.2018.8598372"},{"issue":"7","key":"14_CR62","doi-asserted-by":"publisher","first-page":"1290","DOI":"10.1109\/TVLSI.2018.2814544","volume":"26","author":"Manqing Mao","year":"2018","unstructured":"Mao, M., Yu, S., Chakrabarti, C.: Design and analysis of energy-efficient and reliable 3-d ReRAM cross-point array system. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(7), 1290\u20131300 (2018b)","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"14_CR60","doi-asserted-by":"crossref","unstructured":"Mao, M., Peng, X., Liu, R., Li, J., Yu, S., Chakrabarti, C.: Max2: an ReRAM-based neural network accelerator that maximizes data reuse and area utilization. IEEE J. Emerg. Sel. Top. Circuits Syst. (2019)","DOI":"10.1109\/JETCAS.2019.2908937"},{"issue":"6","key":"14_CR63","doi-asserted-by":"publisher","first-page":"1236","DOI":"10.1093\/bib\/bbx044","volume":"19","author":"R Miotto","year":"2017","unstructured":"Miotto, R., Wang, F., Wang, S., Jiang, X., Dudley, J.T.: Deep learning for healthcare: review, opportunities and challenges. Brief. Bioinform. 19(6), 1236\u20131246 (2017)","journal-title":"Brief. Bioinform."},{"key":"14_CR64","doi-asserted-by":"crossref","unstructured":"Mohanty, A., Du, X., Chen, P.Y., Seo, J.s., Yu, S., Cao, Y.: Random sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays. In: 2017 IEEE International Electron Devices Meeting (IEDM), pp. 6\u20133. IEEE (2017)","DOI":"10.1109\/IEDM.2017.8268339"},{"key":"14_CR65","unstructured":"Netzer, Y., Wang, T., Coates, A., Bissacco, A., Wu, B., Ng, A.Y.: Reading digits in natural images with unsupervised feature learning (2011)"},{"key":"14_CR66","doi-asserted-by":"crossref","unstructured":"Niu, D., Chen, Y., Xu, C., Xie, Y.: Impact of process variations on emerging memristor. In: Proceedings of the 47th Design Automation Conference, pp. 877\u2013882. ACM (2010)","DOI":"10.1145\/1837274.1837495"},{"key":"14_CR67","doi-asserted-by":"crossref","unstructured":"Niu, D., Xu, C., Muralimanohar, N., Jouppi, N.P., Xie, Y.: Design trade-offs for high density cross-point resistive memory. In: Proceedings of the 2012 ACM\/IEEE international symposium on Low power electronics and design, pp. 209\u2013214. ACM (2012)","DOI":"10.1145\/2333660.2333712"},{"key":"14_CR68","doi-asserted-by":"crossref","unstructured":"Parashar, A., Rhu, M., Mukkara, A., Puglielli, A., Venkatesan, R., Khailany, B., Emer, J., Keckler, S.W., Dally, W.J.: SCNN: an accelerator for compressed-sparse convolutional neural networks. In: 2017 ACM\/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), pp. 27\u201340. IEEE (2017)","DOI":"10.1145\/3079856.3080254"},{"key":"14_CR70","doi-asserted-by":"crossref","unstructured":"Qiu, J., Wang, J., Yao, S., Guo, K., Li, B., Zhou, E., Yu, J., Tang, T., Xu, N., Song, S., et\u00a0al.: Going deeper with embedded FPGA platform for convolutional neural network. In: Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 26\u201335. ACM (2016)","DOI":"10.1145\/2847263.2847265"},{"key":"14_CR69","doi-asserted-by":"crossref","unstructured":"Qiao, X., Cao, X., Yang, H., Song, L., Li, H.: Atomlayer: a universal ReRAM-based CNN accelerator with atomic layer computation. In: Proceedings of the 55th Annual Design Automation Conference, p. 103. ACM (2018)","DOI":"10.1145\/3195970.3195998"},{"issue":"4","key":"14_CR71","doi-asserted-by":"publisher","first-page":"474","DOI":"10.1109\/TC.2011.26","volume":"61","author":"J Rajendran","year":"2012","unstructured":"Rajendran, J., Manem, H., Karri, R., Rose, G.S.: An energy-efficient memristive threshold logic circuit. IEEE Trans. Comput. 61(4), 474\u2013487 (2012)","journal-title":"IEEE Trans. Comput."},{"key":"14_CR72","doi-asserted-by":"crossref","unstructured":"Rastegari, M., Ordonez, V., Redmon, J., Farhadi, A.: Xnor-net: Imagenet classification using binary convolutional neural networks. In: European Conference on Computer Vision, pp. 525\u2013542. Springer (2016)","DOI":"10.1007\/978-3-319-46493-0_32"},{"key":"14_CR73","unstructured":"Ren, S., He, K., Girshick, R., Sun, J.: Faster R-CNN: towards real-time object detection with region proposal networks. In: Advances in Neural Information Processing Systems, pp. 91\u201399 (2015)"},{"issue":"3","key":"14_CR74","doi-asserted-by":"publisher","first-page":"211","DOI":"10.1007\/s11263-015-0816-y","volume":"115","author":"O Russakovsky","year":"2015","unstructured":"Russakovsky, O., Deng, J., Su, H., Krause, J., Satheesh, S., Ma, S., Huang, Z., Karpathy, A., Khosla, A., Bernstein, M., et al.: Imagenet large scale visual recognition challenge. Int. J. Comput. Vis. 115(3), 211\u2013252 (2015)","journal-title":"Int. J. Comput. Vis."},{"issue":"3","key":"14_CR75","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1145\/3007787.3001139","volume":"44","author":"A Shafiee","year":"2016","unstructured":"Shafiee, A., Nag, A., Muralimanohar, N., Balasubramonian, R., Strachan, J.P., Hu, M., Williams, R.S., Srikumar, V.: Isaac: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. ACM SIGARCH Comput. Archit. News 44(3), 14\u201326 (2016)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"14_CR76","doi-asserted-by":"crossref","unstructured":"Sharma, H., Park, J., Suda, N., Lai, L., Chau, B., Chandra, V., Esmaeilzadeh, H.: Bit fusion: bit-level dynamically composable architecture for accelerating deep neural networks. In: Proceedings of the 45th Annual International Symposium on Computer Architecture, pp. 764\u2013775. IEEE Press (2018)","DOI":"10.1109\/ISCA.2018.00069"},{"key":"14_CR79","doi-asserted-by":"crossref","unstructured":"Song, L., Qian, X., Li, H., Chen, Y.: Pipelayer: a pipelined ReRAM-based accelerator for deep learning. In: 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 541\u2013552. IEEE (2017)","DOI":"10.1109\/HPCA.2017.55"},{"key":"14_CR80","doi-asserted-by":"crossref","unstructured":"Song, L., Zhuo, Y., Qian, X., Li, H., Chen, Y.: GRAPHR: accelerating graph processing using ReRAM. In: 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 531\u2013543. IEEE (2018a)","DOI":"10.1109\/HPCA.2018.00052"},{"key":"14_CR81","doi-asserted-by":"crossref","unstructured":"Song, M., Zhao, J., Hu, Y., Zhang, J., Li, T.: Prediction based execution on deep neural networks. In: 2018 ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), pp. 752\u2013763. IEEE (2018b)","DOI":"10.1109\/ISCA.2018.00068"},{"key":"14_CR77","doi-asserted-by":"crossref","unstructured":"Song, L., Chen, F., Young, S.R., Schuman, C.D., Perdue, G., Potok, T.E.: Deep learning for vertex reconstruction of neutrino-nucleus interaction events with combined energy and time data. In: ICASSP 2019\u20132019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 3882\u20133886. IEEE (2019a)","DOI":"10.1109\/ICASSP.2019.8683736"},{"key":"14_CR78","doi-asserted-by":"crossref","unstructured":"Song, L., Mao, J., Zhuo, Y., Qian, X., Li, H., Chen, Y.: Hypar: towards hybrid parallelism for deep learning accelerator array. In: 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 56\u201368. IEEE (2019b)","DOI":"10.1109\/HPCA.2019.00027"},{"key":"14_CR82","doi-asserted-by":"crossref","unstructured":"Sun, X., Peng, X., Chen, P.Y., Liu, R., Seo, J.s., Yu, S.: Fully parallel RRAM synaptic array for implementing binary neural network with (+ 1, -1) weights and (+ 1, 0) neurons. In: Proceedings of the 23rd Asia and South Pacific Design Automation Conference, pp. 574\u2013579. IEEE Press (2018a)","DOI":"10.1109\/ASPDAC.2018.8297384"},{"key":"14_CR83","doi-asserted-by":"crossref","unstructured":"Sun, X., Yin, S., Peng, X., Liu, R., Seo, J.s., Yu, S.: XNOR-RRAM: a scalable and parallel resistive synaptic architecture for binary neural networks. In: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1423\u20131428. IEEE (2018b)","DOI":"10.23919\/DATE.2018.8342235"},{"key":"14_CR84","doi-asserted-by":"crossref","unstructured":"Tang, T., Xia, L., Li, B., Wang, Y., Yang, H.: Binary convolutional neural network on RRAM. In: 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 782\u2013787. IEEE (2017)","DOI":"10.1109\/ASPDAC.2017.7858419"},{"key":"14_CR87","doi-asserted-by":"crossref","unstructured":"Wang, Y., Xu, J., Han, Y., Li, H., Li, X.: Deepburning: automatic generation of FPGA-based learning accelerators for the neural network family. In: Proceedings of the 53rd Annual Design Automation Conference, p. 110. ACM (2016)","DOI":"10.1145\/2897937.2898003"},{"key":"14_CR86","doi-asserted-by":"crossref","unstructured":"Wang, Y., Wen, W., Song, L., Li, H.H.: Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses. In: 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 776\u2013781. IEEE (2017)","DOI":"10.1109\/ASPDAC.2017.7858418"},{"key":"14_CR85","doi-asserted-by":"crossref","unstructured":"Wang, P., Ji, Y., Hong, C., Lyu, Y., Wang, D., Xie, Y.: SNRRAM: an efficient sparse neural network computation architecture based on resistive random-access memory. In: Proceedings of the 55th Annual Design Automation Conference, p. 106. ACM (2018)","DOI":"10.1145\/3195970.3196116"},{"issue":"6","key":"14_CR88","doi-asserted-by":"publisher","first-page":"1951","DOI":"10.1109\/JPROC.2012.2190369","volume":"100","author":"HSP Wong","year":"2012","unstructured":"Wong, H.S.P., Lee, H.Y., Yu, S., Chen, Y.S., Wu, Y., Chen, P.S., Lee, B., Chen, F.T., Tsai, M.J.: Metal-oxide rram. Proc. IEEE 100(6), 1951\u20131970 (2012)","journal-title":"Proc. IEEE"},{"key":"14_CR89","doi-asserted-by":"crossref","unstructured":"Woo, J., Peng, X., Yu, S.: Design considerations of selector device in cross-point RRAM array for neuromorphic computing. In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1\u20134. IEEE (2018)","DOI":"10.1109\/ISCAS.2018.8351735"},{"key":"14_CR91","doi-asserted-by":"crossref","unstructured":"Xu, C., Niu, D., Muralimanohar, N., Jouppi, N.P., Xie, Y.: Understanding the trade-offs in multi-level cell ReRAM memory design. In: 2013 50th ACM\/EDAC\/IEEE Design Automation Conference (DAC), pp. 1\u20136. IEEE (2013)","DOI":"10.1145\/2463209.2488867"},{"key":"14_CR90","doi-asserted-by":"crossref","unstructured":"Xu, C., Niu, D., Muralimanohar, N., Balasubramonian, R., Zhang, T., Yu, S., Xie, Y.: Overcoming the challenges of crossbar resistive memory architectures. In: 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pp. 476\u2013488. IEEE (2015)","DOI":"10.1109\/HPCA.2015.7056056"},{"key":"14_CR92","doi-asserted-by":"crossref","unstructured":"Yazdanbakhsh, A., Samadi, K., Kim, N.S., Esmaeilzadeh, H.: GANAX: a unified MIMD-SIMD acceleration for generative adversarial networks. In: Proceedings of the 45th Annual International Symposium on Computer Architecture, pp. 650\u2013661. IEEE Press (2018)","DOI":"10.1109\/ISCA.2018.00060"},{"issue":"8","key":"14_CR96","doi-asserted-by":"publisher","first-page":"2729","DOI":"10.1109\/TED.2011.2147791","volume":"58","author":"S Yu","year":"2011","unstructured":"Yu, S., Wu, Y., Jeyasingh, R., Kuzum, D., Wong, H.S.P.: An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation. IEEE Trans. Electron Devices 58(8), 2729\u20132737 (2011)","journal-title":"IEEE Trans. Electron Devices"},{"issue":"10","key":"14_CR97","doi-asserted-by":"publisher","first-page":"103514","DOI":"10.1063\/1.3564883","volume":"98","author":"S Yu","year":"2011","unstructured":"Yu, S., Wu, Y., Wong, H.S.P.: Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory. Appl. Phys. Lett. 98(10), 103514 (2011)","journal-title":"Appl. Phys. Lett."},{"issue":"12","key":"14_CR95","doi-asserted-by":"publisher","first-page":"1774","DOI":"10.1002\/adma.201203680","volume":"25","author":"S Yu","year":"2013","unstructured":"Yu, S., Gao, B., Fang, Z., Yu, H., Kang, J., Wong, H.S.P.: A low energy oxide-based electronic synaptic device for neuromorphic visual systems with tolerance to device variation. Adv. Mater. 25(12), 1774\u20131779 (2013)","journal-title":"Adv. Mater."},{"key":"14_CR94","doi-asserted-by":"crossref","unstructured":"Yu, S., Chen, P.Y., Cao, Y., Xia, L., Wang, Y., Wu, H.: Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect. In: 2015 IEEE International Electron Devices Meeting (IEDM), pp. 17\u20133. IEEE (2015)","DOI":"10.1109\/IEDM.2015.7409718"},{"issue":"2","key":"14_CR93","doi-asserted-by":"publisher","first-page":"548","DOI":"10.1145\/3140659.3080215","volume":"45","author":"Jiecao Yu","year":"2017","unstructured":"Yu, J., Lukefahr, A., Palframan, D., Dasika, G., Das, R., Mahlke, S.: Scalpel: customizing DNN pruning to the underlying hardware parallelism. In: ACM SIGARCH Computer Architecture News, vol.\u00a045, pp. 548\u2013560. ACM (2017)","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"14_CR98","doi-asserted-by":"crossref","unstructured":"Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., Cong, J.: Optimizing FPGA-based accelerator design for deep convolutional neural networks. In: Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 161\u2013170. ACM (2015)","DOI":"10.1145\/2684746.2689060"},{"key":"14_CR100","doi-asserted-by":"crossref","unstructured":"Zhang, C., Wu, D., Sun, J., Sun, G., Luo, G., Cong, J.: Energy-efficient cnn implementation on a deeply pipelined FPGA cluster. In: Proceedings of the 2016 International Symposium on Low Power Electronics and Design, pp. 326\u2013331. ACM (2016)","DOI":"10.1145\/2934583.2934644"},{"key":"14_CR99","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2785257","author":"C Zhang","year":"2018","unstructured":"Zhang, C., Sun, G., Fang, Z., Zhou, P., Pan, P., Cong, J.: Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. (2018). \nhttps:\/\/doi.org\/10.1109\/TCAD.2017.2785257","journal-title":"IEEE Trans. Comput. Aided Design Integr. Circuits Syst"},{"key":"14_CR101","doi-asserted-by":"crossref","unstructured":"Zokaee, F., Zhang, M., Jiang, L.: Finder: Accelerating fm-index-based exact pattern matching in genomic sequences through ReRAM technology. In: Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques. ACM (2019)","DOI":"10.1109\/PACT.2019.00030"}],"container-title":["CCF Transactions on High Performance Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s42514-019-00014-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s42514-019-00014-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s42514-019-00014-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,21]],"date-time":"2020-10-21T23:53:11Z","timestamp":1603324391000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s42514-019-00014-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10,23]]},"references-count":101,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[2019,12]]}},"alternative-id":["14"],"URL":"https:\/\/doi.org\/10.1007\/s42514-019-00014-8","relation":{},"ISSN":["2524-4922","2524-4930"],"issn-type":[{"type":"print","value":"2524-4922"},{"type":"electronic","value":"2524-4930"}],"subject":[],"published":{"date-parts":[[2019,10,23]]},"assertion":[{"value":"12 June 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"4 October 2019","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 October 2019","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Compliance with ethical standards"}},{"value":"On behalf of all authors, the corresponding author states that there is no conflict of interest.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}