{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,30]],"date-time":"2026-06-30T04:23:03Z","timestamp":1782793383840,"version":"3.54.5"},"reference-count":63,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2022,3,1]],"date-time":"2022-03-01T00:00:00Z","timestamp":1646092800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2022,3,1]],"date-time":"2022-03-01T00:00:00Z","timestamp":1646092800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["CCF Trans. HPC"],"published-print":{"date-parts":[[2022,3]]},"DOI":"10.1007\/s42514-022-00093-0","type":"journal-article","created":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T12:04:39Z","timestamp":1648728279000},"page":"43-52","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":63,"title":["Survey on chiplets: interface, interconnect and integration methodology"],"prefix":"10.1007","volume":"4","author":[{"given":"Xiaohan","family":"Ma","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5172-4736","authenticated-orcid":false,"given":"Ying","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yujie","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xuyi","family":"Cai","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yinhe","family":"Han","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2022,3,31]]},"reference":[{"key":"93_CR1","doi-asserted-by":"crossref","unstructured":"Bharadwaj, S., Yin, J., Beckmann, B., Krishna, T.: Kite: a family of heterogeneous interposer topologies enabled via accurate interconnect modeling. In: Proceedings of the 57th ACM\/IEEE Design Automation Conference, pp. 1\u20136. (2020)","DOI":"10.1109\/DAC18072.2020.9218539"},{"key":"93_CR2","unstructured":"Cadence: 3D-IC Design Solutions (2021). https:\/\/www.cadence.com\/en_US\/home\/solutions\/3dic-design-solutions.html"},{"key":"93_CR3","doi-asserted-by":"crossref","unstructured":"Carusone, A.C., Dehlaghi, B., Beerkens, R., Tonietto, D.: Ultra-short-reach interconnects for package-level integration. In: Proceedings of the IEEE Optical Interconnects Conference, pp. 10\u201311. (2016)","DOI":"10.1109\/OIC.2016.7483009"},{"key":"93_CR4","unstructured":"CCIX Consortium: Cache Coherent Interconnect for Accelerators (2017). http:\/\/www.ccixconsortium.com"},{"key":"93_CR5","unstructured":"DARPA: Common heterogeneous integration and ip reuse strategies (chips) (2021) https:\/\/www.darpa.mil\/program\/commonheterogeneous-integration-and-ip-reuse-strategies."},{"issue":"5","key":"93_CR6","doi-asserted-by":"publisher","first-page":"256","DOI":"10.1109\/JSSC.1974.1050511","volume":"9","author":"RH Dennard","year":"1974","unstructured":"Dennard, R.H., Gaensslen, F.H., Yu, H., Rideout, V.L., Bassous, E., LeBlanc, A.R.: Design of ion-implanted MOSFET\u2019s with very small physical dimensions. IEEE J. Solid State Circ. 9(5), 256\u2013268 (1974). https:\/\/doi.org\/10.1109\/JSSC.1974.1050511","journal-title":"IEEE J. Solid State Circ."},{"issue":"1","key":"93_CR7","doi-asserted-by":"publisher","first-page":"15","DOI":"10.1109\/MM.2019.2950352","volume":"40","author":"R Farjadrad","year":"2019","unstructured":"Farjadrad, R., Kuemerle, M., Vinnakota, B.: A bunch-of-wires (BoW) interface for interchiplet communication. IEEE Micro 40(1), 15\u201324 (2019)","journal-title":"IEEE Micro"},{"key":"93_CR8","unstructured":"GlobeNewswire: AMD delivers semi-custom graphics chip for new intel processor (2017). http:\/\/www.nasdaq.com\/press-release\/amd-delivers-semicustomgraphics-chip-for-new-intel-processor-20171106-00859"},{"key":"93_CR9","doi-asserted-by":"crossref","unstructured":"Gomes, W., Khushu, S., Ingerly, D.B., Stover, P.N., Chowdhury, N.I., O'Mahony, F., Balankutty, A., Dolev, N., Dixon, M.G., Jiang, L., Prekke, S.: 8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12\u00d7 12mm 2, 1mm Package-on-Package. In: Proceedings of the IEEE International Solid-State Circuits Conference, pp. 144\u2013146 (2020)","DOI":"10.1109\/ISSCC19947.2020.9062957"},{"key":"93_CR10","doi-asserted-by":"crossref","unstructured":"Hwang, R., Kim, T., Kwon, Y., Rhu, M.: Centaur: A chiplet-based, hybrid sparse-dense accelerator for personalized recommendations. In: Proceedings of the ACM\/IEEE 47th Annual International Symposium on Computer Architecture, pp. 968\u2013981. (2020)","DOI":"10.1109\/ISCA45697.2020.00083"},{"key":"93_CR11","doi-asserted-by":"publisher","unstructured":"IEEE: IEEE standard for test access architecture for three-dimensional stacked integrated circuits. (2020). https:\/\/doi.org\/10.1109\/IEEESTD.2020.9036129.","DOI":"10.1109\/IEEESTD.2020.9036129"},{"key":"93_CR12","doi-asserted-by":"crossref","unstructured":"Ingerly, D.B., Amin, S., Aryasomayajula, L., Balankutty, A., Borst, D., Chandra, A., Cheemalapati, K., Cook, C.S., Criss, R., Enamul, K., Gomes, W.: Foveros: 3D integration and the use of face-to-face chip stacking for logic devices. In: Proceedings of the IEEE International Electron Devices Meeting, pp. 19\u20136 (2019)","DOI":"10.1109\/IEDM19573.2019.8993637"},{"key":"93_CR13","unstructured":"Intel: intel\/aib-phy-hardware (2020). https:\/\/github.com\/intel\/aib-phy-hardware"},{"key":"93_CR14","unstructured":"Intel: New Intel XPU Innovations Target HPC and AI (2021). https:\/\/www.intel.com\/content\/www\/us\/en\/newsroom\/news\/new-intel-xpu-innovations-target-hpc-ai.html"},{"key":"93_CR15","unstructured":"JEDEC: High Bandwidth Memory (HBM) DRAM|JEDEC (2021). https:\/\/www.jedec.org\/standards-documents\/docs\/jesd235a"},{"key":"93_CR16","doi-asserted-by":"crossref","unstructured":"Jerger, N.E., Kannan, A., Li, Z., Loh, G.H.: Noc architectures for silicon interposer systems: why pay for more wires when you can get them (from your interposer) for free?. In: Proceedings of the 47th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 458\u2013470. (2014)","DOI":"10.1109\/MICRO.2014.61"},{"key":"93_CR17","doi-asserted-by":"crossref","unstructured":"Kabir, M.A., Peng, Y.: Chiplet-package co-design for 2.5 D systems using standard ASIC CAD tools. In: Proceedings of the 25th Asia and South Pacific Design Automation Conference, pp. 351\u2013356. (2020)","DOI":"10.1109\/ASP-DAC47756.2020.9045734"},{"key":"93_CR18","doi-asserted-by":"crossref","unstructured":"Kada, M.: Research and development history of three-dimensional integration technology. In: Three-Dimensional Integration of Semiconductors, pp. 1\u201323 (2015)","DOI":"10.1007\/978-3-319-18675-7_1"},{"key":"93_CR19","unstructured":"Kandou: XSR\/USR interface analysis including chord signaling options (2014). https:\/\/kandou.com\/assets\/downloads\/presentation-XSR-USR-Interface-Analysis-Including-Chord-Signaling-Options.pdf"},{"key":"93_CR20","doi-asserted-by":"crossref","unstructured":"Kannan, A., Jerger, N.E., Loh, G.H.: Enabling interposer-based disintegration of multi-core processors. In: Proceedings of the 48th Annual IEEE\/ACM International Symposium on Microarchitectur, pp. 546\u2013558 (2015)","DOI":"10.1145\/2830772.2830808"},{"key":"93_CR21","unstructured":"Kehlet, D.: Accelerating innovation through a standard chiplet interface: the advanced interface bus (AIB). Intel White Paper (2017)."},{"key":"93_CR22","doi-asserted-by":"crossref","unstructured":"Kim, J., Murali, G., Park, H., Qin, E., Kwon, H., Chekuri, V.C.K., Rahman, N.M., Dasari, N., Singh, A., Lee, M., Torun, H.M.: Architecture, chip, and package codesign flow for interposer-based 2.5-d chiplet integration enabling heterogeneous ip reuse. IEEE Trans Very Large Scale Integr (VLSI) Syst 28(11): 2424\u20132437 (2020)","DOI":"10.1109\/TVLSI.2020.3015494"},{"key":"93_CR23","doi-asserted-by":"crossref","unstructured":"Ko, H.G., Shin, S., Kye, C.H., Lee, S.Y., Yun, J., Jung, H.K., Lee, D., Kim, S., Jeong, D.K.: A 370-fJ\/b, 0.0056 mm 2\/DQ, 4.8-Gb\/s DQ receiver for HBM3 with a baud-rate self-tracking loop. In: Proceedings of the Symposium on VLSI Circuits, pp. C94\u2013C94. (2019)","DOI":"10.23919\/VLSIC.2019.8778082"},{"key":"93_CR24","doi-asserted-by":"crossref","unstructured":"Lan, J., Nambiar, V.P., Sabapathy, R., Dutta, R., Chong, C.T., Rotaru, M.D., Lin, K.K., Bhattacharya, S., Chai, K.T.C., Do, A.T.: An automatic chip-package co-design flow for multi-core neuromorphic computing SiPs. In: Proceedings of the IEEE 22nd Electronics Packaging Technology Conference, pp. 77\u201380. (2020)","DOI":"10.1109\/EPTC50525.2020.9315089"},{"key":"93_CR25","doi-asserted-by":"crossref","unstructured":"Lau, J. H.: Semiconductor advanced packaging. Springer (2021)","DOI":"10.1007\/978-981-16-1376-0"},{"key":"93_CR26","doi-asserted-by":"crossref","unstructured":"Lenihan, T.G., Matthew, L., Vardaman, E.J.: Developments in 2.5 D: The role of silicon interposers. In: Proceedings of the IEEE 15th Electronics Packaging Technology Conference, pp. 53\u201355. (2013)","DOI":"10.1109\/EPTC.2013.6745683"},{"issue":"4","key":"93_CR27","doi-asserted-by":"publisher","first-page":"956","DOI":"10.1109\/JSSC.2019.2960207","volume":"55","author":"MS Lin","year":"2020","unstructured":"Lin, M.S., Huang, T.C., Tsai, C.C., Tam, K.H., Hsieh, K.C.H., Chen, C.F., Huang, W.H., Hu, C.W., Chen, Y.C., Goel, S.K., Fu, C.M.: A 7-nm 4-GHz Arm1-core-based CoWoS1 chiplet design for high-performance computing. IEEE J. Solid-State Circ. 55(4), 956\u2013966 (2020)","journal-title":"IEEE J. Solid-State Circ."},{"key":"93_CR28","unstructured":"Lin, M.S., Tsai, C.C., Chang, C.H., Huang, W.H., Hsu, Y.Y., Yang, S.C., Fu, C.M., Chou, M.H., Huang, T.C., Chen, C.F., Huang, T.C.: An extra low-power 1Tbit\/s bandwidth PLL\/DLL-less eDRAM PHY using 0.3 V low-swing IO for 2.5 D CoWoS application. In: Proceedings of the Symposium on VLSI Technology, pp. C16\u2013C17 (2013)"},{"key":"93_CR29","doi-asserted-by":"crossref","unstructured":"Lin, M.S., Tsai, C.C., Hsieh, C.H., Huang, W.H., Chen, Y.C., Yang, S.C., Fu, C.M., Zhan, H.J., Chien, J.Y., Li, S.Y., Chen, Y.H.: A 16nm 256-bit wide 89.6 GByte\/s total bandwidth in-package interconnect with 0.3 V swing and 0.062 pJ\/bit power in InFO package. In: Proceedings of the IEEE Hot Chips 28 Symposium, pp. 1\u201332. (2016)","DOI":"10.1109\/HOTCHIPS.2016.7936211"},{"key":"93_CR30","doi-asserted-by":"crossref","unstructured":"Mahajan, R., Sankman, R., Patel, N., Kim, D.W., Aygun, K., Qian, Z., Mekonnen, Y., Salama, I., Sharan, S., Iyengar, D., Mallik, D.: Embedded multi-die interconnect bridge (EMIB)\u2014a high density, high bandwidth packaging interconnect. In: Proceedings of the IEEE 66th Electronic Components and Technology Conference, pp. 557\u2013565. (2016)","DOI":"10.1109\/ECTC.2016.201"},{"key":"93_CR31","unstructured":"Manusharow, M., Hasan, A., Chao, T.W. Guzy, M.: Dual die Pentium D package technology development. In: Proceedings of the 56th Electronic Components and Technology Conference, pp. 7 (2006)"},{"key":"93_CR32","doi-asserted-by":"crossref","unstructured":"Mayhew, D., Krishnan, V.: PCI Express and advanced switching: evolutionary path to building next generation interconnects. In: Proceedings of the 11th Symposium on High Performance Interconnects, pp. 21\u201329. (2003).","DOI":"10.1109\/CONECT.2003.1231473"},{"issue":"3","key":"93_CR33","doi-asserted-by":"publisher","first-page":"33","DOI":"10.1109\/N-SSC.2006.4785860","volume":"11","author":"GE Moore","year":"2006","unstructured":"Moore, G.E.: Cramming more components onto integrated circuits, reprinted from electronics. IEEE Solid State Circ. Soc. Newslett. 11(3), 33\u201335 (2006). https:\/\/doi.org\/10.1109\/N-SSC.2006.4785860","journal-title":"IEEE Solid State Circ. Soc. Newslett."},{"issue":"12","key":"93_CR34","doi-asserted-by":"publisher","first-page":"1537","DOI":"10.1109\/PROC.1964.3442","volume":"52","author":"BT Murphy","year":"1964","unstructured":"Murphy, B.T.: Cost-size optima of monolithic integrated circuits. Proc. IEEE 52(12), 1537\u20131545 (1964)","journal-title":"Proc. IEEE"},{"key":"93_CR35","unstructured":"MZ Technologies: Monozukuri-MZ Technologies Genio (2014). https:\/\/www.monozukuri.eu\/"},{"key":"93_CR36","doi-asserted-by":"crossref","unstructured":"Naffziger, S., Lepak K., Paraschou M., Subramony M.: AMD chiplet architecture for high-performance server and desktop products. In Proceedings of the IEEE International Solid- State Circuits Conference, pp. 44\u201345. (2020).","DOI":"10.1109\/ISSCC19947.2020.9063103"},{"key":"93_CR37","unstructured":"OCP: Home \u00bb Open Compute Project (2011) https:\/\/www.opencompute.org\/"},{"key":"93_CR38","unstructured":"ODSA Wiki: Server\/ODSA\u2013OpenCompute (2021). https:\/\/www.opencompute.org\/wiki\/Server\/ODSA"},{"key":"93_CR39","unstructured":"OIF: OIF (1998). https:\/\/www.oiforum.com\/"},{"key":"93_CR40","doi-asserted-by":"crossref","unstructured":"Pano, V., Kuttappa, R., Taskin, B.: 3D NoCs with active interposer for multi-die systems. In: Proceedings of the 13th IEEE\/ACM International Symposium on Networks-on-Chip, pp. 1\u20138. (2019)","DOI":"10.1145\/3313231.3352380"},{"issue":"12","key":"93_CR41","first-page":"2047","volume":"10","author":"H Park","year":"2020","unstructured":"Park, H., Kim, J., Chekuri, V.C.K., Dolatsara, M.A., Nabeel, M., Bojesomo, A., Patnaik, S., Sinanoglu, O., Swaminathan, M., Mukhopadhyay, S., Knechtel, J.: Design 25-D ICs and study of RISC-V architecture with secure NoC. IEEE Trans Comp Pack Manuf Technol 10(12), 2047\u20132060 (2020)","journal-title":"IEEE Trans Comp Pack Manuf Technol"},{"key":"93_CR42","unstructured":"Rajendiran K.: Die-to-die interface PHY and controller subsystem for next generation chiplets (2021). https:\/\/semiwiki.com\/semiconductor-services\/openfive\/298127-die-to-die-interface-phy-and-controller-subsystem-for-next-generation-chiplets\/"},{"key":"93_CR43","unstructured":"Rambus: 40G USR and C2C SerDes PHYs - Interface IP | Rambus (2021). https:\/\/www.rambus.com\/interface-ip\/serdes\/40g-usr-and-c2c-serdes-phys\/"},{"key":"93_CR44","unstructured":"Ramm, P., Franzon, P., Garrou, P., Swaminathan, R., Vivet, P., Badaroglu, M.: Heterogeneous integration and chiplet assembly\u2013all between 2D and 3D. (2020)"},{"key":"93_CR45","doi-asserted-by":"crossref","unstructured":"Rosker, M.J., Greanya, V., Chang, T.H.: The DARPA compound semiconductor materials on silicon (COSMOS) program. In: Proceedings of the IEEE Compound Semiconductor Integrated Circuits Symposium, pp. 1\u20134. (2008)","DOI":"10.1109\/CSICS.2008.6"},{"key":"93_CR46","unstructured":"Schor D.: OCP bunch of wires (2020). A new open chiplets interface for organic substrates. https:\/\/fuse.wikichip.org\/news\/3199\/ocp-bunch-of-wires-a-new-open-chiplets-interface-for-organic-substrates\/"},{"key":"93_CR47","unstructured":"Shao, Y.S., Clemons, J., Venkatesan, R., Zimmer, B., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S.G.: Simba: Scaling deep-learning inference with multi-chip-module-based architecture. In: Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 14\u201327. (2019)"},{"key":"93_CR48","unstructured":"SiFive: SiFive TileLink specification (2017). https:\/\/sifive.cdn.prismic.io\/sifive%2Fcab05224-2df1-4af8-adee-8d9cba3378cd_tilelink-spec-1.8.0.pdf"},{"issue":"4\/5","key":"93_CR49","doi-asserted-by":"publisher","first-page":"8-1","DOI":"10.1147\/JRD.2018.2856978","volume":"62","author":"J Stuecheli","year":"2018","unstructured":"Stuecheli, J., Starke, W.J., Irish, J.D., Arimilli, L.B., Dreps, D., Blaner, B., Wollbrink, C., Allison, B.: IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI. IBM J. Res. Dev. 62(4\/5), 8\u20131 (2018)","journal-title":"IBM J. Res. Dev."},{"issue":"2","key":"93_CR50","doi-asserted-by":"publisher","first-page":"45","DOI":"10.1109\/MM.2020.2974217","volume":"40","author":"D Suggs","year":"2020","unstructured":"Suggs, D., Subramony, M., Bouvier, D.: The AMD \u201cZen 2\u201d processor. IEEE Micro 40(2), 45\u201352 (2020)","journal-title":"IEEE Micro"},{"key":"93_CR51","doi-asserted-by":"crossref","unstructured":"Sunohara, M., Tokunaga, T., Kurihara, T., Higashi, M.: Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring. In: Proceedings of the 58th Electronic Components and Technology Conference, pp. 847\u2013852. (2008)","DOI":"10.1109\/ECTC.2008.4550075"},{"key":"93_CR52","unstructured":"Synopsys: 3DIC Compiler (2020). https:\/\/www.synopsys.com\/implementation-and-signoff\/3dic-design.html"},{"key":"93_CR53","unstructured":"Synopsys: DesignWare Die-to-die PHY IP solutions|Synopsys (2021). https:\/\/www.synopsys.com\/designware-ip\/interface-ip\/die-to-die.html"},{"key":"93_CR54","doi-asserted-by":"crossref","unstructured":"Tan, Z., Cai, H., Dong, R., Ma, K.: NN-Baton: DNN workload orchestration and chiplet granularity exploration for multichip accelerators. In Proceedings of the ACM\/IEEE 48th Annual International Symposium on Computer Architecture, pp. 1013\u20131026 (2021)","DOI":"10.1109\/ISCA52012.2021.00083"},{"key":"93_CR55","doi-asserted-by":"crossref","unstructured":"Van Doren, S.: HOTI 2019: compute express link. In: Proceedings of the IEEE Symposium on High-Performance Interconnects, pp. 18\u201318. (2019)","DOI":"10.1109\/HOTI.2019.00017"},{"key":"93_CR56","doi-asserted-by":"crossref","unstructured":"Vinnakota, B., Agarwal, I., Drucker, K., Jani, D., Miller, G.L., Mittal, M., Wang, R.: The open domain-specific architecture. IEEE Micro. (2020)","DOI":"10.1109\/MM.2020.3042383"},{"issue":"1","key":"93_CR57","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1109\/6144.759349","volume":"22","author":"CP Wong","year":"1999","unstructured":"Wong, C.P., Michelle, M.: Wong: recent advances in plastic packaging of flip-chip and multichip modules (MCM) of microelectronics. IEEE Trans. Compon. Packag. Technol. 22(1), 21\u201325 (1999)","journal-title":"IEEE Trans. Compon. Packag. Technol."},{"key":"93_CR58","doi-asserted-by":"crossref","unstructured":"Wang, M., Wang, Y., Liu, C., Zhang, L.: Network-on-interposer design for agile neural-network processor chip customization. In: Proceedings of 58th ACM\/IEEE Design Automation Conference (2021)","DOI":"10.1109\/DAC18074.2021.9586261"},{"key":"93_CR59","doi-asserted-by":"crossref","unstructured":"Yin, J., Lin, Z., Kayiran, O., Poremba, M., Altaf, M.S.B., Jerger, N.E., Loh, G.H.: Modular routing design for chiplet-based systems. In: Proceedings of the ACM\/IEEE 45th Annual International Symposium on Computer Architecture, pp. 726\u2013738 (2018)","DOI":"10.1109\/ISCA.2018.00066"},{"issue":"2","key":"93_CR60","doi-asserted-by":"publisher","first-page":"36","DOI":"10.1109\/MM.2020.3045564","volume":"41","author":"F Zaruba","year":"2020","unstructured":"Zaruba, F., Schuiki, F., Benini, L.: Manticore: A 4096-Core RISC-V chiplet architecture for ultraefficient floating-point computing. IEEE Micr. 41(2), 36\u201342 (2020)","journal-title":"IEEE Micr."},{"key":"93_CR61","doi-asserted-by":"crossref","unstructured":"Zheng, H., Wang, K., Louri, A.: A versatile and flexible chiplet-based system design for heterogeneous manycore architectures. In: Proceedings of the 57th ACM\/IEEE Design Automation Conference, pp. 1\u20136 (2020)","DOI":"10.1109\/DAC18072.2020.9218654"},{"key":"93_CR62","doi-asserted-by":"crossref","unstructured":"Zimmer, B., Venkatesan, R., Shao, Y.S., Clemons, J., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S.G.: A 0.11 pj\/op, 0.32\u2013128 tops, scalable multi-chip-module-based deep neural network accelerator with ground-reference signaling in 16nm. In: Proceedings of the Symposium on VLSI Circuits, pp. C300\u2013C301 (2019)","DOI":"10.23919\/VLSIC.2019.8778056"},{"issue":"4","key":"93_CR63","doi-asserted-by":"publisher","first-page":"920","DOI":"10.1109\/JSSC.2019.2960488","volume":"55","author":"B Zimmer","year":"2020","unstructured":"Zimmer, B., Venkatesan, R., Shao, Y.S., Clemons, J., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S.G.: A 0.32\u2013128 TOPS, scalable multi-chip-module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm. IEEE J Sol State Circ 55(4), 920\u2013932 (2020)","journal-title":"IEEE J Sol State Circ"}],"container-title":["CCF Transactions on High Performance Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s42514-022-00093-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s42514-022-00093-0\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s42514-022-00093-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,21]],"date-time":"2024-09-21T10:24:47Z","timestamp":1726914287000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s42514-022-00093-0"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,3]]},"references-count":63,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2022,3]]}},"alternative-id":["93"],"URL":"https:\/\/doi.org\/10.1007\/s42514-022-00093-0","relation":{},"ISSN":["2524-4922","2524-4930"],"issn-type":[{"value":"2524-4922","type":"print"},{"value":"2524-4930","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,3]]},"assertion":[{"value":"1 September 2021","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 February 2022","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"31 March 2022","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}