{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T01:03:10Z","timestamp":1773104590933,"version":"3.50.1"},"reference-count":52,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2024,12,5]],"date-time":"2024-12-05T00:00:00Z","timestamp":1733356800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0"},{"start":{"date-parts":[[2024,12,5]],"date-time":"2024-12-05T00:00:00Z","timestamp":1733356800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Int J Netw Distrib Comput"],"published-print":{"date-parts":[[2025,6]]},"DOI":"10.1007\/s44227-024-00047-8","type":"journal-article","created":{"date-parts":[[2024,12,5]],"date-time":"2024-12-05T08:15:57Z","timestamp":1733386557000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Design of a Quaternary Component and Wallace Tree Integrated Baugh-Wooley Multiplier"],"prefix":"10.1007","volume":"13","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6351-3351","authenticated-orcid":false,"given":"Kapil","family":"Juneja","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anupriya","family":"Jangra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dhiraj","family":"Khurana","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2024,12,5]]},"reference":[{"key":"47_CR1","doi-asserted-by":"crossref","unstructured":"Sjalander M, Larsson-Edefors P (2008) High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree. In: 15th IEEE international conference on electronics, circuits and systems, pp 33\u201336","DOI":"10.1109\/ICECS.2008.4674784"},{"key":"47_CR2","doi-asserted-by":"crossref","unstructured":"Bhoi BK, Misra NK, Pradhan M, Rout R (2018) Synthesis methods of Baugh-Wooley multiplier and non-restoring divider to enhance primitive\u2019s results of QCA circuits, vol 104, pp 237\u2013245","DOI":"10.1007\/978-981-13-1921-1_24"},{"key":"47_CR3","doi-asserted-by":"crossref","unstructured":"Xiong X, Lin M (2012) Low power 8-bit Baugh-Wooley multiplier based on Wallace tree architecture. In: Emerging trends in computing, informatics, systems sciences and engineering; lecture notes in electrical engineering, vol 151, pp 851\u2013865","DOI":"10.1007\/978-1-4614-3558-7_73"},{"key":"47_CR4","doi-asserted-by":"publisher","DOI":"10.1007\/s42452-020-2595-5","author":"AA Gudivada","year":"2020","unstructured":"Gudivada AA, Sudha GF (2020) Design of Baugh-Wooley multiplier in quantum-dot cellular automata using a novel 1-bit full adder with power dissipation analysis. SN Appl Sci. https:\/\/doi.org\/10.1007\/s42452-020-2595-5","journal-title":"SN Appl Sci"},{"key":"47_CR5","doi-asserted-by":"crossref","unstructured":"Biradar VB, Vishwas PG, Chetan CS, Premananda BS (2017) Design and performance analysis of modified unsigned braun and signed Baugh-Wooley multiplier. In: International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), pp 1\u20136","DOI":"10.1109\/ICEECCOT.2017.8284612"},{"key":"47_CR6","doi-asserted-by":"crossref","unstructured":"Asati A, Chandrashekhar (2008) An improved high speed fully pipelined 500 MHz 8\u00d78 Baugh Wooley multiplier design using 0.6 \u03bcm CMOS TSPC logic design style. In: Third international conference on industrial and information systems, pp 1\u20136","DOI":"10.1109\/ICIINFS.2008.4798406"},{"key":"47_CR7","doi-asserted-by":"crossref","unstructured":"Muley VS, Tom A, Vigneswaran T (2015) Design of Baugh Wooley and Wallace tree multiplier using two phase clocked adibatic static CMOS logic. In: International Conference on Industrial Instrumentation and Control (ICIC), pp 1178\u20131183","DOI":"10.1109\/IIC.2015.7150926"},{"key":"47_CR8","doi-asserted-by":"crossref","unstructured":"Premananda B, Bhargav U, Vineeth KS (2018) Design and analysis of compact QCA based 4-bit serial-parallel multiplier. In: International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), pp 1014\u20131018","DOI":"10.1109\/ICEECCOT43722.2018.9001619"},{"key":"47_CR9","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1155\/2013\/495354","volume":"2013","author":"B Ramkumar","year":"2013","unstructured":"Ramkumar B, Kittur HM (2013) Faster and energy-efficient signed multipliers. VLSI Des 2013:1\u201312","journal-title":"VLSI Des"},{"key":"47_CR10","doi-asserted-by":"crossref","unstructured":"Tu SH-L, Yen C-H (2006) A high-speed Baugh-Wooley multiplier design using skew-tolerant domino techniques. In: IEEE Asia Pacific conference on circuits and systems, pp 598\u2013601","DOI":"10.1109\/APCCAS.2006.342059"},{"key":"47_CR11","doi-asserted-by":"publisher","first-page":"187","DOI":"10.1023\/A:1023604700591","volume":"35","author":"C-Y Pai","year":"2003","unstructured":"Pai C-Y, Al-Khalili A, Lynch W (2003) Low-power constant-coefficient multiplier generator. J VLSI Signal Process Syst Signal Image Video Technol 35:187\u2013194","journal-title":"J VLSI Signal Process Syst Signal Image Video Technol"},{"key":"47_CR12","doi-asserted-by":"crossref","unstructured":"Warrier R, Vun C, Zhang W (2014) A low-power pipelined MAC architecture using Baugh-Wooley based multiplier. In: IEEE 3rd Global Conference on Consumer Electronics (GCCE), pp 505\u2013506","DOI":"10.1109\/GCCE.2014.7031169"},{"issue":"10","key":"47_CR13","doi-asserted-by":"publisher","first-page":"1346","DOI":"10.1109\/TC.2009.89","volume":"58","author":"J-H Tu","year":"2009","unstructured":"Tu J-H, Van L-D (2009) Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers. IEEE Trans Comput 58(10):1346\u20131355","journal-title":"IEEE Trans Comput"},{"key":"47_CR14","doi-asserted-by":"crossref","unstructured":"Abraham S, Kaur S, Singh S (2015) Study of various high speed multipliers. In: International Conference on Computer Communication and Informatics (ICCCI), pp 1\u20135","DOI":"10.1109\/ICCCI.2015.7218139"},{"key":"47_CR15","doi-asserted-by":"crossref","unstructured":"Akhter S, Chaturvedi S (2014) HDL based implementation of N\u00d7N bit-serial multiplier. In: International Conference on Signal Processing and Integrated Networks (SPIN), pp 470\u2013474","DOI":"10.1109\/SPIN.2014.6776999"},{"key":"47_CR16","doi-asserted-by":"crossref","unstructured":"Singh KN, Tarunkumar H (2015) A review on various multipliers designs in VLSI. In: Annual IEEE India Conference (INDICON), pp 1\u20134","DOI":"10.1109\/INDICON.2015.7443420"},{"key":"47_CR17","first-page":"1","volume":"3","author":"P Mohanty","year":"2012","unstructured":"Mohanty P, Rajan R (2012) An efficient Baugh-Wooley architecture for both signed & unsigned multiplication. Int J Comput Sci Eng Technol 3:1\u20135","journal-title":"Int J Comput Sci Eng Technol"},{"key":"47_CR18","doi-asserted-by":"crossref","unstructured":"Mukherjee A, Asati A (2013) Generic modified Baugh Wooley multiplier. In: International conference on circuits, power and computing technologies, pp 1\u20135","DOI":"10.1109\/ICCPCT.2013.6529021"},{"key":"47_CR19","doi-asserted-by":"crossref","unstructured":"Lamba B, Sharma A (2018) A review paper on different multipliers based on their different performance parameters. In: 2nd International Conference on Inventive Systems and Control (ICISC), pp 324\u2013327","DOI":"10.1109\/ICISC.2018.8399088"},{"key":"47_CR20","doi-asserted-by":"publisher","first-page":"1179","DOI":"10.1016\/j.proeng.2012.01.978","volume":"30","author":"L Rajaa","year":"2012","unstructured":"Rajaa L, Prabhu BM, Thanushkodi K (2012) Design of low power digital multiplier using dual threshold voltage adder module. Procedia Eng 30:1179\u20131186","journal-title":"Procedia Eng"},{"key":"47_CR21","doi-asserted-by":"publisher","first-page":"1455","DOI":"10.1007\/s00542-019-04678-8","volume":"26","author":"P Paliwal","year":"2020","unstructured":"Paliwal P, Sharma JB, Nath V (2020) Comparative study of FFA architectures using different multiplier and adder topologies. Microsyst Technol 26:1455\u20131462","journal-title":"Microsyst Technol"},{"key":"47_CR22","doi-asserted-by":"publisher","first-page":"3549","DOI":"10.1007\/s11277-017-5028-z","volume":"98","author":"GS Tomar","year":"2018","unstructured":"Tomar GS, George ML (2018) Modified binary multiplier architecture to achieve reduced latency and hardware utilization. Wirel Pers Commun 98:3549\u20133561","journal-title":"Wirel Pers Commun"},{"key":"47_CR23","doi-asserted-by":"crossref","unstructured":"Renxi G, Shangjun Z, Hainan Z, Xiaobi M, Wenying G, Lingling X, Yan H (2009) Hardware implementation of a high speed floating point multiplier based on FPGA. In: 4th international conference on computer science & education, pp 1902\u20131906","DOI":"10.1109\/ICCSE.2009.5228240"},{"key":"47_CR24","doi-asserted-by":"publisher","first-page":"149","DOI":"10.1023\/A:1008013818413","volume":"19","author":"L Song","year":"1998","unstructured":"Song L, Parhi KK (1998) Low-energy digit-serial\/parallel finite field multipliers. J VLSI Signal Process Syst Signal Image Video Technol 19:149\u2013166","journal-title":"J VLSI Signal Process Syst Signal Image Video Technol"},{"key":"47_CR25","doi-asserted-by":"crossref","unstructured":"Sabbagh S, Baseri J (2014) Optimization of serial-serial multiplier and implementation of a 4-bit multiplier. In: 22nd Iranian Conference on Electrical Engineering (ICEE), pp 476\u2013479","DOI":"10.1109\/IranianCEE.2014.6999588"},{"key":"47_CR26","doi-asserted-by":"crossref","unstructured":"Yugandhar K, Raja VG, Tejkumar M, Siva D (2018) High performance array multiplier using reversible logic structure. In: International Conference on Current Trends towards Converging Technologies (ICCTCT), pp 1\u20135","DOI":"10.1109\/ICCTCT.2018.8550872"},{"key":"#cr-split#-47_CR27.1","doi-asserted-by":"crossref","unstructured":"Hosseiny A, Amanollahi S, Hashemi R, Jahanian A (2013) Improved performance and resource usage of FPGA using resource-aware design","DOI":"10.1109\/CADS.2013.6714248"},{"key":"#cr-split#-47_CR27.2","unstructured":"the case of a decimal array multiplier. In: 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013), pp 121-122"},{"key":"47_CR28","doi-asserted-by":"publisher","first-page":"108119","DOI":"10.1109\/ACCESS.2021.3100892","volume":"9","author":"S Raveendran","year":"2021","unstructured":"Raveendran S, Edavoor PJ, Kumar YN, Vasantha MH (2021) Inexact signed Wallace tree multiplier design using reversible logic. IEEE Access 9:108119\u2013108130","journal-title":"IEEE Access"},{"key":"47_CR29","doi-asserted-by":"crossref","unstructured":"Pudi V, Sridharan K (2013) Efficient design of Baugh-Wooley multiplier in quantum-dot cellular automata. In: 13th IEEE international conference on nanotechnology, pp 702\u2013706","DOI":"10.1109\/NANO.2013.6721006"},{"key":"47_CR30","doi-asserted-by":"crossref","unstructured":"Bajaj R, Chhabra S, Veeramachaneni S, Srinivas MB (2009) A novel; low-power array multiplier architecture. In: 9th international symposium on communications and information technology, pp 119\u2013123","DOI":"10.1109\/ISCIT.2009.5341273"},{"key":"47_CR31","doi-asserted-by":"crossref","unstructured":"Das D, Rahaman H (2010) A novel signed array multiplier. In: International conference on advances in computer engineering, pp 19\u201323","DOI":"10.1109\/ACE.2010.29"},{"key":"47_CR32","doi-asserted-by":"crossref","unstructured":"Di J, Yuan J (2003) Run-time reconfigurable power-aware pipelined signed array multiplier design. In: International symposium on signals, circuits and systems, vol 2, pp 405\u2013408 2003","DOI":"10.1109\/SCS.2003.1227075"},{"key":"47_CR33","doi-asserted-by":"crossref","unstructured":"Bansal M, Nakhate S, Somkuwar A (2011) High performance pipelined signed 64\u00d764-bit multiplier using Radix-32 modified Booth algorithm and Wallace structure. In: International conference on computational intelligence and communication networks, pp 411\u2013415","DOI":"10.1109\/CICN.2011.86"},{"key":"47_CR34","doi-asserted-by":"crossref","unstructured":"Rajput RP, Swamy MS (2012) High speed modified Booth encoder multiplier for signed and unsigned numbers. In: 14th international conference on computer modelling and simulation, pp 649\u2013654","DOI":"10.1109\/UKSim.2012.99"},{"key":"47_CR35","doi-asserted-by":"crossref","unstructured":"Saokar SS, Banakar RM, Siddamal S (2012) High speed signed multiplier for digital signal processing applications. In: IEEE international conference on signal processing, computing and control, pp 1\u20136","DOI":"10.1109\/ISPCC.2012.6224373"},{"key":"47_CR36","doi-asserted-by":"crossref","unstructured":"Vakili S (2024) A cost-effective Baugh-Wooley approximate multiplier for FPGA-based machine learning computing. In: 6th International Conference on AI Circuits and Systems (AICAS)","DOI":"10.1109\/AICAS59952.2024.10595892"},{"key":"47_CR37","doi-asserted-by":"crossref","unstructured":"Kishore P, Sirimalla R, Sushma KS, Reddy RS (2023) Implementation of braun and Baugh-Wooley multipliers using qca. In: 2nd International Conference for Innovation in Technology (INOCON)","DOI":"10.1109\/INOCON57975.2023.10101300"},{"issue":"1","key":"47_CR38","first-page":"3092","volume":"15","author":"C Pakkiraiah","year":"2024","unstructured":"Pakkiraiah C, Lakshmi AHNSV, Sucharita K, Raghuveer J (2024) Design and implementation of low power Baugh Wooley multiplier using reversible circuits. J Nonlinear Anal Optim 15(1):3092\u20133102","journal-title":"J Nonlinear Anal Optim"},{"issue":"2","key":"47_CR39","first-page":"285","volume":"14","author":"KS Raj","year":"2023","unstructured":"Raj KS, Kumar PR, Satyanarayana M (2023) Baugh-Wooley multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates. Int Rev Appl Sci Eng 14(2):285\u2013292","journal-title":"Int Rev Appl Sci Eng"},{"key":"47_CR40","doi-asserted-by":"crossref","unstructured":"Kishore P, Akash B, Aditya G, Harika N (2024) Design and analysis of low power and high-speed Baugh Wooley multiplier using modified gate diffusion input technique. In: 3rd International Conference for Innovation in Technology (INOCON)","DOI":"10.1109\/INOCON60754.2024.10512080"},{"issue":"6","key":"47_CR41","doi-asserted-by":"publisher","first-page":"3748","DOI":"10.1007\/s00034-024-02630-4","volume":"43","author":"SK Beura","year":"2024","unstructured":"Beura SK, Devi BP, Saha PK, Meher PK (2024) Design of a Novel Inexact 4: 2 compressor and its placement in the partial product array for area, delay, and power-efficient approximate multipliers. Circuits Syst Signal Process 43(6):3748\u20133774","journal-title":"Circuits Syst Signal Process"},{"issue":"1","key":"47_CR42","doi-asserted-by":"publisher","first-page":"8492","DOI":"10.1038\/s41598-024-58482-0","volume":"14","author":"V Thamizharasan","year":"2024","unstructured":"Thamizharasan V, Parthipan V (2024) Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation. Sci Rep 14(1):8492","journal-title":"Sci Rep"},{"key":"47_CR43","doi-asserted-by":"publisher","first-page":"103054","DOI":"10.1016\/j.micpro.2020.103054","volume":"75","author":"V Muralidharan","year":"2020","unstructured":"Muralidharan V, Kumar NS (2020) Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder. Microprocess Microsyst 75:103054","journal-title":"Microprocess Microsyst"},{"key":"47_CR44","doi-asserted-by":"crossref","unstructured":"Ganavi MG, Premananda BS (2020) Design of low power reduced complexity Wallace tree multiplier using positive feedback adiabatic logic. In: Advanced computing and intelligent engineering, pp 139\u2013150","DOI":"10.1007\/978-981-15-1483-8_13"},{"key":"47_CR45","doi-asserted-by":"crossref","unstructured":"Pudi V, Sridharan K (2013) Efficient design of Baugh-Wooley multiplier in quantum-dot cellular automata. In: 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013)","DOI":"10.1109\/NANO.2013.6721006"},{"issue":"1","key":"47_CR46","first-page":"68","volume":"9","author":"H Faraji","year":"2018","unstructured":"Faraji H, Mosleh M (2018) A fast wallace-based parallel multiplier in quantum-dot cellular automata. Int J Nano Dimens 9(1):68\u201378","journal-title":"Int J Nano Dimens"},{"key":"47_CR47","doi-asserted-by":"crossref","unstructured":"Hanninen I, Takala J (2009) Radix-4 recoded multiplier on quantum-dot cellular automata. In: International workshop on embedded computer systems, Berlin","DOI":"10.1007\/978-3-642-03138-0_13"},{"key":"47_CR48","doi-asserted-by":"crossref","unstructured":"Pala V, Makhe V, Bhuva K, Parekh R (2022) RTL to GDSII flow implementation of 8-bit Baugh-Wooley multiplier. In: IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO)","DOI":"10.1109\/5NANO53044.2022.9828876"},{"key":"47_CR49","doi-asserted-by":"crossref","unstructured":"Rampeesa A, Akhila P, Irfan M, Rebelli S, Thoutam LR, Ajayan J (2022) Design of low power 4-bit Baugh-Wooley multiplier using 1-bit mirror and approximate full adders. In: 2nd Asian Conference on Innovation in Technology (ASIANCON)","DOI":"10.1109\/ASIANCON55314.2022.9908919"},{"key":"47_CR50","doi-asserted-by":"crossref","unstructured":"Ponugoti V, Oruganti S, Poloju S, Bopidi S (2021)\"Design of Baugh-Wooley multiplier using full swing GDI technique. In: International conference on soft computing and signal processing","DOI":"10.1007\/978-981-16-7088-6_71"},{"key":"47_CR51","doi-asserted-by":"crossref","unstructured":"Haridas K, Sreehari KN, Chalil A (2021) Performance comparison of Radix-2 FFT butterfly unit with Baugh Wooley and modified Baugh Wooley. In: Second International Conference on Electronics and Sustainable Communication Systems (ICESC)","DOI":"10.1109\/ICESC51422.2021.9532681"}],"container-title":["International Journal of Networked and Distributed Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s44227-024-00047-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s44227-024-00047-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s44227-024-00047-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,6]],"date-time":"2025-09-06T00:56:54Z","timestamp":1757120214000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s44227-024-00047-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,5]]},"references-count":52,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2025,6]]}},"alternative-id":["47"],"URL":"https:\/\/doi.org\/10.1007\/s44227-024-00047-8","relation":{},"ISSN":["2211-7938","2211-7946"],"issn-type":[{"value":"2211-7938","type":"print"},{"value":"2211-7946","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,12,5]]},"assertion":[{"value":"16 July 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"26 September 2024","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"5 December 2024","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"There are no conflict of interest, financial or others. On behalf of all the authors, I ensure ethics approval and participation in the research.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}},{"value":"Not applicable.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethics Approval and Consent to Participate"}},{"value":"Not applicable.","order":4,"name":"Ethics","group":{"name":"EthicsHeading","label":"Consent for Publication"}}],"article-number":"3"}}