{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T13:05:30Z","timestamp":1725455130307},"publisher-location":"Berlin\/Heidelberg","reference-count":20,"publisher":"Springer-Verlag","isbn-type":[{"type":"print","value":"1402031270"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/1-4020-3128-9_10","type":"book-chapter","created":{"date-parts":[[2005,10,20]],"date-time":"2005-10-20T21:28:08Z","timestamp":1129843688000},"page":"117-129","source":"Crossref","is-referenced-by-count":5,"title":["Run-time Defragmentation for Dynamically Reconfigurable Hardware"],"prefix":"10.1007","author":[{"given":"Manuel G.","family":"Gericota","sequence":"first","affiliation":[]},{"given":"Gustavo R.","family":"Alves","sequence":"additional","affiliation":[]},{"given":"Miguel L.","family":"Silva","sequence":"additional","affiliation":[]},{"given":"Jos\u00e9 M.","family":"Ferreira","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"1","key":"10_CR1","doi-asserted-by":"publisher","first-page":"210","DOI":"10.1109\/92.920836","volume":"9","author":"E. Cant\u00f3","year":"2001","unstructured":"Cant\u00f3, E., J. M. Moreno, J. Cabestany, I. Lacadena, and J. M. Insenser. (2001). \u201cA Temporal Bipartitioning Algorithm for Dynamically Reconfigurable FPGAs,\u201d IEEE Trans. on VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 210\u2013218.","journal-title":"IEEE Trans. on VLSI Systems"},{"key":"10_CR2","unstructured":"Cardoso, J. M. P., and H. C. Neto. (1999). \u201cAn Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs,\u201d Proc. 10th Intl. Conf. on VLSI, pp. 485\u2013496."},{"issue":"3","key":"10_CR3","doi-asserted-by":"publisher","first-page":"209","DOI":"10.1109\/TVLSI.2002.1043324","volume":"10","author":"C. K","year":"2002","unstructured":"Compton, K., Z. Li, J. Cooley, S. Knol, and S. Hauck. (2002). \u201cConfiguration, Relocation and Defragmentation for Run-Time Reconfigurable Computing,\u201d IEEE Trans. on VLSI Systems, Vol. 10, No. 3, June 2002, pp. 209\u2013220.","journal-title":"IEEE Trans. on VLSI Systems"},{"issue":"3","key":"10_CR4","doi-asserted-by":"publisher","first-page":"181","DOI":"10.1049\/ip-cdt:20000485","volume":"147","author":"O. Diessel","year":"2000","unstructured":"Diessel, O., H. El Gindy, M. Middendorf, H. Schmeck, and B. Schmidt. (2000). \u201cDynamic scheduling of tasks on partially reconfigurable FPGAs,\u201d IEE Proc.-Computer Digital Technology, Vol. 147, No. 3, May 2000, pp. 181\u2013188.","journal-title":"IEE Proc.-Computer Digital Technology"},{"key":"10_CR5","doi-asserted-by":"crossref","unstructured":"Gericota, M. G., G. R. Alves, M. L. Silva, and J. M. Ferreira. (2002). \u201cOn-line Defragmentation for Run-Time Partially Reconfigurable FPGAs.\u201d In Glesner, M., Zipf, P., and Renovell, M., editors, Proc. 12th Intl. Conf. Field Programmable Logic and Applications: Reconfigurable Computing is Going Mainstream, Lecture Notes in Computer Science 2438, pp. 302\u2013311. Springer.","DOI":"10.1007\/3-540-46117-5_32"},{"key":"10_CR6","doi-asserted-by":"crossref","unstructured":"Gericota, M. G., G. R. Alves, M. L. Silva, and J. M. Ferreira. (2003). \u201cRun-Time Management of Logic Resources on Reconfigurable Systems,\u201d Proc. Design, Automation and Test in Europe, pp. 974\u2013979.","DOI":"10.1109\/DATE.2003.1253731"},{"issue":"8","key":"10_CR7","doi-asserted-by":"publisher","first-page":"849","DOI":"10.1109\/43.644609","volume":"16","author":"S. Hauck","year":"1997","unstructured":"Hauck, S., and G. Borriello. (1997). \u201cAn Evaluation of Bipartitioning Techniques,\u201d IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, Vol. 16, No. 8, Aug. 1997, pp. 849\u2013866.","journal-title":"IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems"},{"key":"10_CR8","doi-asserted-by":"crossref","unstructured":"Huang, W., and E. J. McCluskey. (2001). \u201cA Memory Coherence Technique for Online Transient Error Recovery of FPGA Configurations,\u201d Proc. 9th ACM Intl. Symp. Field Programmable Gate Arrays, pp. 183\u2013192.","DOI":"10.1145\/360276.360344"},{"key":"10_CR9","doi-asserted-by":"crossref","unstructured":"Jeong, B., S. Yoo, S. Lee, and K. Choi. (2000). \u201cHardware-Software Cosynthesis for Run-time Incrementally Reconfigurable FPGAs,\u201d Proc. 2000 Asia South Pacific Design Automation Conf., pp. 169\u2013174.","DOI":"10.1145\/368434.368598"},{"key":"10_CR10","unstructured":"Kaul, M., and R. Vemuri. (1999). \u201cTemporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs,\u201d Proc. Design, Automation and Test in Europe, pp. 202\u2013209."},{"key":"10_CR11","doi-asserted-by":"crossref","unstructured":"Li, Z., and S. Hauck. (2002). \u201cConfiguration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation,\u201d Proc. 10th ACM Int. Symp. Field-Programmable Gate Arrays, pp. 187\u2013195.","DOI":"10.1145\/503048.503076"},{"key":"10_CR12","doi-asserted-by":"crossref","unstructured":"Long, X. P., and H. Amano. (1993). \u201cWASMII: a Data Driven Computer on a Virtual Hardware,\u201d Proc. 1st IEEE Workshop on FPGAs for Custom Computing Machines, pp. 33\u201342.","DOI":"10.1109\/FPGA.1993.279481"},{"issue":"1","key":"10_CR13","doi-asserted-by":"publisher","first-page":"173","DOI":"10.1109\/92.920831","volume":"9","author":"R. Maestre","year":"2001","unstructured":"Maestre, R., F. J. Kurdahi, R. Hermida, N. Bagherzadeh, and H. Singh. (2001). \u201cA Formal Approach to Context Scheduling for Multicontext Reconfigurable Architectures,\u201d IEEE Trans. on VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 173\u2013185.","journal-title":"IEEE Trans. on VLSI Systems"},{"key":"10_CR14","unstructured":"Mei\u00dfner, M., S. Grimm, W. Stra\u00dfer, J. Packer, and D. Latimer. (2001). \u201cParallel Volume Rendering on a Single-Chip SIMD Architecture,\u201d Proc. IEEE Symp. on Parallel and Large-data Visualization and Graphics, pp. 107\u2013113."},{"key":"10_CR15","doi-asserted-by":"crossref","unstructured":"Sanchez-Elez, M., M. Fernandez, R. Maestre, R. Hermida, N. Bagherzadeh, and F. J. Kurdahi. (2002). \u201cA Complete Data Scheduler for Multi-Context Reconfigurable Architectures,\u201d Proc. Design, Automation and Test in Europe, pp. 547\u2013552.","DOI":"10.1109\/DATE.2002.998354"},{"issue":"5","key":"10_CR16","doi-asserted-by":"publisher","first-page":"465","DOI":"10.1109\/12.859540","volume":"49","author":"H. Singh","year":"2000","unstructured":"Singh, H., M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho. (2000). \u201cMorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications,\u201d IEEE Trans. on Computers, Vol. 49, No. 5, May 2000, pp. 465\u2013481.","journal-title":"IEEE Trans. on Computers"},{"key":"10_CR17","unstructured":"Teich, M., S. Fekete, and J. Schepers. (1999). \u201cCompile-time optimization of dynamic hardware reconfigurations,\u201d Proc. Intl. Conf. on Parallel and Distributed Processing Techniques and Applications, pp. 1097\u20131103."},{"key":"10_CR18","doi-asserted-by":"crossref","unstructured":"Trimberger, S. (1998). \u201cScheduling designs into a time-multiplexed FPGA,\u201d Proc. Int. Symp. Field Programmable Gate Arrays, pp. 153\u2013160.","DOI":"10.1145\/275107.275135"},{"key":"10_CR19","doi-asserted-by":"crossref","unstructured":"Vasilko, M. (1999). \u201cDYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems,\u201d Proc. 9th Intl.Workshop on Field-Programmable Logic and Applications, pp. 124\u2013133.","DOI":"10.1007\/978-3-540-48302-1_13"},{"key":"10_CR20","unstructured":"\u201cThe Programmable Logic Data Book,\u201d Xilinx, Inc., 2002."}],"container-title":["New Algorithms, Architectures and Applications for Reconfigurable Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/1-4020-3128-9_10.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T07:51:19Z","timestamp":1619509879000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/1-4020-3128-9_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["1402031270"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/1-4020-3128-9_10","relation":{},"subject":[]}}